Institut f ur Integrierte Systeme

Integrated Systems Laboratory

Analog Integrated Circuits
Exercise 4: Common-Source and Differential Ampliers
Luca Bettini ETZ J64.2, Schekeb Fateh ETZ J64.2, Ren e Blattmann ETZ J64.2
Hand out: 16.11.2012
Hand in: 30.11.2012
The exercise takes place in room ETZ D61.2 on 16
th
November and 23
rd
November 2012.
The exercise starts at 13:15 and ends at 15:00. For the course attendance certicate (Tes-
tat), solutions to all problems have to be handed in by the 30
th
of November.
Requirements to obtain the course attendance certicate: Reasonable solutions have to be handed
in. We are primarily expecting your hand calculations and design considerations. Afew important
plots and annotated schematics from Cadence should be handed in as well. Problems marked as
optional are not mandatory for the testat.
1 Introduction
The amplication of analog signals is a vital task in analog circuits. Signals must be amplied to drive a
given load or to t into a given range, e.g. for A/D conversion, but, most of all, because amplication is
fundamental in any feedback system. During the rst part of this exercise we will examine the simplest
amplier stage, i.e. the common-source (CS) amplier, from a theoretical point of view. In the second
part of the exercise we will investigate, the effect of different types of loads on the stage response by
means of Cadence simulations. Finally, the last part of the exercise is dedicated to the analysis and
simulation of a simple differential amplier. For your hand calculations, use the long-channel equations
to describe the MOSFET transistor and refer to the technological parameters reported in the Appendix.
2 Common-Source Amplier
The basic common-source amplier is depicted in Fig. 1a. The MOS transistor M1 converts variations of
the input voltage V
i
to a small-signal drain current. This small-signal drain current then passes through
the drain resistor R
D
and the voltage drop translates to the output voltage V
o
. However, recall that
the small-signal input voltage v
i
must be small compared to the input voltage operating point V
I
. This
allows us to linearize the inherent non-linear circuit in (V
I
, V
O
) and postulate that v
o
= A
v
v
i
where A
v
is a constant for a given (V
I
, V
O
) and where V
i
= V
I
+ v
i
and V
o
= V
O
+ v
o
. Note that the AC analysis
in Cadence works in the same way: the simulator just linearizes the circuit in the operating point! It is
up to the user to check whether the linear model is still valid for a certain input signal amplitude!
V
DD
V
o
R
D
V
DD
M2
M1 M1
V
DD
M2
M1
V
B
V
i
V
i
V
i
V
o
V
o
(a) (b) (c)
Figure 1: Three variants of the common-source amplier.
2.1 Numerical Exercise
Consider the circuit in Figure 2. The current source I = I
B
+ i
AC
cos(t) consists of a DC or biasing
component I
B
and an AC signal component i
AC
= 10 A. Without the signal component (i.e. i
AC
= 0),
the voltage drop across R
L
is 0.5 V.
I = I
B
+ i
AC
cos(t)
V
2
V
1
M
2
M
1
R
L
= 1 k
W
1
= 5 m
L
1
= 1 m
V
DD
= 3.3 V
W
2
= 20 m
L
2
= 1 m
Figure 2: Schematic of the CS amplier togheter with its bias circuit.
1. Determine the DC load current I
L
and the DC bias component I
B
.
2. Determine the large-signal node voltages V
1
and V
2
.
2
3. Draw a small-signal AC equivalent circuit model of Figure 2, replacing transistors M
1
and M
2
each by a simple 3-element (C
GS{1,2}
, g
m{1,2}
, and r
out{1,2}
) model.
4. Compute the small-signal parameters C
GS{1,2}
, g
m{1,2}
, and r
out{1,2}
.
The reletionship between the input current signal i
AC
and the corresponding voltage signal v
1
generated
on node N
1
can be described by the transfer function:
H(s) =
v
1
i
AC
=
1
g
m1
1
_
1 + s
C
GS1
+C
GS2
g
m1
_
5. Draw the Bode plot of H(s) and calculate its dominant pole. Remember that, as H(s) is function
of the complex variable s, the diagrams of magnitude and phase must always be both drawn.
6. Determine the transfer function G(s) = v
2
/i
AC
.
7. Determine the small-signal voltage gain A
v
= v
2
/v
1
. Provide a meaningful approximation in-
stead of an accurate result.
8. Determine v
1
(t) as a function of i
AC
(t) at 10 kHz.
9. To what extent can A
v
be increased by modifying the bias current I
B
? Calculate the new bias
current I
B
which leads to the maximum achievable gain A
v
.
The resistance R
L
in Figure 2 is replaced by an ideal current source as shown in Figure 3, while the
DC operating point of V
2
is maintained at 1.7 V by netuning the ratio between I
B
and I
L
. Answer the
following questions:
V
2 V
1
M
2 M
1
W
1
= 5 m
L
1
= 1 m
W
2
= 20 m
L
2
= 1 m
I
B
I
L
V
DD
= 3.3 V
Figure 3: Schematic of the CS amplier with active load.
10. Determine A
v
= v
2
/v
1
if I
B
= 1 mA and I
L
= 4 mA.
11. Determine L
2
if A
v
is to be doubled.
3
2.2 Cadence Exercise
As we have seen in the rst part of the numerical exercise, CS ampliers can employ a simple resistor
as a load. However, in standard CMOS processes it is difcult to fabricate resistors with an acceptable
accuracy at a reasonable physical size. Therefore, it is desirable to replace the drain resistor R
D
in
Fig. 1a by a MOSFET. Fig. 1b and 1c show two possibilities:
Fig. 1b uses a diode-connected PMOS as an active load.
Fig. 1c uses a PMOS current source as an active load. Note that a suitable bias voltage V
B
must be
provided here, and the output node must be properly ne-tuned to guarantee its proper operating
point.
1. Create a directory uebung4. Change into that directory and start Cadence with
icdesign ams-hk3.70 -tech c35b3 &.
2. Create a new library (e.g. MyLibrary) in the Library Manager and a new cell commonsource
with the view schematic.
3. Draw a schematic according to Fig. 1 containing the three versions of the simple common source
amplier.
4. First we are going to analyze the small-signal behavior of the common-source ampliers. For each
variant of Fig. 1, draw the small-signal equivalent circuit and subsequently derive an expression
for the small-signal voltage gain A
v
=
vo
v
i
! For the circuits (a) and (b), derive an expression
including the transistor output resistances and a simplied expression where they are neglected.
As we only consider frequencies near DC, you may neglect the capacitances associated with the
transistors.
5. Design the common-source ampliers (a), (b), and (c) such that |A
v
| 5. Choose I
D
= 100 A.
Moreover, set L
1
= 0.35 m and W
1
= 3.5 m, and make use of the following hints: Design (a)
and (b) such that A
v
= 5. Estimate A
v
for (c) if you assume
n
= 0.1 V
1
and
p
= 0.2 V
1
.
For (b) use L
2
= 2 m. For (c) use L
2
= 0.35 m and choose V
dsat2
= 200 mV.
6. Enter the design values into the schematic and perform a DC sweep of V
i
from 0 V to 3.3 V.
Hint: import the variables from the schematic into Analog Environment; set Viadc=Vidc,
Vibdc=Vidc, Vicdc=Vidc, and sweep Vidc. Plot the output voltages Voa, Vob, and Voc as
a function of V
i
in a single plot. The resulting plot should be handed in for the course attendance
certicate.
(a) Explain why V
o
(V
i
= 0) does not attain V
DD
for the diode-connected load.
(b) Which variant is most preferable given your plot?
7. Determine a suitable input voltage operating point for each variant such that the maximum output
voltage swing for positive and negative amplitudes is about the same.
(a) Estimate A
v
at the determined operating point for each variant. Use marker A and B to do
so. Provide an explanation why variant (a) does not attain the required A
v
.
4
(b) Make |A
v
| 5.0 for variant (a) and variant (b). Vary R
D
and W
2
to achieve this. Thereby,
you may have to adjust the operating points such that the maximum output voltage swing
for positive and negative amplitudes remains about the same. Continue with the new R
D
,
W
2
, and operating points.
8. Perform an ACanalysis to plot A
v
as a function of the operating point: Set Viac=1m, then choose
AC analysis and click on Design Variable. Set a frequency of 1 Hz and, as in the DC case, sweep
Vidc from 0 V to 3.3 V. Run the AC analysis. Plot A
v
of circuit (a), (b), and (c) in a single plot.
A
v
of circuit (a) is e.g. given by the expression abs((VF("/Voa")) / (VF("/Via"))).
9. Perform a transient analysis to plot the small-signal output voltage v
o
from 0 to 5 s: Set the small-
signal input voltage amplitude to 5 mV and its frequency to 1 Hz by using the variables Vitr and
freq, respectively. Run the simulation and plot the voltages Vooa, Voob, and Vooc in a single
plot. The voltages Vooa, Voob, and Vooc are DC-decoupled through C
C
from the drain of M1
and designate the small-signal voltages v
o
for circuit (a), (b), and (c), respectively. The value of
C
C
has to be chosen high enough to provide a transfer function of magnitude 1 between Vo and
Voo for f = 1 Hz.
10. Repeat the transient analysis for Vitr=150m.
(a) How does the non-linear resistance of the diode-connected MOSFET affect the output volt-
age waveform?
(b) Find a way to plot g
m2
as a function of the input voltage V
i
.
11. Repeat the transient analysis for Vitr=250m. For all circuit variants, what do you obtain?
3 Differential Amplier (Optional)
The differential pair depicted in Fig. 4 is an important building block of operational ampliers as we will
see in exercise 5. The differential pair offers several advantages over the single-ended common-source
amplier. A differential signal is the difference between two signals that have equal but opposite
small-signal amplitudes around a common potential. Both the input signal and the output signal of the
circuit in Fig. 4 are differential and can thus be written as follows:
V
i
= V
i1
V
i2
= (V
I
+ v
i1
) (V
I
+ v
i2
) = v
i1
v
i2
= v
id
/2 (v
id
/2) = v
id
V
o
= V
o1
V
o2
= (V
O
+ v
o1
) (V
O
+ v
o2
) = v
o1
v
o2
= v
od
/2 (v
od
/2) = v
od
It is clear from the above equations that the input and output signals are immune against common-mode
variations. Common-mode variations may e.g. occur due to environmental noise or due to a noisy
supply voltage. This immunity against common-mode variations is essentially achieved through the tail
current source I
SS
. A further advantage of differential ampliers is the doubled maximum voltage swing
compared to single-ended ampliers.
5
Figure 4: Differential pair.
In the following problems you will analyze rst the large-signal behavior and then the small-signal
behavior of the differential pair depicted in Fig. 4.
1. Determine the maximum voltage swing of V
o1,2
disregarding any non-zero saturation voltage of
M1, M2, and the tail current source! Hint: have a look at the two cases (a) M1 fully on, M2 fully
off, and (b) vice versa.
2. Derive a lower limit for V
o1,2
to keep the transistors M1 and M2 in saturation given the input
common-mode voltage V
I
! You may neglect the small-signal voltages v
i1,2
here as we assume
them to be small compared to V
I
. How should you choose the input common-mode voltage V
I
in
order to maximize the possible output voltage swing: high?, low?
3. Before we are going to dimension the circuit of Fig. 4 we also need to perform a small-signal
analysis. Due to the symmetry of the circuit, the voltage V
p
remains constant. Therefore, we can
consider point P an AC ground. Apply the half-circuit concept and derive the differential voltage
amplication A
v
=
v
od
v
id
.
4. Now we are in a position to dimension the differential pair. Assume V
DD
= 3.3 V, I
SS
= 200 A,
A
v
= 5, L
1,2
= 0.35 m, and W
1,2
= 3.5 m. A good choice to dene the input common-
mode voltage is
V
I
= V
p
+ V
GS1,2
+ V
safteymargin
Note that the tail current-source will be a MOSFET M3 in a real circuit. Set V
p
= 1.5 V
dsat3
and
choose V
dsat3
= 200 mV. V
safetymargin
should be set to 100 mV to assure that the tail current
source is in saturation despite the errors made in our hand calculations for V
GS1,2
. Calculate V
I
and R
D
!
5. Draw the schematic of the circuit.
6
6. Enter the design values into the schematic and perform a DC sweep of v
id
from -1 V to 1 V!
Hint: import the variables from the schematic into Analog Environment and sweep Vid. Adjust
the drain resistors such that A
v
5.0 in the operating point! Then plot the voltages v
od
, V
o1
,
V
o2
, and V
p
as a function of v
id
in a single plot! Do the same for the currents I
d1
and I
d2
! The
resulting plots should be handed in for the testat.
7. The half-circuit concept postulates that the tail current source I
SS
can be replaced by a voltage
source of value V
p
. We would like to conrm this with the simulator. A schematic with the
half-circuit should be designed by yourself. Import the variables from the schematic into Analog
Environment and set Vidc, Vp, and the value of R
D
according to the DC simulation of the full
differential pair. Verify with a DC sweep of Vi whether A
v
remains at about -5.0!
8. A possible load for the differential pair would be a source-follower. A source-follower may be
modeled by a load capacitance C
L
when viewed from the node V
o1
as depicted in Fig. 5.
(a) Draw the small-signal equivalent circuit of Fig. 5 and derive the analytical expression of the
3 dB frequency f
3dB
for the output voltage v
o1
, (i.e.the frequency for which v
o1
is 3 dB
smaller than at DC!).
(b) Calculate the 3 dB frequency for a load capacitance of 1 pF, 100 fF, and 10 fF! Hint: deter-
mine the exact value of r
o
from a DC operating point analysis in Cadence.
(c) Now determine the 3 dB frequency for C
L
= 1 pF, 100 fF, and 10 fF from three AC analyses
with Cadence! Sweep the frequency over a reasonable range for each capacitance and plot
v
o1
to conveniently read out f
3dB
.
(d) Compare the calculated and simulated 3 dB frequencies for C
L
= 1 pF, 100 fF, and 10 fF!
Explain the result!
R
D
M1
V
i1
V
o1
r
o
V
DD
C
L
V
p
Figure 5: Half-circuit of differential pair with load capacitance C
L
.
7
4 Appendix
Transistor equations (valid in saturation region only)
I
DS
=
k

[n,p]
2
W
L
_
V
GS
V
TH[n,p]
_
2
=
_
positive for NFET
negative for PFET
k

[n,p]
=
e[n,p]
C
ox
V
TH[n,p]
= V
TH0[n,p]
+
[n,p]
_
_

2
F[n,p]
V
BS

2
F[n,p]

_
g
m
= k

[n,p]
W
L
_
V
GS
V
TH[n,p]
_
=
_
2k

[n,p]
W
L
I
DS
=
2I
DS
V
GS
V
TH[n,p]
r
out
=
L

[n,p]
I
DS

[n,p]
= L
[n,p]
C
GS
=
2
3
WLC
ox
C
ox
=

ox
t
ox
V
DSAT
= V
GS
V
TH[n,p]
8
Transistor parameters
3.3 V NFET 3.3 V PFET
k

n
170 A/V
2
k

p
58 A/V
2
V
TH0n
0.50 V V
TH0p
0.65 V

n
0.58 V
1/2

p
0.40 V
1/2

Fn
0.44 V
Fp
0.42 V

n
0.0875 m/V

p
0.0875 m/V
NFET and PFET

ox
34.53 pF/m t
ox
7.6 nm
Table 1: Typical process parameters for the AMS C35 FETs.
9