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8 V- 100 MHz CMOS Programmable Gain Amplifier

B. Calvo, S. Celma, P. A. Martnez and M. T. Sanz
Group of Electronic Design University of Zaragoza E-50009 Zaragoza, Spain {becalvo, scelma, pemar2, materesa}@unizar.es
AbstractThis paper presents a low-voltage low-power differential programmable gain amplifier (PGA) for wideband applications. The proposed cell is based on a gm-boosted source degenerated differential pair with a hybrid polysilicon-MOS resistor degeneration structure. Fabricated in a 0.35 m CMOS technology, the PGA consumes less than 0.5 mW at a single 1.8 V supply. Measured results for a 3-bit implementation show a 0 to 18 dB linear-in-dB programmable gain with a constant bandwidth of 100 MHz when driving 150 fF capacitive loads. Distortion levels are below -72 dB over the whole gain range at 10 MHz for a 0.2 Vp-p differential output.

Analog filter PGA A/D DSP D AGC

Fig. 1: Block diagram of an analog front-end

I.

INTRODUCTION

Programmable gain amplifiers (PGA) are basic building blocks employed in many applications in order to optimize the dynamic range of the overall system. Hard-disk-drive (HDD) read/write channels [1, 2] and virtually all wireless communication systems [3, 4, 5] are paradigmatic examples where amplitude equalization is an essential part of the linear signal processing. Fig. 1 shows a typical arrangement for a PGA in an analog front-end. The gain of the PGA is usually digitally controlled by an automatic gain control (AGC) loop. Gain control computation is performed by a digital signal processor (DSP). To achieve a constant settling time of the AGC loop a linear-in-dB gain control for the PGA is required [6]. To obtain the best overall performance, the PGA design is clearly demanding in terms of bandwidth and distortion. First of all, it is desirable that the PGA does not limit the frequency operation of the overall system. On the other hand, its distortion specifications are low in order to preserve good system linearity. In addition, the market has pushed the industry to the implementation of monolithic CMOS circuits to improve reliability and trim time-to-market. Therefore, low voltage circuit design techniques are mandatory, also often constrained to low power consumption. In CMOS technology, designing a low voltage PGA with wide bandwidth, high linearity and acceptable power consumption is a real challenge. There are mainly two approaches for the implementation of variable gain circuits: negative feedback closed-loop configurations and open-loop amplifiers. A closed-loop archit

architecture exhibits better linearity and may allow a better control of gain and accuracy. However, a large amount of power consumption is usually required for an acceptable amplifier performance, particularly in terms of bandwidth. This architectural choice thus involves a trade-off between gain range, bandwidth, linearity and power dissipation. On the other hand, open-loop amplifiers are suitable for low power and broadband applications, but the open-loop nature of the circuit makes the linearity depend heavily on the inherent linearity of the input stage. Therefore, the use of linearization schemes is often required. The most widespread open-loop variable gain amplifiers are based on simple differential or pseudo-differential pairs [7], source degeneration techniques [8, 9], analog multipliers [10, 11] and differential pairs with diode connected loads [4]. This paper describes a differential programmable gain amplifier with a single supply voltage of 1.8 V in a standard 0.35 m CMOS technology. It is based on a very simple widely tunable differential pair degenerated with a combined MOS-polysilicon resistor network, so that a good trade-off between power dissipation, linearity, bandwidth and area consumption will be achieved. Both the circuit principle and the degeneration scheme are discussed in Section 2. The PGA main performances are summarized in Section 3. Finally, some conclusions are presented. II. A. PGA ARCHITECTURE

Differential Amplifier Architecture The proposed differential programmable gain amplifier is based on the conceptual scheme shown in Fig. 2. It is a negative feedback gm-boosted source degenerated differential pair with resistive loads.

0-7803-9390-2/06/$20.00 2006 IEEE

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ISCAS 2006

M1
RL + Vout + Vin IB IB RL Vin

R0 R1

M1 ai

M1 2R

M1

Vout

Ri Rn MSi Ri 4 Ri 2 MSi Ri 4

M2

M2

M2

M2

Fig. 3: Programmable degeneration resistor network configuration Fig. 2: PGA conceptual scheme

Focusing on the transconductor core, it is a source follower where the current through transistor M1 is held constant [12, 13]. Transistors M1-M2 form a two-pole negative-feedback loop that reduces the equivalent source resistance of the input voltage buffer M1 down to 50 , value approximately given by 1 ( g m1ro1 g m 2 ) , where all parameters have their usual meaning. Consequently, for a sourcedegenerated pair exploiting this approach, the differential transconductance can be expressed as R , where denotes the M1 gate-to-source DC voltage gain, which is somewhat less than unity due to the body effect, and R denotes one-half the degeneration resistance. The simplicity of this modified differential pair makes it very attractive for high-frequency and low-voltage operation, conditions we are interested in. The linearized differential signal current -copied out by loading each M2 gate terminal with a matched NMOS device- is converted to voltage through load resistors RL. Thereby, the differential gain of this stage is given by

For low-voltage operation, the common solution is the use of programmable arrays of passive resistors. High linearity and dynamic range have been achieved with this approach. Unfortunately, extensive area is needed to guarantee accuracy, and the operating frequency can be limited by the presence of switches in the signal path. To preserve good linearity and moderate area consumption we have adopted an approach combining linear polysilicon resistors and MOS transistors biased in the triode region, which act simultaneously as resistors and switches. Following this strategy, the proposed degeneration scheme is shown in Fig. 3. The minimum gain setting is imposed by the fixed high resistivity polysilicon (HRP) resistor Ro. The gain is then digitally controlled by adding in parallel a new linear resistor in series with two MSi NMOS switches biased in the triode region, whose on-resistance is one half of the total impedance. C. PGA implementation The complete PGA schematic, indicating transistor sizes and the bias current value, is shown in Fig. 4. Designed in a 0.35 m CMOS process, is supplied at a single voltage of 1.8 V, with a common-mode voltage of 1.3 V. The programmable degeneration impedance consists of a 3-bit array of hybrid HRP-NMOS resistors in parallel, weighted to obtain a logarithmic gain distribution ranging from 0 to 18 dB in 6 dB steps through a thermometer code control. This impedance can be scaled so as to obtain a specified gain distribution. Alternatively, a previous stage, such as an analog multiplier, can be included to provide fine control. Then, the coarse control, with gain steps of 6 dB or more, will be carried out by the proposed PGA. The 0 dB gain setting is settled by the ratio of two HRP resistors. Therefore, high accuracy can be achieved. For the rest of the gain settings, fine gain tuning is performed through slight gate voltage variations for the switching transistors in order to improve the accuracy, if necessary. In particular, 1.6-1.8 V gate voltage variations allow a 10% fine gain tuning without degrading the linearity. To generate a suitable common-mode output voltage (VCM), a current source is added to each output node. Transistors MC in the schematic, biased in the triode region, control these additional current sources that establish VCM.

Gain =

RL R

(1)

The amplifier gain can be selected either by using a variable degeneration or load resistor. However, it is preferably implemented using a variable degeneration resistor while maintaining a constant load resistor. This choice, adopted in this work, results in a fixed dominant pole at the PGA output nodes, and thus a constant bandwidth is maintained throughout all the gain stages [9]. For high-frequency applications, noise specifications limit the value of the load and degeneration resistors to the k range. Hence, RL=10 k has been chosen. Further, polysilicon resistive loads RL have been implemented so as not to degrade the linearity performance. B. Degeneration scheme The simplest variable degeneration resistor is based on the parallel connection of a switched array of MOS transistors biased in the triode region. The resulting topology is very compact in terms of silicon area. However, the linearity performance and tuning capability of this approach is limited by the modern supply voltages.

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1.8 V

M3

M3
2.25/0.5

M3
9/0.5

M3

R0
IB M1
10/0.5

IB /4 10 A IB
40

RL + Vout M2

10 k

IB M1 2R VCM - 1 vin
2

RL Vout M2 M2 M2 Mc vb vref
2(W/L) (W/L)

a0
(W/L)

vb M2 vref
1/3

VCM + 1 vin
2

a1 a2

0.75/0.35

M2

M2
3/0.35

2(W/L)

Mc

Mc

4(W/L)

4(W/L)

(a) Figure 4: PGA detailed schematic: (a) core and (b) programmable degeneration impedance

(b)

III.

PGA PERFORMANCES

The photograph of the implemented 0.35 m CMOS PGA is shown in Fig. 5. It includes a calibration circuit for the measurement of the gain characteristic at high frequency in spite of the I/O parasitic elements. The main performances are summarized in Table 1. It consumes less than 0.5 mW from a single 1.8 V supply. The gain increases linearly in a dB-scale from 0 to 18 dB in 6 dB steps, as shown in Fig. 6, which reproduces the frequency responses for the main gain settings. The measured bandwidth is kept constant around 100 MHz assuming at the two outputs capacitive loads of 150 fF. The total harmonic distortion (THD) figures are below 72 dB over all the gain setting range for a signal frequency of 10 MHz with a differential output signal level of 0.2 Vp-p, value that increases to -60 dB for 0.4 Vp-p.
Fig. 6: PGA frequency response
-50

PGA core

calibration circuit
THD, 10 MHz (dB)
-60

0 dB 18 dB

Fig. 5: Microphotograph of the PGA TABLE I SUMMARY OF PGA PERFORMANCES

12 dB 6 dB
-70

Technology Supply voltage Gain range, 3 bits Gain accuracy, 0 dB Bandwidth THD@ 10MHz, 0.2 Vp-p out In-band noise @ 0 dB Quiescent power Area

0.35 m CMOS 1.8 V 0-18 dB, 6 dB steps 0.05 dB 100 MHz < -72 dB 51 nV/Hz 0.42 mW 0.004 mm2

-80 0.0 0.2 0.4 0.6 differential output (Vpp) 0.8

Fig. 7: THD levels at 10 MHz for all gain settings

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TABLE II COMPARISON OF SEVERAL PGAS PERFORMANCES

Design CMOS process (m) Supply voltage (V) Power dissipation (mW) Gain range (dB) -3 dB BW (MHz) Linearity at 10 MHz Vpp-out/Vsupply THD (dB) Area (mm2)

[8], 1996 0.5 5 5 -2 to 12 15 0.2 -60 0.175

[14], 2003 0.35 3.3 6.4 0 to 19 125 0.6 -74 0.18

[15], 2001 0.25 2.5 2.7 5.6 to 17 100 0.56 -67 0.038

This work
0.35 1.8 0.23 0 to 18 100 0.2 -60 0.004

The worst case distortion values are determined by the 0 dB gain setting, corresponding to the larger input signal levels. Note that the THD results for the 12 and 18 dB-gain slightly degrade with respect to those obtained for a 6 dB gain, even though the associated input signal levels are smaller. This is due to the fact that for the higher gains, the value of the total degeneration resistor lowers, thus modulating the linearity of the voltage-to-current conversion. Finally, the main performances of the proposed design are compared in Table 2 with several previous realisations: references [8], [14] and [15], all using switched banks of linear polysilicon resistors to obtain a similar gain range. The presented circuit has a bandwidth just as large as other published PGAs for similar technologies at a lower supply voltage of 1.8 V and with significantly lower power consumption and area. On the other hand, with our design as well as with [9], also based on a gm-boosted degenerated differential pair linearity is limited by the open loop nature of the amplifier structure. The configurations described in [11] and [12] use amplifiers operating in closed loop with a resistor network feedback, thus obtaining better distortion levels, at the cost of higher power consumption. IV. CONCLUSIONS A low-voltage 3-bit programmable gain amplifier has successfully been implemented in a 0.35 m CMOS process showing a good trade off between power consumption, maximum operating frequency and linearity. Measurement results for a simple general purpose PGA show a wide constant bandwidth over the 100 MHz range with distortion figures below -72 dB. This cell can be the basis for highgain multiple-stage PGAs fitting the specifications of many applications, such as disk drivers, communication receivers, subscriber lines, etc. Furthermore, the design can be easily migrated to a 0.18 m 1.8-V CMOS process. ACKNOWLEDGMENT This work has been partially supported by DGA-FSE (T51/2005) and MCYT-FEDER (TIC2002-00636).

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