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148 IEEE ELECTRON DEVICE LETTERS, VOL. 19, NO. 5, MAY 1998

Reliable Extraction of MOS Interface Traps from Low-Frequency CV Measurements

A. Pacelli, Student Member, IEEE, A. L. Lacaita, Senior Member, IEEE, S. Villa, and L. Perron
Abstract An improved version of the low-frequency capacitancevoltage (LFCV) method for MOS interface trap extraction is presented. The rising edge of the gate-channel capacitance is used as a reliable reference for determining the surface potential, allowing a more accurate calculation of the trap energy. Also, a self-consistent Schr odingerPoisson solver is employed to obtain a theoretical CV curve, accounting for quantization effects. It is shown that the improved method supplies better results than the conventional LFCV and highlow frequency methods. Index Terms Capacitance measurements, MOS interface traps, quantization effects, surface potential, trap energy.

II. EXTRACTION TECHNIQUE The LFCV technique consists of two steps [3], [4]. First, the surface potential , dened as the potential drop between the substrate and the Si/SiO interface, is obtained by integration of the gate capacitance, that is (1) is the gate voltage, is the total low-frequency where is the oxide capacitance measured at the gate, and capacitance. After the relation has been determined, the interface-trap capacitance can be obtained from a split-CV measurement [4] as (2) where is the inversion-layer capacitance, dened as the derivative of the inversion charge with respect to the surface potential, and is the gate-channel capacitance. The conventional LFCV method suffers in practice from several limitations. Fringe effects and overlap capacitances can be an important source of error. Also, most practical devices exhibit polysilicon gate depletion, with an associated voltage drop inside the gate. To account for these effects, (1) must be replaced by

I. INTRODUCTION RAPS at the Si/SiO interface play an important role in determining the threshold voltage, inversion-layer mobility, and low-frequency noise of MOSFETs. Proper device modeling requires the knowledge of the density of interface states throughout the bandgap, rather than the average density of states at midgap as often reported. However, several widely used experimental methods (e.g., triangularwave charge pumping [1]) rely on the ShockleyHallRead (SHR) theory for the determination of the trap energies. If a separate measurement of the energy-dependent capture cross sections is not performed, this approach may lead to signicant errors [2]. A more direct measurement of the trap energy is possible by integration of the low-frequency gate capacitance [3]. Unfortunately, this technique is based on a very simplied physical model. Aggressive scaling, instead, brings about such effects as electron quantization and polysilicon-gate depletion, which make the conventional chargeintegration method unsuitable for the characterization of realistic devices. This letter presents an improved version of the lowfrequency capacitancevoltage (LFCV) technique [3], [4], which signicantly extends the range of applicability of the method. A robust procedure is employed to determine the integration constant in the calculation of the surface potential, while an accurate physical model is used to obtain a theoretical CV curve, properly accounting for quantization effects. The technique represents a substantial advance over the conventional LFCV and highlow frequency methods for fast and reliable characterization of MOS interface traps.
Manuscript received July 3, 1997; revised November 4, 1997. This work was supported by Italian Ministry of University and Scientic Research (MURST) and Italian National Research Council (CNR). The authors are with the Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano I-20133, Italy. Publisher Item Identier S 0741-3106(98)03306-0.

(3) The parasitic capacitance in (3) is often markedly nonlinear, therefore the improvement is partial unless is accurately measured or computed for all bias points. Also, the correction for the polysilicon voltage drop (typically 100200 mV from accumulation to inversion) cannot always be very accurate, since in practice only an effective doping concentration inside the polysilicon can be measured [5]. We nally note that the error due to the neglect of the polysilicon series capacitance in (2) is of the order of a few percent at most, since in the near-threshold regime the polysilicon depletion is still weak and the series capacitance is much higher than the oxide capacitance. The calculation of requires the precise knowledge of the surface potential at some gate voltage . Usually, a bias point in strong inversion or accumulation is used, where the surface potential is known with good accuracy [3], [6], [7]. As an alternative, the at-band voltage [8],

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PACELLI et al.: RELIABLE EXTRACTION OF MOS INTERFACE TRAPS FROM LFCV MEASUREMENTS 149

steep rising edge between 1.0 and 1.3 V, corresponding to the onset of strong inversion, can be used as a common reference for the theoretical and experimental curves. Therefore, we assume that the surface potential is the same for the two curves when reaches a xed fraction of the oxide capacitance . This assumption is valid with excellent accuracy if the trap capacitance is smaller than , which is certainly the case for device-grade oxides. It was veried on several samples that the factor can be varied from 0.5 to 0.8 without affecting the result signicantly. An additional advantage of the technique is that the probe frequency need not be as low as in the case when accumulation or at bands are taken as a reference [11], since the slow electron traps around midgap do not enter the charge integration of (3).
Fig. 1. Crosses: measured gate-channel capacitance Cgc . Solid line: simulated capacitance. Dash-dot line: position of the Fermi level with respect to the conduction bandedge, from the numerical simulation.

III. EXPERIMENTAL RESULTS The solid line in Fig. 2 shows the experimental interface state density extracted from the LFCV data of Fig. 1, using (2) and (3) with the improved method for the calculation . For all the results of Figs. 2 of the integration constant was approximated by a constant value. At the and 3, measurement frequency of 1 kHz, assuming a capture cross cm , the method can detect electron traps in section of 10 the upper half of the bandgap, starting about 0.45 eV below the conduction band. The upper limit of validity is given by the point where the inversion capacitance becomes [4], that is, around V for comparable with the simulated curve of Fig. 1. The gure also shows on the right-hand axis the position of the Fermi level, as obtained from the numerical simulation. At a gate voltage of 0.9 V, the Fermi level lies about 0.2 eV below the conduction band. Above this energy, the extracted value of can be affected by inaccuracies in the modeling of the inversion capacitance in (2). To illustrate this point, the dashed line in Fig. 2 shows the trap density obtained by taking into account the effect of interfacial nonuniformities [11]. These effects were modeled as a Gaussian uctuation of the threshold voltage. The rms amplitude of the uctuation (85 mV) was obtained by an empirical tting, assuming the worst case (i.e., the largest uctuation consistent with the experimental data). The discrepancy between the two results denes the largest error that can be expected, and conrms the good accuracy of the method over an energy range of about 300 meV. The curve shown as crosses in Fig. 2 was obtained by introducing an intentional error of 10% in the substrate doping concentration, still maintaining an excellent match. In fact, the calculation based on (2) and (3) only depends on the local behavior of the curve at threshold, which is very weakly affected by changes in the doping prole. A negligible error was also observed by introducing articial errors in the oxide thickness and polysilicon doping. Fig. 3 compares the result of the improved LFCV method (solid line) with the results of other techniques. The triangles represent the result of a trap extraction using the conventional method for the surface-potential calculation [3], neglecting the polysilicon voltage drop in (3). The reference point was taken at V, i.e., about 2 V above threshold. A

or the point where the surface becomes intrinsic [4] may be used. However, it is clear from (3) that the larger is and , the larger is the effect the difference between and . For most practical purposes, only traps of in the minority-carrier side of the bandgap are of interest close to inversion). These considerations, along (i.e., for with the well-known difculties in the accurate determination of the at-band voltage, discourage the use of a reference at at bands or in accumulation. Even when a voltage , the conventional method point in inversion is chosen as is still affected by an important inaccuracy, due to channel quantization. In fact, heavy doping of the substrate leads to a narrowing of the potential well at the silicon/oxide interface and to a splitting of the electron states. With current values of substrate doping of the order of 10 10 cm , an error of is made if the classical model is assumed 50100 mV on [9], affecting (3) directly. For the above reasons, we have modied the conventional LFCV technique in two respects. First, the surface potential and inversion capacitance have been obtained from a selfconsistent solution of the coupled Schr odinger and Poisson equations [10], thus accounting for quantization effects. The simulation also includes the effect of gate polysilicon deplefrom the numerical tion, allowing the direct estimation of simulation. The doping concentration in the polysilicon is determined from an experimental technique such as that of [5], while the oxide thickness is obtained by tting the theoretical curve to the experimental data in the strong inversion region (not shown in Fig. 1). This procedure is more accurate than approximating the oxide capacitance with the measured capacitance in strong inversion or accumulation, since the series capacitances of the gate and substrate are also taken into account. The second modication of the LFCV technique regards the determination of the integration constant in (3). As discussed above, to reduce the error to a minimum, a reference voltage close to threshold must be used. Fig. 1 compares the (crosses) with the experimental gate-channel capacitance theoretical result (solid line), for a p-substrate MOS capacitor cm and a 12-nm oxide. The with channel doping n-polysilicon gate doping was estimated as cm . The

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150 IEEE ELECTRON DEVICE LETTERS, VOL. 19, NO. 5, MAY 1998

a quasi-static and a 1-MHz curve [8]. The method detects traps that do not respond to the high-frequency probe signal. Assuming an electron capture cross section of 10 cm , from SHR theory we obtain that at 300 K, the response frequency equals the 1-MHz probe frequency at an energy 270 meV below the conduction-band edge [8]. For traps closer to the band, the probe is in fact a low-frequency signal. This causes the substantial underestimation of above 0.3 eV which is observed in Fig. 3. It must be remarked that this limitation cannot be overcome by increasing the CV measurement frequency, because both the frequency response of the inversion layer and the experimental apparatus limit the maximum frequency to a few megahertz [11]. Therefore, the split HLCV method is limited either to a relatively narrow energy range around midgap, or to cryogenic measurements.
Fig. 2. Solid line: density of interface states obtained from the improved LFCV method, shown as a function of energy with respect to the conduction band-edge Ec . Dashed line: density of interface states, also accounting for interfacial nonuniformities. Crosses: result obtained with the improved method, when an intentional error of 10% is introduced in the doping concentration.

IV. CONCLUSIONS In this paper we have shown that the low-frequency CV technique is an effective way of determining the interface trap density of large-area MOS devices. To achieve this goal, we have introduced a better physical model, accounting for quantization effects, and a more accurate calculation of the surface potential, based on the rising edge of the inversion capacitance. The method is not sensitive to errors in the doping prole, and may be applied to cases when fringe effects and polysilicon gate depletion make other techniques unusable. ACKNOWLEDGMENT The authors would like to thank SGS-Thomson Microelectronics, Agrate Brianza, Italy, for supplying the samples, and P. Penati for experimental work. REFERENCES

Fig. 3. Solid line: result obtained from the improved LFCV method (same as the solid line in Fig. 2). ( ) LFCV result not including polysilicon voltage drop, and using a conventional calculation of the surface potential. ( ) Not including poly voltage drop, but with the improved method for computing s . ( ) LFCV result obtained from the improved method for the calculation of s , but without accounting for quantum effects. ( ) Density of interface states from the high-low frequency CV method.

large horizontal distortion of the trap density can be observed, . For comparison, the curve mostly due to the effect of shown as circles was also obtained neglecting , but using the improved method for the determination of . The good agreement with the more accurate result conrms the robustness of the technique with respect to nonidealities of the device. The result shown as squares in Fig. 3 was obtained from the LFCV procedure described in Section II, but without accounting for channel quantization. The neglect of the nite electron eigenenergies results in a corresponding shift toward midgap, and to an overestimation of the trap density by about a factor of two. Therefore, we may conclude that, while the and is largely reduced, the modeling of impact of quantization effects is critical to this technique. Finally, the crosses in Fig. 3 represent the result of a highlow frequency split-CV measurement (HLCV), using

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