Professional Documents
Culture Documents
nd
Semester 2004
Table of contents:
Initializing the LCD 4.2.1 4.2.2 Data from Keyboard to the LCD 4.2.3 Data from ALU to the LCD
All the modules are programmed on ALTERA flex10k card in VERILOG. The picture below shows the different parts of the project.
LCD
ALTERA Flex10k
PAD
padQ
4 8
LCDout
PAD Module
NOT_IRQ
16
Num
5
op
update_result
ALU Module
ALUout
LCD Module
32 reset 8
DB
RS
R_W
Under the integration plan we made, the Keypad module had to submit a steady LCD decoded number or operation as it pressed, and a steady data of the number coded in binary form, stored in a register for the ALU use. For acknowledgment of the ALU that a number is ready for use, there is an OP (operation) register that his outputs represent the chosen operation of the user. Those OP outputs activate the ALU.
Operation. IRQ an interrupt that is produced when a key is pressed on the keypad. used by the LCD module.
The interrupt is produced as long as a key is pressed. The difficulty was that the padQ signal is going to '0' for one clock period, every 4 clock cycles. The pressing period is much longer than a clock period and thats causes hundreds of seemingly pressings. The solution implemented by using a counter that counts 4 clock periods, and than checks if the key is still pressed. Floating diagram: For each clock
if reset was pressed
no
yes
if IRQ = '1'
no
no
yes
counter = 1
incline counter
2.5. Enables
This logical description is the positive edge detector on the IRQ signal. It produces different Enables to the different modules. The Accumulator is enabled by 'dly1' and OP is enabled by 'dly2'.
Accumulator En(1)
OP En(2)
IRQ
reg1
reg2
dly1
dly2
clk
clk
clk
clk
Pin no. 1 - 16 17 18 19 20 21 22 23 24 25 - 56
Signal Input 16 bits integer input from PAD module. equal 1 bit signal from PAD module. ADD 1 bit signal from PAD module. MUL 1 bit signal from PAD module. SUB 1 bit signal from PAD module. DIV 1 bit signal from PAD module. CLK 1 bit clock signal from. Reset 1 bit hardware reset. IRQ 1 bit signal, when high signals to LCD module that Result is ready. Result 32 bits holding result of ALU.
ALU module
3.2
The ALU module has two, 16 bits, registers to hold input numbers from PAD module. When one of the signals ADD, MUL, SUB or DIV is detected high, the first input number .is stored and the action request is stored in one bit register When equal request is detected high, the second input number is stored and after one clock delay the result is stored in result register. One clock cycle after result is stored IRQ signal is posted high for two clock cycles to notify LCD module that the result is .ready to display
The first row located in the address 80h-8Fh. The second row is in the address C0h-CFh. Move to specific address by writing the address into command register (RS = 0). In the LCD are two registers: command reg. (RS = 0) and data register (RS = 1).
LCD module
4.2
The LCD module builds from three parts: Initializing, Data from Keyboard and Data from ALU. The all three parts are in the same module and selected by Reset or IRQ .request
Pins assignment
Pin Name Pin Number clk. 91 reset ..29 Z[0].................................................................................................................................. 83 Z[1].. 84 Z[2].. 86 Z[3]...87 padQ[3]....88 padQ[2]... 94 padQ[1]... 95 padQ[0]... 97 DB[0].. 219 DB[1] . 220 DB[2] . 221 DB[3].. 222 DB[4] ..223 DB[5].. 225 DB[6] ..226 DB[7]...227 E ..228 RS 229 R_W .230
The project contains 8 verilog files with the hierarchy shown below: CalcNew.v LCD.v newALU.v PAD.v Accumulator.v Pad_encoder.v Z_shifter.v OP_interupt.v