International Journal of Artificial Intelligence and Mechatronics Volume 1, Issue 5, ISSN 2320 5121

Design of Ultralow-Power Adiabatic Circuits and Area Characteristics

M. Vasanthakumar
PG Scholar (VLSI Design), AVS Engineering College, Salem 636003 Email: vassece.win@gmail.com Abstract The main objective of this paper is to provide new low power solutions for Very Large Scale Integration (VLSI) designers. Especially, this work focuses on the reduction of the power dissipation, which is showing an everincreasing growth with the scaling down of the technologies. Then, to limit the power dissipation, alternative solutions at each level of abstraction are proposed. The dynamic power requirement of CMOS circuits is rapidly becoming a major concern in the design of personal information systems and large computers. In this paper work, a new CMOS logic family called ADIABATIC LOGIC, based on the adiabatic switching principle is presented. The Logic cells like 2N2P, 2N2N2P, PFAL has been designed and presented here. Power consumption is widely reduced up to 50%. The simulation tool used to design adiabatic cells is TANNER EDA V13.0. Keywords Adiabatic, Low Power Very Large Scale Integration, 2N2N-2P, PFAL, 2N2P.

comparison between various adiabatic logics has been done to provide the better results.

II. DESIGN OF QUASI ADIABATIC CIRCUITS

A. 2N2N-2P
The 2N2N-2P adiabatic block has a 2N2P latch which consists of two NMOS and two PMOS transistors, along with complementary functional blocks, in parallel with the two NMOS devices of the 2N2P latch. The presence of these NMOS transistors avoids the occurrence of floating nodes with remnant charge, which will pay way for charge sharing and leakage. This ultimately results in loss of high frequency performance of the circuit. The four main phases of operation of the 2N2N-2P logic gates are 1) input, 2) hold, 3) recovery and 4) reset. A typical 2N2N2P inverter is shown in Fig. 1, to briefly explain the operation of the circuit.

I. INTRODUCTION
The study of existing literature in the past two decades provides the evolution of different low power gates. Digital CMOS integrated circuits have been the driving force behind VLSI for high performance computing and other applications, related to science and technology. The demand for digital CMOS integrated circuits will continue to increase in the near future, due to its important salient features like low power, reliable performance and improvements in the processing technology. The paper briefly proposed that a conventional semicustom design-ow based on a positive feedback adiabatic logic (PFAL) cell library allows any VLSI designer to design and verify complex adiabatic systems (e.g., arithmetic units) in a short time and easy way, thus, enjoying the energy reduction benets of adiabatic logic. The concepts in paper presents the design, evaluation and performance comparison of cell based, low power adiabatic adder circuits operated by two-phase sinusoidal power clock signals, as against the literatures providing the operation of various adiabatic circuits, focusing on inverter circuits and logic gates, powered by ramp, three phase and four phase clock signals. The cells are designed for the quasi-adiabatic families, namely, 2N2P, 2N2N2P, PFAL, ADSL and IPGL for configuring complex adder circuits. In this paper, we incorporate 2N2N-2P 2N2P and PFAL energy recovery logics to the multiplier circuit and obtain a significant power reduction. The adiabatic efficiency of the circuits is proved. Comparison with the CMOS counterparts is made to prove the validity of the results. The main objective of this paper is to provide the tradeoff between power, area and performance. And also the

Fig.1. Inverter using 2N2N-2P logic A four- phase power-clock is employed to power the circuit. It is called as power-clock to identify the fact that these power-clocks power the circuit and act as the timing clocks for the pipelined adiabatic circuit. By pipelining, we mean the operating nature of the adiabatic circuits, wherein the output of the current stage when held, is used for evaluation by the next stage in the circuit, and signal goes on across the stages by the presence of power-clock signals, each lagging behind the previous by 90o which is shown in figure 2. To explain the buffer operation, consider an input is applied, when the power-clock is low. Note that the complementary input from the previous stage is applied. This makes MN3 to conduct pulling the node out to zero. At this time, MN4 does not conduct. During the evaluation phase the power-clock (PC) rises and when the PC voltage reaches above the threshold voltage of PMOS device MP2

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International Journal of Artificial Intelligence and Mechatronics Volume 1, Issue 5, ISSN 2320 5121 starts conducting. Node outbar gets charged as MP2 conducts and it follows the power-clock. During the hold phase, the outputs are maintained the same. In this phase of operation, the next stage of adiabatic circuit, operates in its evaluate phase. During the recovery phase, power-clock starts falling. Then, since the node outbar is at a higher potential than the power-clock voltage, the charge from outbar goes back to the power-clock and hence energy is recovered. main difference between the PFAL and the 2N2N-2P logics is that the complementary functional blocks in PFAL are implemented as a pull up network, in parallel with the two PMOS devices. This has its characteristic advantages and disadvantages, when compared to the 2N2N-2P logic. This is explained in the following paragraph. The evaluate phase of the power-clock, assume that the input X is already high and /X low. When the power-clock voltage level rises above the threshold voltage Vtn of the NMOS transistor, the transistor MX conducts and connects the rising node voltage Y to PC. This node Y with rising voltage turns on the device MN2 and pulls the node /Y to ground. This in turn is applied to the gate of the PMOS device MP1. This in effect realizes a parallel combination of the PMOS and NMOS devices, namely, MX and MP1. This results in reduced ON resistance through the transmission gate structure. This reduction of resistance is the main advantage of the PFAL. During the hold phase of the power-clock, the Y and /Y logic levels are used as the input for the succeeding gate of the adiabatic pipeline. During the recovery phase, the power-clock voltage reduces. Then, due to the potential difference existing between the power rail and Y node, the charge gets transferred back to the PC. However, since the input NMOS device at this time is OFF, energy recovery is made possible only through the PMOS device. This in effect poses increased resistance. When the PC voltage is lower than the Vth of the PMOS device, the charge recovery stops. This results in the floating node problem, due to the remnant charge. This remaining charge is retained in the output node and is dissipated in the next stage, when the states of the adiabatic stage change. Hence, this logic falls under quasi adiabatic family, that is complete recovery of energy is not possible due to the losses mentioned above. The floating output node problem also results in poorer high frequency performance.

Fig.2. Timing Diagram for 2N2N-2P logic

B. PFAL
The acronym PFAL stands for the Positive Feedback Adiabatic Logic. It is a dual rail adiabatic circuit capable of realizing partial energy recovery. The basic circuit of Fig 3 represents a buffer implemented using PFAL logic. Analogous to the 2N2N-2P logic, this logic also uses the four-phase power-clock, consisting of 4 phases, namely, (1) the rising phase of power-clock called evaluate, (2) the constant phase called hold, when the output is held for the next stage to evaluate this signal, (3) the falling phase of power-clock called reset or recovery, where the process of charge reclamation or charge retrieval takes place. This is followed by the Wait phase, which synchronizes the flow of data across the adiabatic pipeline.

C. 2N2P
The 2N2P adiabatic block consists of two NMOS and two PMOS transistors. The operation is same as a 2N2N2P adiabatic cell. The presence of these NMOS transistors avoids the occurrence of floating nodes with remnant charge, which will pay way for charge sharing and leakage. This ultimately results in loss of high frequency performance of the circuit. The four main phases of operation of the 2N2N-2P logic gates are 1) input, 2) hold, 3) recovery and 4) reset. A typical 2N2P inverter is shown in Figure 4, to briefly explain the operation of the circuit. A four- phase power-clock is employed to power the circuit. It is called as power-clock to identify the fact that these power-clocks power the circuit and act as the timing clocks for the pipelined adiabatic circuit. By pipelining, we mean the operating nature of the adiabatic circuits, wherein the output of the current stage when held, is used for evaluation by the next stage in the circuit, and signal goes on across the stages by the presence of power-clock signals, each lagging behind the previous by 90o.

Fig.3. Structure of PFAL buffer The heart of the PFAL circuits is the adiabatic amplifier latch made by two PMOS and NMOS transistors. The

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International Journal of Artificial Intelligence and Mechatronics Volume 1, Issue 5, ISSN 2320 5121

Fig.4. Inverter using 2N2P logic

III. ADIABATIC CELL DESIGN AND DESIGN FLOW

The realization of multiplier is done in a semi-automatic custom flow as depicted in Fig.5 the individual modules are constructed using the S-Edit and the designs are exported to the T-Spice circuit Simulator. The operational feasibility of the gate is studied for various frequency ranges and capacitive loads. The functional block diagram of the multiplier circuit is shown in Fig.5.

Fig.6. Schematic of 8x8 Adiabatic Multiplier

V. PERFORMANCE EVALUATION AND COMPARISON

The results of the simulation are presented in this section. Each of the multiplier was analyzed for energy consumption and the number of transistor devices employed in the design, which is an indication of the actual silicon area requirement for the circuit. The inputs A, B, C and D were supplied as per the four bit binary counting sequence for uniformity. The frequency of the power clock was 50 MHz The energy dissipation measurement was done from the simulation outputs, by integrating the power over the specific period of simulation. The average power dissipation of the circuit was also observed. The waveform shown in figure 7 gives the performance evaluation of Conventional CMOS circuit.

Fig.5. Schematic of 4x4 Multiplier

IV. ADIABATIC ADDER DESIGNS

The Baugh- wooley multiplier is selected because of its high efficiency. This technique has been developed in order to design regular multipliers, suited for 2s complement numbers. It is capable of performing doubleprecision multiply-accumulate operations without the speed penalty. The Schematic diagram of the multiplier is shown in below figure 6.

Fig.7. Output Waveform of CMOS multiplier The waveform of the adiabatic multiplier is shown below in figure 8.

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International Journal of Artificial Intelligence and Mechatronics Volume 1, Issue 5, ISSN 2320 5121

Multipliers CMOS 2N2P 2N2N2p PFAL

No. Of Transistors Used 2080 1568 2020 1968

Fig.8. Output waveform of 2N2P adiabatic Multiplier. The waveform shown in figure 8 is the output waveform of the PFAL adiabatic multiplier.

Table II depict the power comparison made for the proposed multiplier constructed using 2N2N-2P, 2N2P and PFAL adiabatic structures. The results show the reduction of power from 30% to 50%, while using adiabatic circuit. Table II: Power Comparison of Various Multipliers Multipliers Min Max Power(mW) Power(mW) CMOS 167 0.0052 2N2P 0 0.0000088 2N2N2P 0 0.0000323 PFAL 0 0.0000136

VI. CONCLUSION
The paper primarily was focused on the design of low power CMOS cell structures, which is the main contribution of this work. The design of low power CMOS cell structures uses fully complementary CMOS logic style and an adiabatic 2N2P, 2N2N2P, PFAL logic style. The basic principle behind implementing various design units in the two logic styles is to compare them with reference to the average power dissipated by all of them. A family of full-custom conventional CMOS Logic and Adiabatic Logic units was designed in Tanner Tool V.13 using 120 micrometer technology and the analysis of power, are, and simulation was done. It was found that the adiabatic 2N2P, 2N2N2P, PFAL logic style is advantageous in applications where power reduction is of prime importance as in high performance battery-portable digital systems running on batteries such as note-book computers, cellular phones and personal digital assistants. With the adiabatic switching approach, the circuit energies are conserved rather than dissipated as heat. Depending on the application and the system requirements, this approach can be used to reduce the power dissipation of the digital systems. With the help of adiabatic logic, the energy savings of up to 30 % to 50 % can be reached.

Fig.8. Output waveform of PFAL multiplier. Table I shows the number of transistors in various multiplier architectures. It is found that our proposed architecture uses the lowest number of transistors when it comes to adiabatic implementation. This considerable reduction of transistor count is obtained as results of processing three generate and propagate signals together. Reduction in Transistor count provides the very less area when compare with the conventional CMOS.

REFERENCES
[1] Antonio Blotti and Roberto Saletti, Ultralow-Power Adiabatic Circuit Semi-Custom Design, IEEE Transactions on Very Large Scale Integration (VLSI) systems, Vol.12, No.11, November 2004. V. S. Kanchana Bhaaskaran, D. S. Emmanuel and S. Salivahanan. Semi custom Design of Adiabatic Adder Circuits, Proceedings of the 19th International Conference on VLSI Design (VLSID06), pp. 745-748. H. Neil. Weste and Kamran Eshraghian, Principles of CMOS VLSI design-A Systems Perspective, Pearson Edition Pvt Ltd. 3rd edition, pp. 345-356, 2005. V.S.Kanchana Bhaaskaran, Adiabatic Logic Circuit design with Integrated Power Clock Generator, Proceedings, Third International Conference on Signals,Systems & devices, March 21-24, 2005, Vol IV

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Table I Transistor Count Comparison of Various Multiplier

The table I shown below is the comparison of conventional CMOS multiplier with the adiabatic multiplier. The result shows the reduced transistor count in adiabatic circuits.
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International Journal of Artificial Intelligence and Mechatronics Volume 1, Issue 5, ISSN 2320 5121
[5] Dragan Maksimovic et al. Clocked CMOS adiabatic Logic with Integrated Single Phase Power Clock Supply, IEEE Transactions on VLSI Systems, Vol 8, No 4, Aug 2000, pp 460463. Leverage, F.Kovacs, G.Hosszu,An improved pass gate adiabatic logic, Proceedings, 14th Annual International ASIC/SOC Conference, pp 208-211, 2001 W. C. ATHAS, J. G. KOLLER, L. SVENSSON, An EnergyEfficient CMOS Line Driver using Adiabatic Switching, Fourth Great Lakes symposium on VLSI, California, March 2005. L.Verga, F.Kovacs, G.Hosszu,An improved pass gate adiabatic logic, Proceedings, 14th Annual International ASIC/SOC Conference, pp 208-211, 2001.

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AUTHORS PROFILE
M. Vasanthakumar
Completed B.E Degree in Electronics and Communication engineering in 2009 from paavai engineering College affiliated by Anna University, Chennai and currently pursuing M.E Degree in VLSI DESIGN from AVS Engineering College, affiliated by Anna University, Chennai. He worked as an EMF & RF Engineer in Sprint Communication Services at Chennai during the year of 2009-2010.The research interest includes Wireless networks and Testing of VLSI Circuits System.

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