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Pipelining & RISCs

2 methods used to achieve concurrency : Pipelining increases concurrency by dividing a computation into a number of steps. parallelism- the use of multiple resources to increase concurrency. Pipelining used key implementation technique to build fast processors. It allows the execution of multiple instructions to overlap in time : Entire processing flow is broken up into multiple stages, and a new data/instruction is processed by a stage potentially as soon as it is done with the current data/instruction, which then goes onto the next stage for further processing For the Non-Pipelining is by contrast Performance improved but not doubled: Fetch usually shorter than execution Any jump or branch means that pre-fetched instructions are not the required instructions To improve performance, the pipeline should have more stages. An ideal pipeline divides a task into k independent sequential subtasks : each subtask requires 1 time unit to complete. the task itself then requires k time units to complete. Instruction Pipelining Typical instruction execution sequences: fetch, decode, read, execute, write, etc In a non-pipelined CPU, instructions are performed one at a time.ie. before an instruction is begun, the preceding instruction is completed.

In a pipelined CPU, the execution of instructions is performed in stages. Separate hardware is provided to handle each of these stages. Instructions proceed through the CPU stages:

To implement instruction pipelining, desirable features of (instruction set) IS: all instructions same length registers specified in same place in instruction memory operands only in loads or stores, i.e. RISC But, it is not always the case in reality.

Two Stage Instruction Pipeline

6 stage pipelining
Fetch instruction Decode instruction Calculate operands (i.e. EAs) Fetch operands

Execute instructions Write result Overlap these operations EXAMPLE -6 Stage Pipelining

Pipelining of Unequal Stages

Important for pipelining where stages are unequal: Always take the largest of the stage delay to be the cycle time No stage overlaps and latency must be constant Ensure that instruction overlap is the same as the cycle time else get timing diagram is wrong

Timing Diagram
Wrong Timing Diagram: Overlaps

Wrong Timing Diagram: Latencies not constant

Correct timing diagram

Pipeline Performance n:number of instructions k: stages in pipeline : cycletime (time in seconds needed to advance a set of instructions one stage through the pipeline) Tk: total time for pipelining T0 : total time without pipelining

Total time for equal stages Total time with no pipelining, T0 = nk Total time with pipelining, Tk = (k + (n-1)) Total time for unequal stages For n instructions, with k unequal stages. Each stage have unequal delays. Total time with no pipelining Where is the delay time for stage i Total time with pipelining, where Fill time is ch stage

Speedup Speedup of a k-stage pipeline for n instructions : S = T0 / Tk = nk / ((k+(n-1))

k (for large n) Note: the equations for T0 and Tk is not equal, it means that each stage from 1 to k would have the time(s), like , . Limits to Pipelining Factors that limits performance enhancement: Unequal duration/delay of stages Conditional branch instruction or interrupts Branch in a Pipeline

Hazards as limitation to pipelining. 3 types of hazards: Resource hazards : HW cannot support this combination of instructions (single person to fold and put clothes away, washer-drier) Data hazards: Instruction depends on result of prior instruction still in the pipeline Data dependencies example A=B+C D=E+A C=GxH Control hazards: Caused by delay between the fetching of instructions and decisions about changes in control flow (branches and jumps). Reduced Instruction Set Computers Major advances in computer : The family concept Separates architecture from implementation Microprogrammed control unit Cache memory Solid State RAM Microprocessors Pipelining Introduces parallelism into fetch execute cycle

 Multiple processors CISC and RISC The next step: Reduced Instruction Set Computer in processor architecture Key features of CISC: Large number of predefined instructions making high level programming languages easy to design and implement. Supports microprogramming to simplify computer architecture Key features of RISC Limited and simple instruction set Large number of general purpose registers or use of compiler technology to optimize register use. Emphasis on optimizing the instruction pipeline CISC characteristics Varying number of instructions per cycle Small number of general purpose registers More addressing modes More instruction formats : fewer instructions can be used to implement a given task Use microcode Variable length instruction Simplified compiler: microprogram instructions could be written to match constructs of high level languages

RISC Characteristics One instruction per cycle Register to register operations Few, simple addressing modes Few, simple instruction formats Hardwired design (no microcode) Fixed instruction format More compile time/effort

RISC vs. CISC