STP8NM50 STP8NM50FP

N-channel 550V @ Tjmax - 0.7 - 8A - TO-220 - TO-220FP MDmesh Power MOSFET

General features
Type STP8NM50 STP8NM50FP VDSS (@Tjmax) 550V 550V RDS(on) <0.8 <0.8 ID 8A 8A (1)
3 1 2

1. Limited only by maximum temperature allowed

3 1 2

100% avalanche tested High dv/dt and avalanche capabilities Low gate input resistance Low input capacitance and gate charge

TO-220

TO-220FP

Description
The MDmesh is a new revolutionary Power MOSFET technology that associates the multiple drain process with the companys PowerMESH horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the companys proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competitions products.

Internal schematic diagram

Applications

Switching application

Order codes
Part number STP8NM50 STP8NM50FP Marking P8NM50 P8NM50FP Package TO-220 TO-220FP Packaging Tube Tube

October 2006

Rev 7

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Contents

STP8NM50 - STP8NM50FP

Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 4 5

Test circuit

................................................ 9

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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STP8NM50 - STP8NM50FP

Electrical ratings

Electrical ratings
Table 1.
Symbol VGS ID ID IDM
(2)

Absolute maximum ratings

Value Parameter TO-220 Gate-source voltage Drain current (continuous) at TC = 25C Drain current (continuous) at TC = 100C Drain current (pulsed) Total dissipation at TC = 25C Derating factor 8 5 32 100 0.8 15 --65 to 150 2500 30 8
(1)

Unit TO-220FP V A A A W W/C V/ns V C

5 (1) 32
(1)

PTOT dv/dt(3) VISO Tj Tstg

25

Peak diode recovery voltage slope Insulation withstand voltage (RMS) from all three leads to external heat sink (t=1s;TC=25C) Operating junction temperature Storage temperature

1. Limited only by maximum temperature allowed 2. Pulse width limited by safe operating area 3. ISD 8 A, di/dt 200 A/s, VDD V(BR)DSS, Tj TJMAX.

Table 2.
Symbol Rthj-case Rthj-amb Tl

Thermal data
Parameter Thermal resistance junction-case max Thermal resistance junction-amb max Maximum lead temperature for soldering purpose TO-220 1.25 62.5 300 TO-220FP 5 Unit C/W C/W C

Table 3.
Symbol IAR EAS

Avalanche characteristics
Parameter Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) Single pulse avalanche energy (starting Tj=25C, ID=IAR, VDD= 50V) Max value 2.5 200 Unit A mJ

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Electrical characteristics

STP8NM50 - STP8NM50FP

Electrical characteristics
(TCASE=25C unless otherwise specified) Table 4.
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)

On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250A, VGS= 0 VDS = Max rating, VDS = Max rating @125C VGS = 30 V VDS= VGS, ID = 250 A VGS= 10 V, ID= 2.5A 3 4 0.7 Min. 500 1 10
100

Typ.

Max.

Unit V A A nA V

5 0.8

Table 5.
Symbol gfs (1) Ciss Coss Crss Coss eq.(2) Qg Qgs Qgd RG

Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Equivalent ouput capacitance Total gate charge Gate-source charge Gate-drain charge Gate input resistance Test conditions VDS > ID(on) x RDS(on)max, ID= 2.5A Min. Typ. 2.4 415 88 12 50 13 4 6 3 Max. Unit S pF pF pF pF nC nC nC

VDS =25V, f=1 MHz, VGS=0

VGS=0, VDS =0V to 400V VDD=400V, ID = 5A VGS =10V (see Figure 16) f=1MHz Gate DC Bias = 0 Test signal level = 20mV Open drain

1. Pulsed: pulse duration=300s, duty cycle 1.5% 2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS

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STP8NM50 - STP8NM50FP

Electrical characteristics

Table 6.
Symbol td(on) tr tr(Voff) tf tc

Switching times
Parameter Turn-on delay time Rise time Off-voltage rise time Fall time Cross-over time Test conditions VDD=250 V, ID=2.5A, RG=4.7, VGS=10V (see Figure 15) VDD=400 V, ID=5A, RG=4.7, VGS=10V (see Figure 15) Min Typ 16 8 14 6 13 Max Unit ns ns ns ns ns

Table 7.
Symbol ISD ISDM VSD trr Qrr IRRM trr Qrr IRRM

Source drain diode

Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current Reverse recovery time Reverse recovery charge Reverse recovery current ISD=10A, VGS=0 ISD=5A, di/dt = 100A/s, VDD=100 V, Tj=25C (see Figure 20) ISD=5A, di/dt = 100A/s, VDD=100 V, Tj=150C (see Figure 20) 185 1.1 11.5 270 1.6 12 Test conditions Min Typ Max 8 32 1.5 Unit A A V ns C A ns C A

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Electrical characteristics

STP8NM50 - STP8NM50FP

2.1
Figure 1.

Electrical characteristics (curves)

Safe operating area for TO-220 Figure 2. Thermal impedance for TO-220

Figure 3.

Safe operating area for TO-220FP

Figure 4.

Safe operating area for TO-220FP

Figure 5.

Output characteristics

Figure 6.

Transfer characteristics

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STP8NM50 - STP8NM50FP Figure 7. Transconductance Figure 8.

Electrical characteristics Static drain-source on resistance

Figure 9.

Gate charge vs gate-source voltage Figure 10. Capacitance variations

Figure 11. Normalized gate threshold voltage vs temperature

Figure 12. Normalized on resistance vs temperature

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Electrical characteristics Figure 13. Source-drain diode forward characteristics

STP8NM50 - STP8NM50FP Figure 14. Normalized BVDSS vs temperature

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STP8NM50 - STP8NM50FP

Test circuit

Test circuit
Figure 16. Gate charge test circuit

Figure 15. Switching times test circuit for resistive load

Figure 17. Test circuit for inductive load Figure 18. Unclamped Inductive load test switching and diode recovery times circuit

Figure 19. Unclamped inductive waveform

Figure 20. Switching time waveform

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Package mechanical data

STP8NM50 - STP8NM50FP

Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com

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STP8NM50 - STP8NM50FP

Package mechanical data

TO-220 MECHANICAL DATA

DIM. A b b1 c D E e e1 F H1 J1 L L1 L20 L30 mm. MIN. 4.40 0.61 1.15 0.49 15.25 10 2.40 4.95 1.23 6.20 2.40 13 3.50 16.40 28.90 3.75 2.65 3.85 2.95 0.147 0.104 TYP MAX. 4.60 0.88 1.70 0.70 15.75 10.40 2.70 5.15 1.32 6.60 2.72 14 3.93 MIN. 0.173 0.024 0.045 0.019 0.60 0.393 0.094 0.194 0.048 0.244 0.094 0.511 0.137 0.645 1.137 0.151 0.116 inch TYP. MAX. 0.181 0.034 0.066 0.027 0.620 0.409 0.106 0.202 0.052 0.256 0.107 0.551 0.154

P
Q

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Package mechanical data

STP8NM50 - STP8NM50FP

TO-220FP MECHANICAL DATA

mm. MIN. 4.4 2.5 2.5 0.45 0.75 1.15 1.15 4.95 2.4 10 16 28.6 9.8 2.9 15.9 9 3 30.6 10.6 3.6 16.4 9.3 3.2 1.126 .0385 0.114 0.626 0.354 0.118 TYP MAX. 4.6 2.7 2.75 0.7 1 1.7 1.7 5.2 2.7 10.4 MIN. 0.173 0.098 0.098 0.017 0.030 0.045 0.045 0.195 0.094 0.393 0.630 1.204 0.417 0.141 0.645 0.366 0.126 inch TYP. MAX. 0.181 0.106 0.108 0.027 0.039 0.067 0.067 0.204 0.106 0.409

DIM. A B D E F F1 F2 G G1 H L2 L3 L4 L5 L6 L7

L3 L6 L7
F1 F

G1 H
F2
L2 L5

E
1 2 3
L4

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STP8NM50 - STP8NM50FP

Revision history

Revision history
Table 8.
Date 09-Sep-2004 11-Aug-2006 22-Sep-2006 18-Oct-2006

Revision history
Revision 4 5 6 7 Title changed New template Some value change in Table 4: On/off states Updated Note 3 on page 3 Changes

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STP8NM50 - STP8NM50FP

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