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8086 Interrupt System By. M. Chinyuku

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The meaning of interrupts is to break the sequence of operation. While the CPU is executing a program, on interrupt breaks the normal sequence of execution ofinstructions, diverts its execution to some other program called Interrupt Service Routine (ISR). After executing ISR , the control is transferred back again to the main program. Interrupts cause control to be passed to an interrupt handler. Interrupt handlers are routines that process the interrupt. Each type of interrupt is assigned an integer number. At the beginning of physical memory, a table of interrupt vectors resides that contain the segmented addresses of the interrupt handlers. The number of interrupt is essentially an index into this table. Edge or Level sensitive Interrupts Edge level interrupts are recognized on the falling or Rising edge of the input signal. They are generally used for high priority interrupts and are latched internally inside the processor. If this latching was not done, the processor could easily miss the falling edge (due to its short duration) and thus not respond to the interrupt request. Level sensitive interrupts overcome the problem of
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latching, in that the requesting device holds the interrupt line at a specified logic state (normally logic zero) till the processor acknowledges the interrupt. This type of interrupt can be shared by other devices in a wired 'OR' configuration, which is commonly used to support daisy chaining and other techniques. Classification of Interrupts Interrupts can be classified into two types 1. Non Maskable Interrupts (NMI) Programmer cannot disable or remove An NMI request causes the program to branch to a fixed address in memory An NMI is used in association with a subroutine having the highest priority The processor can inhibit certain types of interrupts by use of a special interrupt mask bit. This mask bit is part of the flags/condition code register, or a special interrupt register. In the 8086 microprocessor if this bit is clear, and an interrupt request occurs on the Interrupt Request input, it is ignored. 2. Maskable Interrupts (MI)

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Can be disabled or masked out It can be ignored or delayed by the CPU if it is performing a critical task.

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Interrupt instructions Interrupt enable flag (IF) - causes external interrupts to be enabled. INT n - initiates a vectored call of a subroutine. INTO- instruction should be used after each arithmethic instruction where there is a possibility of an overflow. HLT - waits for an interrupt to occur. WAIT- waits for TEST input to go high. 12

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Difference between INT and CALL instructions S.No CALL INT 1. Can Jump to any Goes to fixed memory location with in 1MB location in the interrupt address range vector table to get address of ISR 2. Used by the externally activated programmer in the hardware interrupt can sequence of come at any time instructions in the program S.No CALL INT 3. Cannot be masked INTR can be masked (disabled) 4. Automatically saves In addition to CS:IP, FlagsCS: IP of next can be saved instruction 5. RET is the last IRET to pops of F, CS:IP instruction

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The Operation of Real Mode Interrupt The 8086 reserves the lower 1024 bytes of memory for an interrupt vector table. There is one 4-byte vector for each of the 256 possible interrupt/exception numbers. Each entry contains the offset and the segment address of the interrupt vector each 2 bytes long. Table starts at the memory address 00000F 03FFH (reserved for interrupt vectors). Each interrupt vector format segment:offset. E.g CS:50 An ISR is identified by a number from 0 to 255 this called its type An interrupt pointer/vector is a doubleword the low word contains the IP value the high word contains the CS value FFFF0h - FFFFFh - after RESET the processor always starts program execution at the FFFF0h address. First 32 vectors are spared for various microprocessor families. The rest 224 vectors are user definable. The lower the vector number, the higher the priority. Dedicated Interrupts Type 0 to Type 4 interrupts are dedicated to specific interrupts
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Type 5 to Type 31 interrupts are reserved by Intel for more complex microprocessors Type 32 to Type 255 interrupts can be user specified for dealing with hardware or software interrupts Interrupts Western Washington University When an interrupt or exception occurs, the processor: 1. External interface sends an interrupt signal, to the Interrupt Request (INTR) pin, or an internal interrupt occurs. 2. The CPU finishes the present instruction (for a hardware interrupt) and sends Interrupt Acknowledge (INTA) to hardware interface. 3. The interrupt type N is sent to the Central Processor Unit (CPU) via the Data bus from the hardware interface.

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4. The contents of the flag registers are pushed onto the stack. 5. Both the interrupt (IF) and (TF) flags are cleared. This disables the INTR pin and the trap or single-step feature. 6. Pushes the flags register, CS, and IP (in that order), 7. The interrupt vector contents are fetched, from (4 xN) and then placed into the IP and from (4 x N +2) into the CS so that the next instruction executes at the interrupt service procedure addressed by the interrupt vector, and 8. Transfers control to that location. 9. While returning from the interrupt-service routine by the Interrupt Return (IRET) instruction, the IP, CS and Flag registers are popped from the Stack and return to their state prior to the interrupt.

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Example At what address should vector 50, CS:50, and IP:50 be stored in memory? Answer Each vector requires four bytes of memory Address = 50 x 4 = 200 Converting to binary 200 = 1100 1000b Address = C8h IP:50 is stored in 00C8h CS:50 is stored in 00CAh

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For external interrupts (IRQ or NMI) the interruptnumber is read from the data bus during an interrupt acknowledge bus cycle. For internal interrupts (e.g. INT instruction) the interrupt number is determined from the instruction. The INT instruction allows a program to generate any of the 256 interrupts. This software interrupt is typically used to access operating system services. Exercise MS-DOS programs use the INT 21H instruction to request operating system services. Where would the address of the entry point to these DOS : services be found?

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8086 Interrupt Response ISR procedure Mainline Program PUSH Flags PUSH registers CLEAR IF , TF PUSH CS PUSH IP FETCH ISR ADDRESS POP registers POP IP IRET POP CS POP FLAGS

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The CLI and STI instructions clear/set the interrupt-enable bit in the flags register to disable/ enable external interrupts. The IRET instruction pops the IP, CS and flags register values from the stack and thus returns control to the instruction following the one where interrupt or exception occurred. Exercise : What would happen if you used RET instead of IRET to return from an interrupt?

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Interrupt Vector Table Type 4 POINTER 010H (OVERFLOW) Type 3 POINTER 00CH (BREAK POINT) Type 2 POINTER 008H (NON-MASKABLE) Type 1 POINTER 004H (SINGLE STEP) Type 0 POINTER CS base address 000H (DIVIDE ERROR) IP offset 16 bits

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03FFH Type 255 (Available) Available Type 32 (Available) (224) 080H Type 31 (Reserved) Reserved 07FH Interrupts Type 5 Reserved 0014H Interrupt Vector Table INT Number INT 00 INT 01 INT 02 Physical Address 00000 00004 00008 03FCH Interrupts

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Multiple Interrupts If more than one device is connected to the interrupt line, the processor needs to know to which device service routine it should branch to. The identification of the device requesting service can be done in either hardware or software, or a combination of both. The three main methods are: Software Polling, Hardware Polling, (Daisy Chain), Hardware Identification (Vectored Interrupts).

INT FF

003FC

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Software Polling Determination of the Requesting Device A software routine is used to identify the device requesting service. A simple polling technique is used, each device is checked to see if it was the one needing service. Having identified the device, the processor then branches to the appropriate interrupthandling-routine address for the given device.The order in which the devices appear in the polling sequence determines their priority.

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Summary of Software Polled I/O Polling is the most common and simplest method of I/O control. It requires no special hardware and all I/O transfers are controlled by the CPU programme. Polling is a synchronous mechanism, by which devices are serviced in sequential order. The polling technique, however, has limitations. 1) It is wasteful of the processors time, as it needlessly checks the status of all devices all the time, 2) It is inherently slow, as it checks the status of all I/O devices before it comes back to check any given one again, 3) When fast devices are connected to a system, polling may simply not be fast enough to satisfy the minimum service requirements, 4) Priority of the device is determined by the order in the polling loop, but it is possible to change it via software.

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Software/Hardware Driven Identification (Daisy Chain) This is significantly faster than a pure software approach. A daisy chain is used to identify the device requesting service. Daisy chaining is used for level sensitive interrupts, which act like a wired 'OR' gate. Any requesting device can take the interrupt line low, and keep it asserted low until it is serviced. Because more than one device can assert the shared interrupt line simultaneously, some method must be employed to ensure device priority. This is done using the interrupt acknowledge signal generated by the processor in response to an interrupt request.

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Each device is connected to the same interrupt request line, but the interrupt acknowledge line is passed through each device, from the highest priority device first, to the lowest priority device last. After preserving the required registers, the microprocessor generates an interrupt acknowledge signal. This is gated through each device. If device 1 generated the interrupt, it will place its identification signal on the data bus, which is read by the processor, and used to generate the address of the interruptservice routine. If device 1 did not request the servicing, it will pass the interrupt acknowledge signal on to the next device in the chain. Device 2 follows the same procedure, and so on.

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Hardware Identification (Vectored Interrupts) This is the fastest system. The onus is placed on the requesting device to request the interrupt, and identify itself. The identity could be a branching address for the desired interrupthandling routine. If the device just supplies an identification number, this can be used in conjunction with a lookup table to determine the address of the required service routine. Response time is best when the device requesting service also supplies a branching address. Priority Interrupt Controller Chips (PIC's) are hardware chips designed to make the task of a device presenting its own address to the CPU simple. The PIC also assesses the priority of the devices connected to it. Modern PIC's can also be programmed to prevent the generation of interrupts which are lower than a desired level. The decoded location is connected to the output of a priority encoder. The input of the priority encoder is connected to each device. When a device requests service, the priority encoder presents a special code combination (unique for each device) to the decoded memory location. The port thus holds the value or address associated with the highest device

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requesting service.

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The priority encoder arranges all devices in a list, devices given a lower priority are serviced when no other higher priority devices need servicing. This simplifies the software required to determine the device, resulting in anincrease in speed. The disadvantages are: 1) The extra chip required, 2) Resultant increases in cost, 3) More board space and power consumption, 4) Fixed priority in hardware. Functions associated with INT00 to INT04 (Exceptions) INT 00 (divide error) INT00 is invoked by the microprocessor whenever there is an attempt to divide a number by zero ISR is responsible for displaying the message Divide Error on the screen Ex1: Mov AL,82H ;AL= 82 SUB CL,CL ;CL=00 DIV CL ;82/0 = undefined result EX2: Mov AX,0 FFFFH; AX = FFFFH Mov BL,2 ; BL=02

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DIV BL ; 65,535/2 = 32767 larger than 255 maximum capacity of AL INT 01 For single stepping the trap flag must be 1 After execution of each instruction, 8086 automatically jumps to 00004H to fetch 4 bytes for CS: IP of the ISR The job of ISR is to dump the registers on to the screen Resetting TF (TF = 0) First method: PUSH F POP AX AND AX, 1111 1110 1111 1111 B PUSH AX POP F Second method: PUSH F MOV BP,SP AND 0(BP), OFE FFH POP F Setting TF (TF = 1) Use OR instruction in place of AND instruction.

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PUSH F POP AX OR AX, 0000 0001 0000 0000 B PUSH AX POP F INT 02 (Non maskable Interrupt) 8086 5v NMI Whenever NMI pin of the 8086 is activated by a high signal (5v), the CPU Jumps to physical memory location 00008 to fetch CS:IP of the ISR assocaiated with NMI INT 03 (break point) A break point is used to examine the CPU and memory after the execution of a group of Instructions. It is one byte instruction whereas other instructions of the form INT nn are 2 byte instructions. INT 04 ( Signed number overflow) There is an instruction associated with this INT 0 (interrupt on overflow). If INT 0 is placed after a signed number arithmetic as IMUL or ADD the CPU will activate INT

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04 if 0F = 1. In case where 0F = 0 , the INT 0 is not executed but is bypassed and acts as a NOP. Example Mov AL , 64 Mov BL , 64 ADD AL , BL INT 0 ; 0F = 1 +64 +128 INT 0 causes the cpu to perform INT 04 and jumps to physical location 00010H of the vector table to get the CS : IP of the ISR HARDWARE INTERRUPTS NMI : Non maskable interrupts INTR : Interrupt request Edge triggered Input Input INTA INTR input 8086 Hardware Interrupts NMI INTR Level triggered Response to 0100 0000 +64 0100 0000

1000 0000

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NMI: TYPE 2 Interrupt INTR: Between 20H and FFH Interrupt priority structure Interrupt Priority Divide Error, INT(n),INTO Highest NMI INTR Single Step Lowest University Questions 1) Explain the sequence of operation follow after the execution of INTR interrupt. Write timing diagram. 2) What do you mean by interrupt priorities? List out interrupt priorities in 8086. 3) On receiving a hardware interrupt, the 8086 processor pushes the flag to the stack and clears the TF and IF before doing any further operation. Explain why this is required. (6marks) 4) Even though interrupt service routine is similar to any procedure routine from the last instruction of interrupt routine is IRET which is coded differently from the RET instruction of the subroutine return. Explain the reasons for this separate IRET instruction (4 marks) 5) What is an Interrupt Vector? Explain in detail the events
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that occur when a real mode interrupt becomes active.(6marks) 6) Describe the software and hardware interrupts of 8086. (8marks) Important Questions 1. What are the sources of Interrupts in 8086? 2. What is Interrupt vector table? 3. Briefly describe the conditions which cause the 8086 to perform each of the following types of Interrupts Type 0 , Type 1, Type 2, Type 3, Type 4 4. What is meant by Interrupt priorities? State the Interrupt priorities of 8086.

What Is The Difference Between I/O Mapped I/O & Memory Mapped I/O ?
Best Answer - Chosen by Voters
Is this a homework question? Memory mapped I/O is mapped into the same address space as program memory and/or user memory, and is accessed in the same way. I/O mapped I/O (also known as port mapped I/O) uses a separate, dedicated address space and is accessed via a dedicated set of microprocessor instructions. If you're using a microprocessor or microcontroller that doesn't support port mapped I/O, then you have to
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use memory mapped I/O. Microprocessors that support port mapped I/O include Intel x86 and compatible processors, and also the Zilog Z80 and Intel 8080. Microprocessors that DON'T support port mapped I/O (and hence require the use of memory mapped I/O) include the Motorola 6800 and the MOS Technology 6502. The advantage of port mapped I/O is that it makes for neater code and requires fewer external components to implement I/O. However, it adds to the complexity and pin count of the microprocessor itself.

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