DLD GTU Question Bank: Chapter-1 Binary System

PREPARED BY: Prof Nirav R. Patel, EEE Dept.
, GMFE
DLD
GTU Question Bank

Chapter-1 Binary System

Convert the following numbers to decimal
(i) (10001.101)
2
(ii) (101011.11101)
2
(iii) (0.365)
8
(iv) A3E5 (v) CDA4 (vi) (11101.001)
2
(vii)
B2D4
Perform the operation of subtractions with the following binary numbers using 2 complement
(i) 10010 - 10011 (ii) 100 -110000 (iii) 11010 -10000
Define : Integrated Circuit and briefly explain SSI, MSI, LSI and VLSI
Define: Digital System. Convert following Hexadecimal Number to Decimal : B28, FFF, F28
Convert following Octal Number to Hexadecimal and Binary: 414, 574, 725.25
Convert the following Numbers as directed:
(1) (52)10 = ( ) 2
(2) (101001011)2 = ( ) 10
(3) (11101110) 2 = ( ) 8
(4) (68)10 = ( )16
Convert decimal 225.225 to binary ,octal and hexadecimal
Convert decimal 8620 into BCD , excess-3 code and Gray code.
Represent the decimal number 8620 in BCD , Excess-3 , and Gray code
Convert the Decimal Number 250.5 to base 3, base 4, base 7 & base 16.

Chapter- 2 Boolean algebra and Logic Gates

Demonstrate by means of truth tables the validity of the following theorems of Boolean algebra
(i) De Morgans theorems for three variables (ii) The Distributive law of + over -
Draw the logic symbol and construct the truth table for each of the following gates. [1] Two input
NAND gate [2] Three input OR gate [3] Three input EX-NOR gate [4] NOT gate
Give classification of Logic Families and compare CMOS and TTL families
Explain SOP and POS expression using suitable examples
Draw symbol and construct the truth table for three inputs Ex-OR gate.
What is the principle of Duality Theorem?
Explain briefly: standard SOP and POS forms.
What are Minterms and Maxterms?
Define: Noise margin , Propagation delay
Explain briefly : SOP & POS , minterm & maxterm , canonical form , propagation delay, fan out
Given Boolean function
F= x y + x y + y z
1. Implement it with only OR & NOT gates
2. Implement it with only AND & NOT gates
PREPARED BY: Prof Nirav R. Patel, EEE Dept., GMFE
Express following Function in Product of Maxterms F(x,y,z)= ( xy + z ) ( y + xz )

Chapter- 3 Simplification of Boolean Functions
Obtain the simplified expressions in sum of products for the following Boolean functions: (i)
F(A,B,C,D,E) =(0,1,4,5,16,17,21,25,29) (ii) ABCE + ABCD +BDE + BC D
Reduce the expression: (1) A+B(AC+(B+C)D) (2) (A+(BC))(AB+ABC)
Simplify the Boolean function: (1) F = ABC+BCD+ABCD+ABC (2) F
=ABD+ACD+ABC d=ABCD+ACD+ABD Where d indicates Dont care conditions.
Simplify the Boolean function: (1)F(w,x,y,z) = (0,1,2,4,5,6,8,9,12,13,14) (2)F(w,x,y) =
(0,1,3,4,5,7)
Simplify the following Boolean function by using Tabulation method.
F = (0,1,2,8,10,11,14,15 )
Simplify the following Boolean function using K-map
F( w,x,y,z) = ( 1 , 3 , 7 , 11 , 15 ), with dont care conditions d(w,x,y,z) = ( 0, 2 ,5 )
Simplify the following Boolean function using tabulation Method and draw logic diagram using
NOR gates only F(w,x,y,z ) = ( 0 ,1 , 2 , 8 ,10 ,11,14,15 )
Determine the Prime Implicants of following Boolean Function using Tabulation
Method.
F(A,B,C,D,E,F,G)=(20,28,38,39,52,60,102,103,127)
Simplify the following Boolean function using K-Map.
F=ABC+BCD+ABCD+ABC

Chapter- 4 Combinational Logic
Design a combinational circuit that accepts a three bit binary number and generates an output binary
number equal to the square of the input number.
With necessary sketch explain full adder in detail
Design a 4 bit binary to BCD code converter
Design a combinational circuit that generates the 9 complement of a BCD digit
Design a full-adder with two half-adders and an OR gate
Implement Boolean expression for Ex-OR gate using NAND gates only
Draw symbol and truth table for four input EX-OR gate. Explain NAND and NOR as an universal gate
Simplify Boolean function F ( w,x,y,z ) = ( 0,1,2,4,5,6,8,9,12,13,14 ) using K-map and Implement it using (i)
NAND gates only (ii) NOR gates only
Design the Combinational Circuits for Binary to Gray Code Conversion.
Explain Design Procedure for Combinational Circuit & Difference between Combinational Circuit &
Sequential Circuit.
Explain with figures how NAND gate and NOR gate can be used as Universal gate.
Implement the following Boolean functions (i) F= A (B +CD) +BC with NOR gates (ii) F= (A + B) (CD + E) with
NAND gates
Design a BCD to decimal decoder
Design a combinational circuit whose input is four bit binary number and output is the 2s complement of
the input binary number.
Design BCD to Excess-3 code converter using minimum number of NAND gates

Chapter- 5 Combinational Logic With MSI AND LSI
Discuss 4-bit magnitude comparator in detail
Design a full adder circuit using decoder and multiplexer
write short note on EEPROM,EPROM and PROM
Define: [1] Comparator [2] Encoder [3] Decoder
[4] Multiplexer [5] De-multiplexer [6] Flip Flop [7] PLA
What is multiplexer? Implement the following function with a multiplexer: F(A,B,C,D) = (0 , 1 ,
3 , 4 , 8 , 9 ,15 )
Write short note on : Read Only Memory (ROM)
A combinational circuit is defined by functions: F1(A,B,C) = ( 3 , 5 , 6, 7 ) ,F2(A,B,C) = ( 0 , 2
, 4, 7 ) Implement the circuit with PLA having three inputs ,four product term and two outputs
What is meant by multiplexer? Explain with diagram and truth table the Operation of 4-to-1 line
multiplexer
What is meant by decoder? Explain 3-to-8 line decoder with diagram and truth table
Construct 4*16 Decoder with help of 2*4 Decoder.
Discuss 4 bit BCD Adder in Detain.

Chapter- 6 Sequential Logic
Discuss D-type edge- triggered flip-flop in detail
(i)With neat sketch explain the operation of clocked RS flip
(ii)Show the logic diagram of clocked D
With logic diagram and truth table explain the working JK Flipflop. Also obtain its characteristic
equation. How JK flip-flop is the refinement of RS flip-flop?
Draw and explain the working of following flip-flops [1] Clocked RS [2] JK
Convert SR flip-flop into JK flip-flop
Draw logic diagram , graphical symbol , and Characteristic table for clocked D flip-flop
What is race-around condition in JK flip-flop?
Explain working of master-slave JK flip-flop with necessary logic diagram , state equation and state
diagram
Explain the working of the Master Slave J K flip-flop
Explain the procedure followed to analyze a clocked sequential circuit With suitable example
Explain Master Slave Flip Flop through J.K Flip Flop
Give comparison between combinational and Sequential logic circuits
Design a counter with the following binary sequence:0,4,2,1,6 and repeat (Use JK flip-flop)
Design a counter with the following binary sequence:0,1,3,7,6,4, and repeat.(Use T flip-flop)
Design sequential counter as shown in the state diagram using JK flip-flops
Design Sequential Circuit with J.K. Flip Flops to satisfy the following state
equation.
A( t + 1 ) =A B CD + A B C + ACD +AC D
B(t+1)= A C + CD + A BC
C(t + 1) = B
D(t +1)=D

Chapter- 7 Registers Transfer Logic & Micro-Operation
Discuss Interregister Transfer in detail
With respect to Register Transfer logic, explain Inter-register Transfer with necessary diagrams.
Prepare a detailed note on: Instruction Codes.
State and explain the features of register transfer logic
Explain briefly: (i) logic and shift micro-operations (ii) fixed-point binary data and floating-point
data
Define : state table , state equation , state diagram , input & output equations
Define the different mode of operation of registers & explain any two in details.
Explain Macro operations Versus micro operations

Chapter- 8 Registers, Counters and the Memory unit
Draw the state diagram of BCD ripple counter, develop its logic diagram, and explain its
operation.
Construct a Johnson counter with Ten timing signals.
What is the function of shift register? With the help of simple diagram explain its working. With
block diagram and timing diagram explain the serial transfer of information from register A to
register B.
With logic diagram explain the operation of 4 bit binary ripple counter. Explain the count
sequence, How up counter can be converted into down counter?
Explain the working of 4 bit asynchronous counter
Explain memory unit
Give classification of counters and explain asynchronous 4-bit binary ripple counter
Explain working of 4-bit binary ripple counter
Draw and explain block diagram of 4-bit bidirectional shift register with Parallel load
How many flip flops are required to build a shift register to store following
numbers.
i) Decimal 28
ii) Binary 6 bits
iii) Octal 17
iv)Hexadecimals A
Explain 4-bit up-down binary synchronous counter.
Explain Johnson Counters.

Chapter- 9 Processor Logic Design
What is scratchpad memory? With diagram explain the working of a processor unit employing
a scratchpad memory.
Draw the block diagram of a processor unit with control variables and explain its operation
briefly.
Explain the design of Arithmetic Logic Unit
Draw block diagram of a 4-bit arithmetic logic unit. Design an adder / 5subtractor circuit with
one selection variable S and two inputs A and B .when S = 0 circuit performs A+B, when S =
1 circuit performs A B by taking the 2s complement of B
Explain Arithmetic micro operations
Explain Arithmetic addition and arithmetic subtraction.
Briefly explain processor unit with a 2-port memory
Explain common cathode types seven segments displays.

Chapter- 10 Control Logic Design
With simple diagram explain the working of control logic with sequence register and decoder.
Briefly explain control organization. With diagram explain control logic with one flip-flop per state.
Explain Control Logic Design
Draw and explain block diagram of microprograme control.
What is the difference between hardwired control and micro program control? Write advantages and
disadvantages of each method
Write the Comparisons between Hard wired control and micro programmed
Controls.

PREPARED BY ASST. PROF NIRAV PATEL Page 1

CHAPTER-10
CONTROL LOGIC DESIGN

GTU QUESTION BANK

1. With simple diagram explain the working of control logic with sequence register and decoder.
2. Briefly explain control organization. With diagram explain control logic with one flip-flop per
state.
3. Explain Control Logic Design
4. Draw and explain block diagram of microprograme control.
5. What is the difference between hardwired control and micro program control? Write advantages
and disadvantages of each method
6. Write the Comparisons between Hard wired control and micro programmed
Controls.

QUE 1 TO 4==Chapter 10 (Control Logic Design) ------------------------------Morris Mano
Topic-10.2 Control Organization-------------------------Page No-409 to 415
(With four methods1. One flip-flop per state method
2. Sequence register and decoder method
3. PLA control
4. Microprogram Control)

QUE-5 what are the advantages and disadvantages of hardwired and micro-programmed
control?

ANS

Hardwired control

Advantages
It is implemented using the gates, Flip Flops and hardware circuits. High speed operation
and hence execution is faster
Smaller implementation (component counts)
Favored approach in RISC style designs.
Disadvantages
Complex sequencing and micro operation logic.
Difficult to design and test
Inflexible design
Difficult to add new instructions


Micro-programmed control

Advantages
It stores the control signals in the sequence in control memory.
Modification is simple by modifying the micro program in the control memory.
Just read from the control memory every clock cycle
Favored approach in CISC style designs.
Disadvantages
Execution is slow
Separate Control memory is used

QUE-6. State the differences between hardwired and micro-programmed control unit.
Hardwired control Micro programmed control

ANS

DIGITAL LOGIC DESIGN

Prepared By Nirav Patel EEE Dept

CHAPTER-1

BINARY SYSTEMS

REMEMBER THESE:
There are two input signals: analog signals have infinite number of distinct values and are
continuous, while digital signals have finite number of distinct values and are discrete in
nature.
Types of number systems are : decimal, binary, octal, hexadecimal.
There are two logic levels in digital system : high (1) and low (0).
Number of values that a character or digit can assume is called Radix or Base. For Ex. -
Decimal system has radix 10.
Leftmost digit is MSD (Most Significant Digit) and rightmost digit is LSD (Least
Significant Digit).
Binary system has radix 2 and two binary digits one 1 and 0. Its weight is expressed as
a power of 2.
The smallest unit of information is called bit (0 and 1).
Binary representation of four bits is called a Nibble.
A byte is a combination of 8-binary bits.
A word is a combination of 16-binary bits.
Octal numbers system has radix 8 and the digits are (0 to 7). Its weight is expressed in
power of 8.
Hexadecimal has radix 16. The digits are 0 to 9 in continuation with letters A to F Its
weight is expressed in power of 16.
ls complement of a binary number is written by simply replacing all 0s by 1 and all 1s by
0.
2s complement is one increment of ls complement.
Numbers without +ve / -ve sign are unsigned numbers.
Numbers represented by sign magnitude are signed numbers.
BCD represent as 4 bit binary code; also known as 8421 code.
Excess 3 codes are obtained by addition of three Le. (0011)2 to BCD and is set
complementary,
Gray codes are reflected codes in which the successive coded characters differ in only bit
position.



TYPES OF NUMBER SYSTEM:

Following table shows the various, number system with their radix (r) or base (b).

(1). The Decimal Number System: The number system having radix or base 10 is called as
decimal number system. The number which we make use in our life is called decimal number
system. The decimal system has the base value of 10. So, its maximum or largest value of digit is
(r 1) = 10 1 = 9,
where r = radix or base. Decimal position values as powers of 10 are as shown:

(2). Binary Number System: The number system having radix or base 2 is called as binary
number system. As the radix or base value of binary number system is 2, so its maximum value
of digit

(r 1) = (2 1) = 1, where r is radix or base.

The two binary digits are 1 and 0. in binary system each binary digit is known as bit and has
its own weight or value. Its weight is expressed as a power of 2.


(3). Octal Number System: The number system which make use of radix 8 is known as octal
number system. As the radix or base of octal number system is 8, so its maximum or largest
value of a digit is

(r 1) = (8 1) = 7 where r is radix or base.

It make use of first eight digits of decimal number system i.e. 0, 1, 2, 3, 4, 5, 6 and 7.
Thus, 8 and 9 digits never come in octal number system. Octal positions values as a power of 8
are as shown:

(4). Hexadecimal Number System: The number system having radix or base 16 is called as
hexadecimal number system.. In short these are known as hex system. The number of values
assumed by each digit is 0 through 9 and letters A, B, C, D, E and F. Thus the sixteen possible
values are


0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F,

Here A represents 10
B represents 11
C represents 12
D represents 13
E represents 14
F represents 15
The largest value or maximum value for the system is
(r 1) = (16 - 1) = 15

For e.g.

CONVERSION OF DIFFERENT NUMBERS:

(I) Conversion from binary to decimal:

Que. Convert the binary number (110)
2
to its decimal equivalent.
Solution.

Que. Convert the binary number (1011.01) to its decimal equivalent.
Solution.

Que. Convert (11011.111)
2
= (?)
10

Solution.



(II) Conversion from octal to decimal:

Que. Convert (71)
8
= (?)
10

Solution.

Que. Convert the following
(521.63)
8
= (?)
10

Solution.

Que. Convert the following:
(385.24)
8
= (?)
10

Solution.

(III) Conversion from hexadecimal to decimal:

(3A)
16
> (?)
10

Solution.

(2B.48)
16
> (?)
10

Solution.


(4C8.2)
16
> (?)
10

Solution.

(IV) Conversion from decimal to binary

Que. Convert (14)
10
= (?)
2

Solution.

Que. (204)
10
= (?)
2

Solution.



Que. (0.6875)
10
= (?)
2

Solution.

(V) Conversion decimal to octal

Que. Convert (241)
10
= (?)
8

Solution.

10
= (?)
8

Solution.

10
= (?)
8

Solution.



(VI) Conversion from decimal to hex.

Que. Convert (80)
10
= (?)
16

Solution.

10
= (?)
16

Solution.

(0.122)
10
= (0.1F3B64)
16

10
= (?)
16

Solution.



(VII) Conversion from binary to octal

Que. Convert (10110)
2
= (?)
8

Solution.

2
= (?)
8

Solution.

(11010010)2 = (322)8

2
= (?)
8

Solution.

(0.1011011)2 (0.554)8

(VIII) Conversion from binary to hexadecimal

2
= (?)
16

Solution.

(1010111) 2 = (57)16

Que. Convert (1010 1111 1011 0010)
2
= (?)
16

Solution.

(1010 1111 1011 0010) 2 = (AFB2)16



Que. Convert (10110110.101111001) 2 = (?)16
Solution.

(10110110.101111001) 2 = (B6.BC8)16

(IX) Conversion from octal to hexadecimal

Que. Convert (436)
8
= (?)
16

Solution.

(X) Conversion from hexadecimal to octal

Que. Convert (1AF)
16
= (?)
8

Solution.

Que. Convert (3CFB.2E)
16
= (?)
8

Solution.


Que. Convert (68.4B)
16
= (?)
8

Solution.

Que. What is the largest decimal number that can be represented by a 16 bit binary word?
Ans.

=15 x 4096 + 15 x 256 + 15 x 16 + 15
= 61440 + 3840 + 240 + 15
= (65535)
10

Thus, 65535 is the largest decimal number that can be represented by a 16 bit binary word.

Que. Convert the decimal number 39.75 to octal.
Ans. (39.75)
10
= (?)
8

Integer part:

(39)
10
= (47)
8

Fractional part:
0.75 x 8 = 6.0
(0.75)
10
= (0.6)
8

Ans: (39.75)
10
= (47.6)
8



Que. Represent the decimal number 8620 in BCD and as a binary number.
Ans. BCD:
(1000 0110 0010 0000)

Binary:

Que. Convert decimal 225.225 to binary, octal and hexadecimal bases.
Ans. 225.225



Que. Convert decimal 100. 625 to binary, octal and hexadecimal codes.
Ans. In binary:

(1100100.101)2

In Octal:

(144.5)8

In Hexadecimal:

(64.A)16

Que. How negative numbers are accounted for in digital system?


Ans. In digital system sometimes signed numbers are used. To denote positive numbers (+) plus
sign is used and 0 is used as MSB bit in binary numbers. In case of negative numbers (-) minus
sign is used to denote it. In binary system, bit us used as MSB bit in negative numbers.
e.g. (+7)2 = (0111)
2

(-7)2 = (1111)
2

Que. Give the binary code for the hexadecimal number F01.
Ans. (F01)16 = (?)
2

Que. Determine the decimal representation of a negative integer whose 8bit twos
complement code 10010110.

Ans. 8-bit 2s complement code is:
10010110
Its 2s complement is:

Que. Define bit, byte and nibble.

Ans. 1. Bit : Bit is an abbreviation of the binary digit and it is the smallest unit of
information. It is either 0 or 1.
2. Byte : A byte is a combination of 8-binary bits A byte contains two nibbles. It is used in case
of representation of memory.
3. Nibble : Binary representation of four bits is called a nibble. In case of BCD i.e. binary coded
decimal and hexadecimal numbers nibble is used as both are four bit numbers.

Q 32. Find the complement of

Ans.


Its complement is given by:



COMPLEMENTS:

1s & 2s complements:

In 1s complement 1 is replaced by 0 and 0 is replaced by 1.

2s complement is obtained by adding 1 to the least significant digit of the 1s complement.

Que. Find twos complement of the numbers (i) 01001110 ; (ii) 01100100.
Ans (i) 01001110

(ii) 01100100.











BINARY ADDITION



BINARY SUBTRACTION



BINARY MULTIPLICATION



Que (378)
5
0 (438)
5

Ans

3 7 8
04 3 8
3 3 4 2 0 0
2 4 0 4 0
7 2 3 4
4 3 1 0 2 4

Que (249)
4
0 (112)
4

Ans

3 7 8
04 3 8
3 2 1 0 0
3 2 1 0
1 3 0 2
1 0 3 2 1 2



BINARY DIVISION



Que. If A = 1101 and B = 101 find:
(i) A+B
(ii) A0B

Ans:

Que. If A = 1101 and B = 101 find:
(iii) A-B
(iv) B-A
By 2s complement method.

Ans A = 1101, B = 0101

(i)

(ii)









EXCESS-3 ARITHMETIC

Truth table-BCD to Excess-3 codes





Que. Add the following numbers in Excess - 3 Code.
(i) 108 + 789
(ii) 275 + 496

Ans. Add in excess-3 code

(i) Firstly converting (108)10 and (789) 10 to excees-3 form

Adding

If no carry i.e. c = 0, subtract 0011
If carry i.e. c = 1, add 0011

(ii) (275)
10
+ (496)
10

Firstly, converting into Excess-3 form

Addition of (275)
10
+ (496)
10

If no carry i.e. c = 0, subtract 0011
If carry i.e. c = 1, add 0011 to sum



= (1010 1010 0100) or (771)
10

Que. Subtract the following numbers
(i) (BC5)16 (A2B)16 = ?
(ii) (1 75.6)8 (47.7)8 = ?

Ans. (i) Firstly, convert it into binary form (4 digits)

(ii) Firstly, convert it into binary (3 digits)

Que. Add the following numbers in BCD
(i) 89.6 + 273.7
(ii) 205.7 + 193.65

Ans, (i) 89.6 + 273.7

Add (0110)2 to only the invalid BCD numbers.

(ii) 205.7 + 193.65


Add (0110)2 to only the invalid BCD numbers.



GRAY CODE

Truth table-Binary to gray code



Que. What is the importance and applications of Gray code? Convert the binary number
10100111 to Gray code.

Ans. Importance of gray code is that it has a very special feature as only one bit will change each
time when the decimal number is incremented by 1. Due to this reason it is also known as unit
distance code.
Applications of Gray Code
1. These are used in the shaft position encoders.
2. These are used in the optical discs to produce an appropriate binary code.

Que. Represent the decimal numbers (a) 27, (b) 396 and (c) 4096 in binary form in (i) Gray
code and (ii) Excess 3 code.

Ans.

(11011)2
(27)10 = (11011)2
(27)10 = 00100111 in BCD

(i) Gray Code
(11011)2 =

(ii) Excess 3 Code
(27)10



Binary = (101111000)2
(396)10 = 0011 1001 0110 BCD

(i) Gray Code

(ii) Excess 3 Code

(c) (4096) =



(4096)10 = (1000000000000)2

(i) Gray Code

(ii) Excess 3 Code



CHAPTER-2

BOOLEAN ALGEBRA & LOGIC GATES

REMEMBER THESE:

Logic gates most commonly used are AND, OR. NOT. NAND, NOR, XOR. XNOR.
NAND and NOR are universal gates.
Output of AND gate is low even if one input is low (Y = A.B) where A and B are inputs
and Y is the output.
Output of OR gate is high if any one input is high (Y = A + B)
In NOT gate, when a high is applied as input, a low appears at output and vice versa.
NAND gate has output high when any one of its input is low.
The output of NOR gate is high when any input is low.
Output of XOR gate is high if only one input is high.
The output of XNOR gate is high when all inputs are high.
NAND and NOR can be used to realize any gate.



LOGIC OPERATION



AXIOMS & LAWS OF BOOLEAN ALGEBRA





















DUALITY







CANONICAL AND STANDARD FORM







& Maxterm= [ (3)

& Maxterm= [ (, 1, 2, 3, , 7)



& Minterm= _ (3)

& Minterm= _ (, 7)



DIGITAL LOGIC GATES



NAND & NOR ARE THE UNIVERSAL GATES.
Implementation with NAND Gate
The NAND gate is said to be a universal gate because any digital system can be implement
with it. Logic operation AND, OR, NOT can be implanted with NAND.
The equivalent circuit of AND, OR, NOT & NOR, EX-OR gate in the form of NAND gate is as
shown in fig.

1.) NAND as NOT gate

Truth Table
Input A Output Y = A
0 1
1 0

2.) NAND as OR Gate

Truth Table
A B a = A b = B Y = [A.B]= A+B
0 0 1 1 0
0 1 1 0 1
1 0 0 1 1
1 1 0 0 1

Logic

Circuit

Logic

Circuit

Prepared By Nirav Patel

3.) NAND as NOR Gate

Truth Table
A B a = A
0 0 1
0 1 1
1 0 0
1 1 0

4.) NAND as AND Gate

Truth Table
A B
0 0
0 1
1 0
1 1

5.) NAND as XOR Gate


b = B c = [A.B] = A+B Y=c=[A+B]
1 0 1
0 1 0
1 1 0
0 1 0

a = [A.B] Y= a = A . B
1 0
1 0
1 0
0 1

Logic

Circuit

Logic

Circuit

Logic

Circuit

EEE Dept
Y=c=[A+B]


Truth Table
A B a = [A.B] b = [A.B] Y= [a.b] =
AB+AB
0 0 1 1 0
0 1 0 1 1
1 0 1 0 1
1 1 1 1 0

NOR AS A UNIVERSAL GATE:
The NOR is the dual of the NAND function. Any Boolean function
as well as a flip-flops can be implemented using NOR gate. The conversion of
AND, OR, NOT & NAND, EX-OR gate is shown in the fig.

1.) NOR as NOT Gate

Truth Table
Input A Output Y = A
0 1
1 0

2.) NOR as OR Gate

Logic

Circuit

Logic

Circuit


Truth Table
A B
0 0
0 1
1 0
1 1

3.) NOR as AND Gate

Truth Table
A B a = A
0 0 1
0 1 1
1 0 0
1 1 0

4.) NOR as NAND Gate

a = [A+B] Y = a = A+B
1 0
0 1
0 1
0 1
b = B Y=[a+b]=[A.B]
1 0
0 0
1 0
0 1

Logic

Circuit

Logic

Circuit

EEE Dept


Truth Table
A B a = A
0 0 1
0 1 1
1 0 0
1 1 0

5.) NOR as XOR Gate

Truth Table
A B
0 0
0 1
1 0
1 1

b = B c=[a+b]=[A.B] Y=c=[A.B]
1 0 1
0 0 1
1 0 1
0 1 0
a =[A+B] b =[A+B] Y= [(a+b)]
= AB+AB
0 0 0
1 0 1
0 1 1
0 0 0
Logic Circuit

EEE Dept
Y= [(a+b)]




CHAPTER-3

SIMPLIFICATION OF BOOLEAN FUNCTION

REMEMBER THESE:

SOP involves sum of given product terms and these terms are known as minterms (m).
POS involves product of given sum terms of these are known as maxterms (M).
A karnaugh map is simply a graphical method for representing a boolean function. It is used
to simplify a logic equation or to convert a truth table to its logic circuit.
Types at K-map are 2 variable, 3 variable, 4 variable, 5 variable and 6 variable.
= M formula is used for the calculation of total number of squares in a K-map. Here,
n=number of variables and M = number of squares.
For representing SOP form for K map: enter 1 for each minterm and 0 otherwise.
To minimize the boolean expression using K-map, pair, Quad and octet are formed in
increasing priority.
Q-M method or Quine Mc-Clusky method or Tabular minimization method is used for large
number of variables if increases from 6 variable i.e. for 7, 8, 9 or oven 10 variables. K-map
method fails for large number of variables.
Incompletely specified functions are dont care conditions. In these cases output level in rot
defined, it can be high or low i.e. 1 or 0.Dont care conditions are marked by d or x.



Que. What is K-map? Why we need K-maps? Give the various types of K-map.
Ans. K-map i.e. Karnaugh map is simply a graphical method for representing a Boolean fraction.
The Karnaugh map is a systematic method for simplify and manipulating Boolean expression. It
is used to simplify a logic expression or to convert a truth table to its corresponding logic circuit.
It is used for the minimization of switching functions but upto six variables. For more than
six variable it becomes complex or cubersome.
The K-map for n-Boolean variable switching function consists of squares. Here square
represents the normal or standard term i.e. one minterm or maxterm.
Need of K-maps: We need K-map for representing Boolean function through graphical method.
Because K-map simplify and manipulates a Boolean expression. So to solve or simplify a
Boolean expression, we use K-map. K-map can be used for problems involving any number of
input variables (upto six variables) which is not easily solve by Boolean Algebra. Types of K-
map :
Types of K-maps commonly used are
1. Two variable K-map
2. Three variable K-map
3. Four variable K-map
4. Five variable K-map
5. Six variable K-map



TWO VARIABLE K-MAP:

= M formula is used where, n = Number of variables and M = Number of squares.

SOP form POS form

SOP form



POS form



THREE VARIABLE K-MAP:

SOP form(Minterms) POS form(Maxterms)





FOUR VARIABLE K-MAP:

Formula used is = M
Where, n = number of variables, M = Number Of squares
n = 4

So, 4 variable K-map consists of 16 squares.



FIVE VARIABLE K-MAPS:
Five variable K-map has squares and five
variables are A, B, C, D and E. It is shown in figure.



Que. Solve following using K-map and Boolean algebra:

Solution.

Using boolean,

So Y = B, is the simplified expression.

Using boolean,



Que. Solve following using K-map and boolean algebra:

Solution.

Using boolean,

Using boolean,

Minimized output of K-map is V = C

Using boolean,


Que. Solve the following using K-map and verify by using boolean algebra:
(i) F (A, B, C, D) = (3, 4, 5,7, 9, 13, 14, 15)

Solution

(ii) F (A, B, C, D) = (0, 1, 2, 3, 6, 8, 9, 10, 11, 12, 13)

Solution.



(iii) F (A, B, C, D) = (0, 1, 4, 5, 3, 2, 11, 10)

Solution



Sum of Product Product of sum



NAND & NOR IMPLEMENTATION











Example









Que. Construct the truth table for F =

Ans Truth table for F =
This is the output of an XOR gate.
Truth Table :

Que. A four-variable function is given as f (A, B, C, D) = (0, 2, 3, 4, 5, 7, 8, 13, 15). Use
a K-map to minimize the function.

Ans. f (A B, C D) = (0, 2, 3, 4 5, 7, 8, 13, 15)

Que. Simplify the expression 2. =AB + AC + ABC (AB + C). Implement using minimum
number of NAND gates.

Ans Z = AB + AC + ABC (AB + C)
= AB + AC + ABC. AB + ABCC
= AB + AC + ABC + ABC
= AB + AC + ABC
=AB(1 + C) + AC
= AB + AC
Implementation using minimum number & NAND gates:


Que. Minimize the function using K-map.
f (A, B, C, D) = (0, 1, 2, 3, 5, 7, 8, 9, 11,14)

Ans.

Que. Obtain the minimal SOP expression for (0, 1, 2, 4, 6, 9. 11, 12, 13) and implement it in
NAND logic.

Ans. f (A, B, C, D) = (0, 1, 2, 4, 6, 9. 11, 12, 13)
Firstly K-map

Circuit diagram using NAND only


Que. Obtain the minimal POS expression for (0, 1, 2, 4, 5, 6, 9, 11, 12, 13, 14, 15) and
implement it in NOR logic.

Ans. Firstly, fill given os in K-map, to get the expression in POS form.

Implementation using NOR gates



Que. Simplify the function using Karnaugh map and implement using minimum Lumber
of logic gates.
F = (2, 9, 10, 12, 13) + D(1, 5, 14)
What are the limitations of Karnaugh map?

Ans. F = (2, 9, 10, 12, 13) + D(1, 5, 14)
K-map:

Implementation using minimum number of logic gates can be obtained from the minimized
output of the given function.
Implementation is as shown:

Limitations of K-map:
For large number of variables i e more than six variables the K-map becomes cumbersome It is
difficult to solve the output of K-map having 7 8 and more variables as it covers more space and
need large time for calculations Also, the K-map for 6 variables is possible and for more
variables Q-M method or tabular minimization method is used



DONT CARE CONDITION:

Incompletely specified functions are dont care conditions. In these cases output level in rot
defined, it can be high or low i.e. 1 or 0.Dont care conditions are marked by d or x.



Que. Solve the following using k-map:
f (A, B, C, D) = (0,2, 3, 8, 11, 12) + d (1,9, 14)

Ans. K-map is as shown:





TABULATION METHOD

Que. Obtain the set of prime implicants for = (1,4,6,7,8,9,10,11,15) using the binary
designations of min-terms using tabulation method(Q M method).
Ans:-
{ {

Detemine the prime implicants



Selection of prime implicants



Que. Obtain the set of prime implicants for = (0,1,2,8,10,11,14,15) using the binary
designations of min-terms using tabulation method(Q M method).
Ans:-
{ {

F=wxy+xz+wy




Que. Obtain the set of prime implicants for (0, 1, 6, 7, 8, 9, 13, 14, 15) using the binary
designations of minterms using Q-M method.

Ans.

{ {

F=ACD+ABD+BC+BC


CHAPTER-4

COMBINATIONAL LOGIC

LOGIC CIRCUIT- A circuit that behaves according to a set of logic gates.

Logic circuit

Combinational logic circuit Sequential logic circuit

Que. Explain Design Procedure for Combinational Circuit & Difference
between Combinational Circuit & Sequential Circuit.
Ans.
Combinational Circuits: - In these circuits the outputs at any instant of time depends on the
inputs present at that instant only.

The design procedure involves the following steps:
1. Problem description
2. Inputs/outputs of the circuit
3. Define truth table
4. Simplification for each output
5. Draw the logic circuit

Difference between combinational circuit and sequential circuit
S.No. Combinational Circuit Sequential Circuit
1.
The outputs depend only on the present time inputs.

The outputs depend only on the present time
inputs as well as the past time outputs.
2. It contains no memory elements. It contains memory elements.
3. It contains no feedback.
It contains feedback.

4.
Examples for combinational digital circuits are
Half adder, Full adder, Half subtractor, Full
subtractor, Code converter, Decoder, Multiplexer,
Demultiplexer, Encoder, ROM, etc.

Examples for sequential digital circuits are
Registers, Shift register, Counters etc.

5.
Combinational Circuits are faster than sequential
circuits.
Sequential circuits are slower.
6. Combinational Circuits are easy to design.
Sequential circuits are comparatively harder to
design.
7.

HALF ADDER:-

A half adder is a logical circuit that performs an addition operation on two binary digits. The half
adder produces a sum and a carry value which are both binary digits.

The sum(s) bit and carry(c) bit , according to the rules of binary addition, are given by:
Truth Table:

Input A Input B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

For sum:

Sum=AB+AB

For carry::

Carry=AB

A half-adder can realized by using one X

Circuit Diagram:

by using one X-OR gate and one AND gate as shown in the figure.

OR gate and one AND gate as shown in the figure.
FULL-ADDER CIRCUIT

OR

DESIGN A FULL-ADDER WITH TWO HALF-ADDERS AND AN OR
GATE.

A Full Adder is a combinational circuit that performs the arithmetic sum of three input bits. It
consists of three inputs and two outputs. Three of the input variables can be defined as A, B,
Cin and the two output variables can be defined as S, Cout. The two input variables that we
defined earlier A and B represents the two significant bits to be added. The third input
Cin represents the carry bit. We have to use two digits because the arithmetic sum of the three
binary digits needs two digits. The two outputs represents S for sum and Cout for carry.

For designing a full adder circuit, two half adder circuits and an OR gate is required. It is the
simplest way to design a full adder circuit. For this two XOR gates, two AND gates, one OR
gate is required.

Truth Table:

Input A Input B Input C
in
Output C
out
Output S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
From the truth table, a circuit that will produce the correct sum and carry bits in response to
every possible combination of A,B and Cin is described by

Solution using K-map

For Sum

S=A'B'C
in
+A'BC
in
'+AB'C
in
'+ABC
in

=C
in
'(AB'+A'B)+C
in
(AB+A'B')
=C
in
'(AB'+A'B)+C
in
(AB'+A'B)'
= C
in
(A B)

For C
out

C
out
=AB+AC
in
+BC
in

=C
in
(AB'+A'B)+AB

= C
in
(A B)+AB

Circuit Diagram

Implementation of Full-adder in sum of product

Implementation of Full-adder with two half-adder and OR gate

HALF-SUBTRACTOR CIRCUIT

Half subtractor (HS):
This circuit subtracts two bits and gives Borrow andDifference as 2 outputs. The
following table shows the result for different combinations of inputs:

We can easily see that difference is 1 only when we have one of the inputs as 1 and other
as 0 just like a XOR gate.
So equation for difference is D= ab + ab
We can also obtain the equations using K-maps

And the digital circuit to implement the above functions is as follow:

FULL SUBTRACTOR

The subtraction of two binary numbers may be accomplished by taking the complement of the
subtrahend and adding it to the minuhend. By this method, the subtraction operation becomes an
addition operation requiring full adders for its machine implementation. It is possible to
implement subtraction with logic circuits in a direct manner. By this method, each subtrahend bit
of the number is subtracted from its corresponding significant minuhend bit to form a different
bit. If the minuhend bit is smaller than the subtrahend bit, a 1 is borrowed from the next
significant position. The fact that a 1 has been borrowed must be conveyed to the next higher
pair of bits by means of a binary signal coming out (output) of a given stage and going into
(input) the next higher stage. It is same for the half-adder and full-adder, half-subtractor and full-
subtractor circuits.

A full-subtractor is a combinational circuit that performs a subtraction between two bits, taking
into account that a 1 may have been borrowed by a lower significant stage. The circuit has three
inputs and two outputs. The three inputs is denoted by a, b and c which represent the minuhend,
subtrahend and the previous borrow bit respectively.

Truth Table

Input a Input b Input c Output B Output D
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Solution Using K-Map

For Difference

D=a'b'c+a'bc'+ab'c'+abc

For Borrow

B=a'b+a'c+bc

Circuit Diagram

Que. Design the Combinational Circuits for Binary to Gray Code Conversion.

Ans.

Que.Design BCD to Excess-3 code converter.

Ans.

BCD to Excess-3 Code Converter:
The input variables are BCDs (A, B, C and D) and output variables are excess-3 code (E3, E2,
E1 and E0)

Truth Table

Minimization Using K-map:

For E3

E3 = A + BD + BC
For E2

For E1

For E0

Implementation of Excess-3 Code Converter:


CHAPTER-5
COMBINATIONAL LOGIC WITH MSI AND LSI(IMP QUE.)

Que 1--Combinational logic implementation-Full adder with a decoder
Ans- A Full Adder is a combinational circuit that performs the arithmetic sum of three input bits.
It consists of three inputs and two outputs. Three of the input variables can be defined as X,Y,Z
and the two output variables can be defined as Sum, Carry.
Truth Table:

INPUTS OUTPUTS
X Y Z C Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

So, S(X,Y,Z)=(1,2,4,7)
C(X,Y,Z)=(3,5,6,7)
Implementation of full-adder with a decoder:

Que 2- Construct a 5-to-32-line decoder with four 3-to-8-line decoders with enable and a 2-
to-4-line decoder. Use block diagrams for the components
Ans-5-to-32-line decoder

We need four 3- to -8 decoder for the last stage and one 2-to-4 decoder for selecting each of
them at the first stage.

Que 3- Design a combinational circuit using a ROM. The circuit accepts a 3 bit number
and generates an output binary number equal to the square of the input number.
Ans-The first step is to derive the truth table for the combinational circuit. So for this example
the truth-table is:

Three inputs and six outputs are needed to accommodate all possible numbers. We note that
output B
0
is always equal to input A
0
.So there is no need to generate B
0
with a ROM since it is
equal to an input variable. Moreover, output B
1
is always 0, so the output is always known. We
actually need to generate only four outputs with the ROM. So the minimum size ROM needed
must have three inputs and four outputs. Three inputs specify eight words, so the ROM size must
be 84.The ROM implementation is shown in the figure.


Que 4-Implement full-adder with two 41multiplexer.
Ans-The truth table for the full adder is:

INPUTS OUTPUTS
X Y Cin Cout Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Now for Multiplexer
X,Y=Selection lines
Bin=input
For Sum

For Cout


Implement full adder with the help of two 41 multiplexer:

DLD GTU Question Bank: Chapter-1 Binary System

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PREPARED BY: Prof Nirav R. Patel, EEE Dept.

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