Anagram

Script started on Tue 05 Mar 2013 10:48:39 AM CST [root@localhost 32]# cd /simplesim-3.0/ mysim_anagram.exp <<.
/sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 i l2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb:dtlb none ./benc hmarks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 il2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb :dtlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:54 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
false false false false 1 false <null> <null>
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:l # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:l # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
<null> # profile stat(s) against text addr's (mult uses o
The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl>
<name> <nsets> <bsize> <assoc> <repl> Examples:
name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 431 # total number of accesses il2.hits 1 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9977 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref)
dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 322 # total number of accesses dl2.hits 52 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.8385 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 i l2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb:dtlb none ./benc hmarks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 il2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb :dtlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:54 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # # # # # # -config -dumpconfig -h -v -d -i # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger
false false false false
-seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)
1 false <null> <null>
# # # #
random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:f # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:f # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses
il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 431 # total number of accesses il2.hits 1 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9977 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 322 # total number of accesses dl2.hits 52 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.8385 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 i l2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb:dtlb none ./benc hmarks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary
sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 il2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb :dtlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:54 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:r # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:r # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 431 # total number of accesses il2.hits 1 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9977 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 322 # total number of accesses dl2.hits 52 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.8385 # miss rate (i.e., misses/ref)
dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 i l2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:dtlb none ./benchm arks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 il2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:d tlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:54 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute
-cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)
dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:l # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:l # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 431 # total number of accesses
il2.hits 1 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9977 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 322 # total number of accesses dl2.hits 52 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.8385 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 i l2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:dtlb none ./benchm arks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored...
sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 il2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:d tlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:54 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:f # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:f # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 431 # total number of accesses il2.hits 1 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9977 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 322 # total number of accesses dl2.hits 52 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.8385 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes
ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 i l2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:dtlb none ./benchm arks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 il2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:d tlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:54 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:r # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:r # l2 instruction cache config, i.e., {<config>| none # instruction TLB config, i.e., {<config>|none} none # data TLB config, i.e., {<config>|none}
-flush -cache:icompress ivalents # -pcstat k)
false # flush caches on system calls false # convert 64-bit inst addresses to 32-bit inst equ <null> # profile stat(s) against text addr's (mult uses o
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 431 # total number of accesses il2.hits 1 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9977 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref)
il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 322 # total number of accesses dl2.hits 52 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.8385 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:54 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration,
which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches **
warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 753 # total number of accesses dl2.hits 53 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9296 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary
sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:54 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 753 # total number of accesses dl2.hits 53 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9296 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack)
ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:54 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ
ivalents # -pcstat k)
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 753 # total number of accesses
dl2.hits 53 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9296 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:54 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately
false false false false 1 false
# -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks
il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 753 # total number of accesses dl2.hits 53 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9296 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i
sim: simulation started @ Tue Mar 5 10:48:54 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 753 # total number of accesses dl2.hits 53 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9296 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 d
l2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:54 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> name of the cache being defined number of sets in the cache block size of the cache associativity of the cache
<repl> Examples:
- block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 753 # total number of accesses dl2.hits 53 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 7 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9296 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0093 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base
ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 i l2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb:dtlb none ./benc hmarks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 il2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb :dtlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:54 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:l # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:l # l2 instruction cache config, i.e., {<config>
-tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)
none none false false
# # # #
instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 431 # total number of accesses il2.hits 1 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9977 # miss rate (i.e., misses/ref)
il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 322 # total number of accesses dl2.hits 52 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.8385 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 i l2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb:dtlb none ./benc hmarks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 il2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb :dtlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:54 2013, options follow:
sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:f # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:f # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 sim_num_refs 1904 sim_elapsed_time 1 sim_inst_rate 5015.0000 il1.accesses 5015 il1.hits 4584 il1.misses 431 il1.replacements 27 il1.writebacks 0 il1.invalidations 0 il1.miss_rate 0.0859 il1.repl_rate 0.0054 il1.wb_rate 0.0000 il1.inv_rate 0.0000 il2.accesses 431 il2.hits 1 il2.misses 430 il2.replacements 0 il2.writebacks 0 il2.invalidations 0 il2.miss_rate 0.9977 il2.repl_rate 0.0000 il2.wb_rate 0.0000 il2.inv_rate 0.0000 dl1.accesses 2022 dl1.hits 1736 dl1.misses 286 dl1.replacements 52 dl1.writebacks 36 dl1.invalidations 0 dl1.miss_rate 0.1414 dl1.repl_rate 0.0257 dl1.wb_rate 0.0178 dl1.inv_rate 0.0000 dl2.accesses 322 dl2.hits 52 dl2.misses 270 dl2.replacements 0 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 0.8385 dl2.repl_rate 0.0000 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 106496 ld_data_base 0x0140000000 ld_data_size 71264 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x01200059c0 ld_environ_base 0x011ff97000 ld_target_big_endian 0 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs
# program stack segment base (highest addres # # # # program initial stack size program entry point (initial PC) program environment base address address target executable endian-ness, non-zero if
big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 i l2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb:dtlb none ./benc hmarks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 il2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb :dtlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:54 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:r # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:r # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 431 # total number of accesses il2.hits 1 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9977 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks
dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 322 # total number of accesses dl2.hits 52 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.8385 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 i l2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:dtlb none ./benchm arks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 il2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:d tlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:54 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # load configuration from a file # dump configuration to a file
# -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)
# # # # # # # #
print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:l # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:l # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds
sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 431 # total number of accesses il2.hits 1 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9977 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 322 # total number of accesses dl2.hits 52 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.8385 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 i
l2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:dtlb none ./benchm arks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 il2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:d tlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:54 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:f # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:f # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> name of the cache being defined number of sets in the cache block size of the cache associativity of the cache
<repl> Examples:
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 431 # total number of accesses il2.hits 1 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9977 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 322 # total number of accesses dl2.hits 52 # total number of hits dl2.misses 270 # total number of misses
dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.8385 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 i l2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:dtlb none ./benchm arks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 il2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:d tlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:54 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:r # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:r # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref)
il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 431 # total number of accesses il2.hits 1 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9977 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 322 # total number of accesses dl2.hits 52 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.8385 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial
entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:54 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g.,
A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 sim_num_refs 1904 sim_elapsed_time 1 sim_inst_rate 5015.0000 il1.accesses 5015 il1.hits 4584 il1.misses 431 il1.replacements 27 il1.writebacks 0 il1.invalidations 0 il1.miss_rate 0.0859 il1.repl_rate 0.0054 il1.wb_rate 0.0000 il1.inv_rate 0.0000 dl1.accesses 2022 dl1.hits 1736 dl1.misses 286 dl1.replacements 52 dl1.writebacks 36 dl1.invalidations 0 dl1.miss_rate 0.1414 dl1.repl_rate 0.0257 dl1.wb_rate 0.0178 dl1.inv_rate 0.0000 dl2.accesses 753 dl2.hits 53 dl2.misses 700 dl2.replacements 0 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 0.9296 dl2.repl_rate 0.0000 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 106496 ld_data_base 0x0140000000 ld_data_size 71264 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x01200059c0 ld_environ_base 0x011ff97000 ld_target_big_endian 0 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs
big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:54 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k)
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 753 # total number of accesses dl2.hits 53 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks
dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9296 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file
-nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref)
il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 753 # total number of accesses dl2.hits 53 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9296 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration,
which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 753 # total number of accesses dl2.hits 53 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9296 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary
sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ
dl2.hits 53 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 7 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9296 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0093 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 i l2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb:dtlb none ./benc hmarks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 il2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb :dtlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately
# -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)
<null> # restore EIO trace execution from <fname> <null> # redirect simulator output to file (non-interacti <null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:l # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:l # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 431 # total number of accesses il2.hits 1 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9977 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 322 # total number of accesses dl2.hits 52 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.8385 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 i l2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb:dtlb none ./benc hmarks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 il2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb :dtlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:f # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:f # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
Cache levels can be unified by pointing a level of the instruction cache
hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 431 # total number of accesses il2.hits 1 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9977 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 322 # total number of accesses dl2.hits 52 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.8385 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref)
dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 i l2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb:dtlb none ./benc hmarks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 il2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb :dtlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:r # l2 data cache config, i.e., {<config>|none}
-cache:il1 il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 il2:16384:32:1:r # l2 instruction cache config, i.e., {<config> |dl2|none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 431 # total number of accesses il2.hits 1 # total number of hits il2.misses 430 # total number of misses
il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9977 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 322 # total number of accesses dl2.hits 52 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.8385 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 i l2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:dtlb none ./benchm arks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 il2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:d
tlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:l # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:l # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1):
-cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 431 # total number of accesses il2.hits 1 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9977 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 322 # total number of accesses dl2.hits 52 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.8385 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack)
ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 i l2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:dtlb none ./benchm arks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 il2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:d tlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:f # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:f # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 431 # total number of accesses il2.hits 1 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9977 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses
dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 322 # total number of accesses dl2.hits 52 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.8385 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 i l2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:dtlb none ./benchm arks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 il2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:d tlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing
information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:r # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:r # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call...
sim: ** simulation statistics ** sim_num_insn 5015 sim_num_refs 1904 sim_elapsed_time 1 sim_inst_rate 5015.0000 il1.accesses 5015 il1.hits 4584 il1.misses 431 il1.replacements 27 il1.writebacks 0 il1.invalidations 0 il1.miss_rate 0.0859 il1.repl_rate 0.0054 il1.wb_rate 0.0000 il1.inv_rate 0.0000 il2.accesses 431 il2.hits 1 il2.misses 430 il2.replacements 0 il2.writebacks 0 il2.invalidations 0 il2.miss_rate 0.9977 il2.repl_rate 0.0000 il2.wb_rate 0.0000 il2.inv_rate 0.0000 dl1.accesses 2022 dl1.hits 1736 dl1.misses 286 dl1.replacements 52 dl1.writebacks 36 dl1.invalidations 0 dl1.miss_rate 0.1414 dl1.repl_rate 0.0257 dl1.wb_rate 0.0178 dl1.inv_rate 0.0000 dl2.accesses 322 dl2.hits 52 dl2.misses 270 dl2.replacements 0 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 0.8385 dl2.repl_rate 0.0000 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 106496 ld_data_base 0x0140000000 ld_data_size 71264 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x01200059c0 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian mem.page_count 19 mem.page_mem 152k mem.ptab_misses 31
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs
# total number of pages allocated # total size of memory pages allocated # total first level page table misses
mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl>
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 753 # total number of accesses dl2.hits 53 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9296 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref)
dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none}
-cache:il1 il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses
dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 753 # total number of accesses dl2.hits 53 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9296 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated.
# -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed
sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 753 # total number of accesses dl2.hits 53 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9296 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial
entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 sim_num_refs 1904 sim_elapsed_time 1 sim_inst_rate 5015.0000 il1.accesses 5015 il1.hits 4584 il1.misses 431 il1.replacements 27 il1.writebacks 0 il1.invalidations 0 il1.miss_rate 0.0859 il1.repl_rate 0.0054 il1.wb_rate 0.0000 il1.inv_rate 0.0000 dl1.accesses 2022 dl1.hits 1736 dl1.misses 286 dl1.replacements 52 dl1.writebacks 36 dl1.invalidations 0 dl1.miss_rate 0.1414 dl1.repl_rate 0.0257 dl1.wb_rate 0.0178 dl1.inv_rate 0.0000 dl2.accesses 753 dl2.hits 53 dl2.misses 700 dl2.replacements 0 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 0.9296 dl2.repl_rate 0.0000 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 106496 ld_data_base 0x0140000000 ld_data_size 71264 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x01200059c0 ld_environ_base 0x011ff97000 ld_target_big_endian 0 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs
big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k)
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4584 # total number of hits il1.misses 431 # total number of misses il1.replacements 27 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0859 # miss rate (i.e., misses/ref) il1.repl_rate 0.0054 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 753 # total number of accesses dl2.hits 53 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks
dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9296 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
-nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1736 # total number of hits dl1.misses 286 # total number of misses dl1.replacements 52 # total number of replacements dl1.writebacks 36 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1414 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0257 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0178 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 753 # total number of accesses dl2.hits 53 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 7 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9296 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0093 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 i l2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb:dtlb none ./benc hmarks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 il2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb :dtlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration,
which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:l # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:l # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 sim_num_refs 1904 sim_elapsed_time 1 sim_inst_rate 5015.0000 il1.accesses 5015 il1.hits 4585 il1.misses 430 il1.replacements 5 il1.writebacks 0 il1.invalidations 0 il1.miss_rate 0.0857 il1.repl_rate 0.0010 il1.wb_rate 0.0000 il1.inv_rate 0.0000 il2.accesses 430 il2.hits 0 il2.misses 430 il2.replacements 0 il2.writebacks 0 il2.invalidations 0 il2.miss_rate 1.0000 il2.repl_rate 0.0000 il2.wb_rate 0.0000 il2.inv_rate 0.0000 dl1.accesses 2022 dl1.hits 1752 dl1.misses 270 dl1.replacements 0 dl1.writebacks 0 dl1.invalidations 0 dl1.miss_rate 0.1335 dl1.repl_rate 0.0000 dl1.wb_rate 0.0000 dl1.inv_rate 0.0000 dl2.accesses 270 dl2.hits 0 dl2.misses 270 dl2.replacements 0 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 1.0000 dl2.repl_rate 0.0000 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 106496 ld_data_base 0x0140000000 ld_data_size 71264 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x01200059c0 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian mem.page_count 19 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs
# total number of pages allocated
mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 i l2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb:dtlb none ./benc hmarks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 il2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb :dtlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:f # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:f # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
The cache config parameter <config> has the following format:
<name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4585 # total number of hits il1.misses 430 # total number of misses il1.replacements 5 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0857 # miss rate (i.e., misses/ref) il1.repl_rate 0.0010 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 430 # total number of accesses il2.hits 0 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 1.0000 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1752 # total number of hits dl1.misses 270 # total number of misses dl1.replacements 0 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1335 # miss rate (i.e., misses/ref)
dl1.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 270 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 i l2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb:dtlb none ./benc hmarks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 il2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb :dtlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # # # # -config -dumpconfig -h -v # # false # false # load configuration from a file dump configuration to a file print help message verbose operation
# -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)
false false 1 false <null> <null>
# # # # # #
enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:r # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:r # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses
il1.hits 4585 # total number of hits il1.misses 430 # total number of misses il1.replacements 5 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0857 # miss rate (i.e., misses/ref) il1.repl_rate 0.0010 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 430 # total number of accesses il2.hits 0 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 1.0000 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1752 # total number of hits dl1.misses 270 # total number of misses dl1.replacements 0 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1335 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 270 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 i l2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:dtlb none ./benchm arks/anagram.alpha -O ./benchmarks/1stmt.i>>
Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 il2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:d tlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:l # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:l # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random
Examples:
-cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4585 # total number of hits il1.misses 430 # total number of misses il1.replacements 5 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0857 # miss rate (i.e., misses/ref) il1.repl_rate 0.0010 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 430 # total number of accesses il2.hits 0 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 1.0000 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1752 # total number of hits dl1.misses 270 # total number of misses dl1.replacements 0 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1335 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 270 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks
dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 i l2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:dtlb none ./benchm arks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 il2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:d tlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
-nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)
0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:f # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:f # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 430 # total number of accesses il2.hits 0 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 1.0000 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1752 # total number of hits dl1.misses 270 # total number of misses dl1.replacements 0 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1335 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 270 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 i l2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:dtlb none ./benchm arks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com).
warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 il2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:d tlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:r # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:r # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2):
-cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4585 # total number of hits il1.misses 430 # total number of misses il1.replacements 5 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0857 # miss rate (i.e., misses/ref) il1.repl_rate 0.0010 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 430 # total number of accesses il2.hits 0 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 1.0000 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1752 # total number of hits dl1.misses 270 # total number of misses dl1.replacements 0 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1335 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 270 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base
ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |none} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 dl2 # l2 instruction cache config, i.e., {<config>|dl2
# # # #
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4585 # total number of hits il1.misses 430 # total number of misses il1.replacements 5 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0857 # miss rate (i.e., misses/ref) il1.repl_rate 0.0010 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1752 # total number of hits dl1.misses 270 # total number of misses dl1.replacements 0 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1335 # miss rate (i.e., misses/ref)
dl1.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # # # # -config -dumpconfig -h -v # # false # false # load configuration from a file dump configuration to a file print help message verbose operation
# -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
il1.hits 4585 # total number of hits il1.misses 430 # total number of misses il1.replacements 5 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0857 # miss rate (i.e., misses/ref) il1.repl_rate 0.0010 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1752 # total number of hits dl1.misses 270 # total number of misses dl1.replacements 0 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1335 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored...
sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 sim_num_refs 1904 sim_elapsed_time 1 sim_inst_rate 5015.0000 il1.accesses 5015 il1.hits 4585 il1.misses 430 il1.replacements 5 il1.writebacks 0 il1.invalidations 0 il1.miss_rate 0.0857 il1.repl_rate 0.0010 il1.wb_rate 0.0000 il1.inv_rate 0.0000 dl1.accesses 2022 dl1.hits 1752 dl1.misses 270 dl1.replacements 0 dl1.writebacks 0 dl1.invalidations 0 dl1.miss_rate 0.1335 dl1.repl_rate 0.0000 dl1.wb_rate 0.0000 dl1.inv_rate 0.0000 dl2.accesses 700 dl2.hits 0 dl2.misses 700 dl2.replacements 0 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 1.0000 dl2.repl_rate 0.0000 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 106496 ld_data_base 0x0140000000 ld_data_size 71264 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x01200059c0 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian mem.page_count 19 mem.page_mem 152k mem.ptab_misses 31 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs
mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl>
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4585 # total number of hits il1.misses 430 # total number of misses il1.replacements 5 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0857 # miss rate (i.e., misses/ref) il1.repl_rate 0.0010 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1752 # total number of hits dl1.misses 270 # total number of misses dl1.replacements 0 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1335 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref)
dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none}
-cache:il1 il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4585 # total number of hits il1.misses 430 # total number of misses il1.replacements 5 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0857 # miss rate (i.e., misses/ref) il1.repl_rate 0.0010 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1752 # total number of hits dl1.misses 270 # total number of misses
dl1.replacements 0 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1335 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated.
# -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4585 # total number of hits il1.misses 430 # total number of misses il1.replacements 5 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0857 # miss rate (i.e., misses/ref) il1.repl_rate 0.0010 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1752 # total number of hits dl1.misses 270 # total number of misses dl1.replacements 0 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1335 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 7 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0100 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 i l2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb:dtlb none ./benc hmarks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial
entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 il2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb :dtlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:l # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:l # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4585 # total number of hits il1.misses 430 # total number of misses il1.replacements 5 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0857 # miss rate (i.e., misses/ref) il1.repl_rate 0.0010 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 430 # total number of accesses il2.hits 0 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 1.0000 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1752 # total number of hits dl1.misses 270 # total number of misses dl1.replacements 0 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1335 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 270 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base
ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 i l2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb:dtlb none ./benc hmarks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 il2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb :dtlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:f # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2
-cache:il2 il2:16384:32:1:f # l2 instruction cache config, i.e., {<config> |dl2|none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4585 # total number of hits il1.misses 430 # total number of misses il1.replacements 5 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0857 # miss rate (i.e., misses/ref) il1.repl_rate 0.0010 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 430 # total number of accesses il2.hits 0 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks
il2.invalidations 0 # total number of invalidations il2.miss_rate 1.0000 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1752 # total number of hits dl1.misses 270 # total number of misses dl1.replacements 0 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1335 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 270 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 i l2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb:dtlb none ./benc hmarks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 il2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb :dtlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i
sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:r # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:r # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4585 # total number of hits il1.misses 430 # total number of misses il1.replacements 5 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0857 # miss rate (i.e., misses/ref) il1.repl_rate 0.0010 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 430 # total number of accesses il2.hits 0 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 1.0000 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1752 # total number of hits dl1.misses 270 # total number of misses dl1.replacements 0 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1335 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 270 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC)
ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 i l2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:dtlb none ./benchm arks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 il2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:d tlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:l # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:l # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4585 # total number of hits il1.misses 430 # total number of misses il1.replacements 5 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0857 # miss rate (i.e., misses/ref) il1.repl_rate 0.0010 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 430 # total number of accesses il2.hits 0 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 1.0000 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1752 # total number of hits dl1.misses 270 # total number of misses
dl1.replacements 0 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1335 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 270 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 i l2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:dtlb none ./benchm arks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 il2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:d tlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated.
# -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)
# # # # # # # # # #
load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:f # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:f # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim_num_refs sim_elapsed_time sim_inst_rate il1.accesses il1.hits il1.misses il1.replacements il1.writebacks il1.invalidations il1.miss_rate il1.repl_rate il1.wb_rate il1.inv_rate il2.accesses il2.hits il2.misses il2.replacements il2.writebacks il2.invalidations il2.miss_rate il2.repl_rate il2.wb_rate il2.inv_rate dl1.accesses dl1.hits dl1.misses dl1.replacements dl1.writebacks dl1.invalidations dl1.miss_rate dl1.repl_rate dl1.wb_rate dl1.inv_rate dl2.accesses dl2.hits dl2.misses dl2.replacements dl2.writebacks dl2.invalidations dl2.miss_rate dl2.repl_rate dl2.wb_rate dl2.inv_rate ld_text_base ld_text_size ld_data_base ld_data_size s' size in bytes ld_stack_base s in stack) ld_stack_size ld_prog_entry ld_environ_base ld_target_big_endian big endian mem.page_count mem.page_mem mem.ptab_misses mem.ptab_accesses mem.ptab_miss_rate
1904 1 5015.0000 5015 4585 430 5 0 0 0.0857 0.0010 0.0000 0.0000 430 0 430 0 0 0 1.0000 0.0000 0.0000 0.0000 2022 1752 270 0 0 0 0.1335 0.0000 0.0000 0.0000 270 0 270 0 0 0 1.0000 0.0000 0.0000 0.0000 0x0120000000 106496 0x0140000000 71264
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs
0x011ff9b000 # program stack segment base (highest addres 16384 0x01200059c0 0x011ff97000 0 19 152k 31 239570 0.0001 # # # # # # # # # program initial stack size program entry point (initial PC) program environment base address address target executable endian-ness, non-zero if total total total total first number of pages allocated size of memory pages allocated first level page table misses page table accesses level page table miss rate
>>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 i l2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:dtlb none ./benchm arks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 il2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:d tlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:r # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:r # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> - name of the cache being defined <nsets> - number of sets in the cache
<bsize> - block size of the cache <assoc> - associativity of the cache <repl> - block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random Examples: -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4585 # total number of hits il1.misses 430 # total number of misses il1.replacements 5 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0857 # miss rate (i.e., misses/ref) il1.repl_rate 0.0010 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 430 # total number of accesses il2.hits 0 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 1.0000 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1752 # total number of hits dl1.misses 270 # total number of misses dl1.replacements 0 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1335 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 270 # total number of accesses
dl2.hits 0 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately
# -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0857 # miss rate (i.e., misses/ref) il1.repl_rate 0.0010 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1752 # total number of hits dl1.misses 270 # total number of misses dl1.replacements 0 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1335 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i
sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4585 # total number of hits il1.misses 430 # total number of misses il1.replacements 5 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0857 # miss rate (i.e., misses/ref) il1.repl_rate 0.0010 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1752 # total number of hits dl1.misses 270 # total number of misses dl1.replacements 0 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1335 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 d
l2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> name of the cache being defined number of sets in the cache block size of the cache associativity of the cache
<repl> Examples:
ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |none} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 dl2 # l2 instruction cache config, i.e., {<config>|dl2
# # # #
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4585 # total number of hits il1.misses 430 # total number of misses il1.replacements 5 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0857 # miss rate (i.e., misses/ref) il1.repl_rate 0.0010 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1752 # total number of hits dl1.misses 270 # total number of misses dl1.replacements 0 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1335 # miss rate (i.e., misses/ref)
dl1.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # # # # -config -dumpconfig -h -v # # false # false # load configuration from a file dump configuration to a file print help message verbose operation
# -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
il1.hits 4585 # total number of hits il1.misses 430 # total number of misses il1.replacements 5 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0857 # miss rate (i.e., misses/ref) il1.repl_rate 0.0010 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1752 # total number of hits dl1.misses 270 # total number of misses dl1.replacements 0 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1335 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored...
sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 sim_num_refs 1904 sim_elapsed_time 1 sim_inst_rate 5015.0000 il1.accesses 5015 il1.hits 4585 il1.misses 430 il1.replacements 5 il1.writebacks 0 il1.invalidations 0 il1.miss_rate 0.0857 il1.repl_rate 0.0010 il1.wb_rate 0.0000 il1.inv_rate 0.0000 dl1.accesses 2022 dl1.hits 1752 dl1.misses 270 dl1.replacements 0 dl1.writebacks 0 dl1.invalidations 0 dl1.miss_rate 0.1335 dl1.repl_rate 0.0000 dl1.wb_rate 0.0000 dl1.inv_rate 0.0000 dl2.accesses 700 dl2.hits 0 dl2.misses 700 dl2.replacements 7 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 1.0000 dl2.repl_rate 0.0100 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 106496 ld_data_base 0x0140000000 ld_data_size 71264 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x01200059c0 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian mem.page_count 19 mem.page_mem 152k mem.ptab_misses 31 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs
mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 i l2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb:dtlb none ./benc hmarks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 il2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb :dtlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:l # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:l # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl>
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4579 # total number of hits il1.misses 436 # total number of misses il1.replacements 36 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0869 # miss rate (i.e., misses/ref) il1.repl_rate 0.0072 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 436 # total number of accesses il2.hits 6 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9862 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1746 # total number of hits dl1.misses 276 # total number of misses dl1.replacements 24 # total number of replacements dl1.writebacks 18 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1365 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0119 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0089 # writeback rate (i.e., wrbks/ref)
dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 294 # total number of accesses dl2.hits 24 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9184 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 i l2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb:dtlb none ./benc hmarks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 il2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb :dtlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # # # # # # -config -dumpconfig -h -v -d -i # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger
false false false false
-seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)
1 false <null> <null>
# # # #
random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:f # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:f # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4579 # total number of hits il1.misses 436 # total number of misses
il1.replacements 36 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0869 # miss rate (i.e., misses/ref) il1.repl_rate 0.0072 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 436 # total number of accesses il2.hits 6 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9862 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1746 # total number of hits dl1.misses 276 # total number of misses dl1.replacements 24 # total number of replacements dl1.writebacks 18 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1365 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0119 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0089 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 294 # total number of accesses dl2.hits 24 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9184 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 i l2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb:dtlb none ./benc hmarks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary
sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 il2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb :dtlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:r # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:r # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4580 # total number of hits il1.misses 435 # total number of misses il1.replacements 32 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0867 # miss rate (i.e., misses/ref) il1.repl_rate 0.0064 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 435 # total number of accesses il2.hits 5 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9885 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1745 # total number of hits dl1.misses 277 # total number of misses dl1.replacements 21 # total number of replacements dl1.writebacks 16 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1370 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0104 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0079 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 293 # total number of accesses dl2.hits 23 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9215 # miss rate (i.e., misses/ref)
dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 i l2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:dtlb none ./benchm arks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 il2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:d tlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
-cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)
dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:l # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:l # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4579 # total number of hits il1.misses 436 # total number of misses il1.replacements 36 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0869 # miss rate (i.e., misses/ref) il1.repl_rate 0.0072 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 436 # total number of accesses
il2.hits 6 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9862 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1746 # total number of hits dl1.misses 276 # total number of misses dl1.replacements 24 # total number of replacements dl1.writebacks 18 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1365 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0119 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0089 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 294 # total number of accesses dl2.hits 24 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9184 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 i l2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:dtlb none ./benchm arks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored...
sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 il2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:d tlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:f # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:f # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4579 # total number of hits il1.misses 436 # total number of misses il1.replacements 36 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0869 # miss rate (i.e., misses/ref) il1.repl_rate 0.0072 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 436 # total number of accesses il2.hits 6 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9862 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1746 # total number of hits dl1.misses 276 # total number of misses dl1.replacements 24 # total number of replacements dl1.writebacks 18 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1365 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0119 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0089 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 294 # total number of accesses dl2.hits 24 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9184 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes
ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 i l2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:dtlb none ./benchm arks/anagram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 il2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:d tlb none ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:r # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:r # l2 instruction cache config, i.e., {<config>| none # instruction TLB config, i.e., {<config>|none} none # data TLB config, i.e., {<config>|none}
-flush -cache:icompress ivalents # -pcstat k)
false # flush caches on system calls false # convert 64-bit inst addresses to 32-bit inst equ <null> # profile stat(s) against text addr's (mult uses o
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4580 # total number of hits il1.misses 435 # total number of misses il1.replacements 32 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0867 # miss rate (i.e., misses/ref) il1.repl_rate 0.0064 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 435 # total number of accesses il2.hits 5 # total number of hits il2.misses 430 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9885 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref)
il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1745 # total number of hits dl1.misses 277 # total number of misses dl1.replacements 21 # total number of replacements dl1.writebacks 16 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1370 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0104 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0079 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 293 # total number of accesses dl2.hits 23 # total number of hits dl2.misses 270 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9215 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration,
which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4579 # total number of hits il1.misses 436 # total number of misses il1.replacements 36 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0869 # miss rate (i.e., misses/ref) il1.repl_rate 0.0072 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1746 # total number of hits dl1.misses 276 # total number of misses dl1.replacements 24 # total number of replacements dl1.writebacks 18 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1365 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0119 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0089 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 730 # total number of accesses dl2.hits 30 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9589 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary
sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ
dl2.hits 28 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9615 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately
# -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0869 # miss rate (i.e., misses/ref) il1.repl_rate 0.0072 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1746 # total number of hits dl1.misses 276 # total number of misses dl1.replacements 24 # total number of replacements dl1.writebacks 18 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1365 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0119 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0089 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 730 # total number of accesses dl2.hits 30 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9589 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i
sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) il1.accesses 5015 # total number of accesses il1.hits 4579 # total number of hits il1.misses 436 # total number of misses il1.replacements 36 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0869 # miss rate (i.e., misses/ref) il1.repl_rate 0.0072 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 2022 # total number of accesses dl1.hits 1746 # total number of hits dl1.misses 276 # total number of misses dl1.replacements 24 # total number of replacements dl1.writebacks 18 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1365 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0119 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0089 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 730 # total number of accesses dl2.hits 30 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9589 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 d
l2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./benchmarks/anagra m.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> name of the cache being defined number of sets in the cache block size of the cache associativity of the cache
<repl> Examples:
ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 ne} -cache:il2 |none} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:4096:32:1:l # l1 data cache config, i.e., {<config>|none} dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no none # l2 instruction cache config, i.e., {<config>|dl2
# # # #
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) dl1.accesses 7037 # total number of accesses dl1.hits 6337 # total number of hits dl1.misses 700 # total number of misses dl1.replacements 10 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0995 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0014 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref)
dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
-cache:dl1 dl1:4096:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) dl1.accesses 7037 # total number of accesses dl1.hits 6337 # total number of hits dl1.misses 700 # total number of misses dl1.replacements 10 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0995 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0014 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses
dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately
# -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) dl1.accesses 7037 # total number of accesses dl1.hits 6337 # total number of hits dl1.misses 700 # total number of misses dl1.replacements 10 # total number of replacements dl1.writebacks 0 # total number of writebacks
dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0995 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0014 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # load configuration from a file # dump configuration to a file
# -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim_inst_rate 5015.0000 # simulation speed (in insts/sec) dl1.accesses 7037 # total number of accesses dl1.hits 6337 # total number of hits dl1.misses 700 # total number of misses dl1.replacements 10 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0995 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0014 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration,
which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) dl1.accesses 7037 # total number of accesses dl1.hits 6337 # total number of hits dl1.misses 700 # total number of misses dl1.replacements 10 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0995 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0014 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb non
e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) dl1.accesses 7037 # total number of accesses dl1.hits 6337 # total number of hits dl1.misses 700 # total number of misses dl1.replacements 10 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0995 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0014 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 7 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0100 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial
entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) dl1.accesses 7037 # total number of accesses dl1.hits 6337 # total number of hits dl1.misses 700 # total number of misses dl1.replacements 10 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0995 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0014 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>>
Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random
Examples:
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 sim_num_refs 1904 sim_elapsed_time 1 sim_inst_rate 5015.0000 dl1.accesses 7037 dl1.hits 6337 dl1.misses 700 dl1.replacements 10 dl1.writebacks 0 dl1.invalidations 0 dl1.miss_rate 0.0995 dl1.repl_rate 0.0014 dl1.wb_rate 0.0000 dl1.inv_rate 0.0000 dl2.accesses 700 dl2.hits 0 dl2.misses 700 dl2.replacements 0 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 1.0000 dl2.repl_rate 0.0000 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 106496 ld_data_base 0x0140000000 ld_data_size 71264 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x01200059c0 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian mem.page_count 19 mem.page_mem 152k mem.ptab_misses 31 # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs
mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl>
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) dl1.accesses 7037 # total number of accesses dl1.hits 6337 # total number of hits dl1.misses 700 # total number of misses dl1.replacements 10 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0995 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0014 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC)
ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) dl1.accesses 7037 # total number of accesses dl1.hits 6337 # total number of hits dl1.misses 700 # total number of misses dl1.replacements 10 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0995 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0014 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base
ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 ne} -cache:il2 |none} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:4096:32:1:f # l1 data cache config, i.e., {<config>|none} dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no none # l2 instruction cache config, i.e., {<config>|dl2
# # # #
dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
-cache:dl1 dl1:4096:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 7 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0100 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately
# -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0995 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0014 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # load configuration from a file # dump configuration to a file
# -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim_inst_rate 5015.0000 # simulation speed (in insts/sec) dl1.accesses 7037 # total number of accesses dl1.hits 6337 # total number of hits dl1.misses 700 # total number of misses dl1.replacements 10 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0995 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0014 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration,
which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) dl1.accesses 7037 # total number of accesses dl1.hits 6337 # total number of hits dl1.misses 700 # total number of misses dl1.replacements 10 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0995 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0014 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb non
e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) dl1.accesses 7037 # total number of accesses dl1.hits 6337 # total number of hits dl1.misses 700 # total number of misses dl1.replacements 10 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0995 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0014 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial
entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) dl1.accesses 7037 # total number of accesses dl1.hits 6337 # total number of hits dl1.misses 700 # total number of misses dl1.replacements 10 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0995 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0014 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>>
Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random
Examples:
mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl>
ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o
ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:55 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 ne} -cache:il2 |none} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no none # l2 instruction cache config, i.e., {<config>|dl2
# # # #
dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:56 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
-cache:dl1 dl1:2048:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:56 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately
# -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0995 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0010 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:56 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # load configuration from a file # dump configuration to a file
# -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim_inst_rate 5015.0000 # simulation speed (in insts/sec) dl1.accesses 7037 # total number of accesses dl1.hits 6337 # total number of hits dl1.misses 700 # total number of misses dl1.replacements 7 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0995 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0010 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 7 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0100 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:56 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration,
which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) dl1.accesses 7037 # total number of accesses dl1.hits 6337 # total number of hits dl1.misses 700 # total number of misses dl1.replacements 7 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0995 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0010 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb non
e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:56 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) dl1.accesses 7037 # total number of accesses dl1.hits 6337 # total number of hits dl1.misses 700 # total number of misses dl1.replacements 7 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0995 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0010 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial
entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:56 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) dl1.accesses 7037 # total number of accesses dl1.hits 6337 # total number of hits dl1.misses 700 # total number of misses dl1.replacements 7 # total number of replacements dl1.writebacks 0 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0995 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0010 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 700 # total number of accesses dl2.hits 0 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 1.0000 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>>
Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:56 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random
Examples:
mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:56 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl>
ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:56 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o
ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:56 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 ne} -cache:il2 |none} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:2:r # l1 data cache config, i.e., {<config>|none} dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no none # l2 instruction cache config, i.e., {<config>|dl2
# # # #
dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:56 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
-cache:dl1 dl1:2048:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
dl2.hits 27 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9629 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:56 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately
# -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1006 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0064 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0023 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 724 # total number of accesses dl2.hits 24 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9669 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:56 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # load configuration from a file # dump configuration to a file
# -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim_inst_rate 5015.0000 # simulation speed (in insts/sec) dl1.accesses 7037 # total number of accesses dl1.hits 6328 # total number of hits dl1.misses 709 # total number of misses dl1.replacements 54 # total number of replacements dl1.writebacks 18 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1008 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0077 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0026 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 727 # total number of accesses dl2.hits 27 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9629 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:56 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration,
which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 # total number of instructions executed sim_num_refs 1904 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 5015.0000 # simulation speed (in insts/sec) dl1.accesses 7037 # total number of accesses dl1.hits 6328 # total number of hits dl1.misses 709 # total number of misses dl1.replacements 54 # total number of replacements dl1.writebacks 18 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.1008 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0077 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0026 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 727 # total number of accesses dl2.hits 27 # total number of hits dl2.misses 700 # total number of misses dl2.replacements 0 # total number of replacements dl2.writebacks 0 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.9629 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 106496 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 71264 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x01200059c0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 19 # total number of pages allocated mem.page_mem 152k # total size of memory pages allocated mem.ptab_misses 31 # total first level page table misses mem.ptab_accesses 239570 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/an agram.alpha -O ./benchmarks/1stmt.i>> Error is: <<<Cannot stat dictionary sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb non
e ./benchmarks/anagram.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 10:48:56 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 5015 sim_num_refs 1904 sim_elapsed_time 1 sim_inst_rate 5015.0000 dl1.accesses 7037 dl1.hits 6329 dl1.misses 708 dl1.replacements 45 dl1.writebacks 16 dl1.invalidations 0 dl1.miss_rate 0.1006 dl1.repl_rate 0.0064 dl1.wb_rate 0.0023 dl1.inv_rate 0.0000 dl2.accesses 724 dl2.hits 24 dl2.misses 700 dl2.replacements 6 dl2.writebacks 0 dl2.invalidations 0 dl2.miss_rate 0.9669 dl2.repl_rate 0.0083 dl2.wb_rate 0.0000 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 106496 ld_data_base 0x0140000000 ld_data_size 71264 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x01200059c0 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian mem.page_count 19 mem.page_mem 152k mem.ptab_misses 31 mem.ptab_accesses 239570 mem.ptab_miss_rate 0.0001 >>> exit Script done on Tue 05 Mar 2013 10:49:02 AM CST # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs
# program stack segment base (highest addres # # # # # # # # # program initial stack size program entry point (initial PC) program environment base address address target executable endian-ness, non-zero if total total total total first number of pages allocated size of memory pages allocated first level page table misses page table accesses level page table miss rate

Anagram

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Anagram

Uploaded by

Copyright:

Available Formats

Script started on Tue 05 Mar 2013 10:48:39 AM CST [root@localhost 32]# cd /simplesim-3.0/ mysim_anagram.exp <<.

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

<name> <nsets> <bsize> <assoc> <repl> Examples:

false false false false

1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

-flush -cache:icompress ivalents # -pcstat k)

sim: ** starting functional simulation w/ caches **

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false

false false false false 1 false <null> <null>

-tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)

none none false false

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file

sim: ** starting functional simulation w/ caches **

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

Cache levels can be unified by pointing a level of the instruction cache

false false false false 1 false <null> <null>

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

-cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

<name> <nsets> <bsize> <assoc> <repl> Examples:

false false false false 1 false <null> <null>

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

sim: ** starting functional simulation w/ caches **

# total number of pages allocated

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format:

false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

sim: starting functional simulation w/ caches

sim: starting functional simulation w/ caches

sim: starting functional simulation w/ caches

sim: starting functional simulation w/ caches

sim: starting functional simulation w/ caches

sim: starting functional simulation w/ caches