4FM Get Started Guide

4FM GETTING STARTED GUIDE
V4.2
4FM
Getting Started Guide Microsoft Windows
4DSP LLC Email: support@4dsp.com This document is the property of 4DSP LLC and may not be copied nor communicated to a third party without the written permission of 4DSP LLC. 4DSP Inc. 2006-2012
V4.2
Table of Contents
1 2 Introduction ......................................................................................................................... 5 Requirements and handling instructions ............................................................................... 6 2.1 2.2 2.3 2.4 2.5 3 4 Hardware requirements and handling instructions ................................................................ 6 Software requirements ........................................................................................................... 6 Software requirements (Visual Studio 2008 SP1) ................................................................... 7 Software requirements (Modelsim Xilinx Simulation Library) ............................................. 8 Software requirements (Modelsim Various Configuration) ................................................. 9
Software Installation .......................................................................................................... 10 Development kit components description ........................................................................... 11 4.1 Software Overview ................................................................................................................ 11 PCI/PCI Express installation ........................................................................................... 11 Ethernet installation ...................................................................................................... 12 4.1.1 4.1.2 4.2 4.4 4.5 4.6 4.7 4.8
StellarIP overview .................................................................................................................. 13 Firmware overview ................................................................................................................ 15 Documentation...................................................................................................................... 16 4FM Firmware (Design Files) ................................................................................................. 16 4FM Firmware (Recovery Files) ............................................................................................. 16 4DSP Drivers .......................................................................................................................... 17 4FM PCI/PCI(e) driver .................................................................................................... 17 4DSPNET NDIS Protocol driver ...................................................................................... 17 4FM (PCI API) ................................................................................................................. 18 ETHAPI API (Ethernet API) ............................................................................................. 18 4FM Diagnostics/Information plug-in (PCI/PCIe hardware) ......................................... 20 4FM Registers/Update plug-in (PCI/PCIe hardware) .................................................... 22 4FM Memory Test plug-ins (PCI/PCIe hardware) ......................................................... 24 4FM Firmware Installer Plug-in .................................................................................... 25
4.8.1 4.8.2 4.9 4.9.1 4.9.2 4.10 4.10.1 4.10.2 4.10.3 4.10.4 5 5.1
4DSP APIs ............................................................................................................................... 18
4FM GUI Control application ................................................................................................ 19
StellarIP ............................................................................................................................. 26 Firmware project creation..................................................................................................... 26 StellarIP plug-in configuration ....................................................................................... 27 Launch StellarIP ............................................................................................................. 27 Examine StellarIP results ............................................................................................... 28 5.1.1 5.1.2 5.1.3
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5.2 5.3 5.4 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8
Simulating StellarIP results .................................................................................................... 29 Modifying simulation behaviour ........................................................................................... 30 Open and compile the project in Xilinx ISE ........................................................................... 31 Preparation ............................................................................................................................ 33 Adding a custom star ............................................................................................................. 34 Configuring the custom star .................................................................................................. 35 Generate support code for the custom star ......................................................................... 36 Incorporating our new star into the definition file ............................................................... 37 Compile the new design ........................................................................................................ 38 Verifying our modifications ................................................................................................... 38 Uploading a firmware (PCI/PCIe hardware) ......................................................................... 38 Convert the .bit file into a .hex file (bit2hex) ................................................................ 38 Convert the .bit file into a .hex file (shell extension) .................................................... 38 Upload the firmware into hardware ............................................................................. 39
StellarIP Star Creation ........................................................................................................ 32
6.8.1 6.8.2 6.8.3 6.9 6.10 7 7.1 7.2 7.3 7.4 8 8.1 8.2 9 9.1
Test the firmware using StellarIPs Script Parser (PCI/PCIe hardware) ................................ 39 Test the firmware using training materials reference application ....................................... 41 Step 1 ..................................................................................................................................... 42 Step 2 ..................................................................................................................................... 44 Step 3 ..................................................................................................................................... 46 Step 4 ..................................................................................................................................... 46 Documentation...................................................................................................................... 49 Reference Firmware Matrix .................................................................................................. 49 Quick start ............................................................................................................................. 51 Prepare the host computer ........................................................................................... 52 Prepare and connect ML605 to the host computer ...................................................... 53 Programming ML605 FPGA device (Virtex 6 LX240T) ................................................... 53 Programming ML605 Flash device (Optional) ............................................................... 53 Verify FPGA firmware initialization ............................................................................... 54 Check which virtual COM (UART) port is featured by the device driver ....................... 55 Description of the FMC645 Test Peripheral Application ............................................... 56 Executing the FMC645 Test Peripheral Application ...................................................... 56
Training materials .............................................................................................................. 42
Evaluating FMC AD/DA product using Xilinx Development kits (ML605, SP601, SP605) ......... 47
Evaluating FMC DSP product using Xilinx Development kits (ML605) ................................... 51 9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 9.1.6 9.1.7 9.1.8
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9.1.9 10 10.1 10.2 10.3 10.4 11 11.1 11.2
Obtaining more information, technical support ........................................................... 56
Annex 1 Manual Firmware Installation ............................................................................. 58 Select a input firmware package file ..................................................................................... 59 Select an output folder .......................................................................................................... 60 Install the firmware ............................................................................................................... 61 In case of trouble ................................................................................................................... 62 Introduction........................................................................................................................... 63 License format ....................................................................................................................... 64 The NOTICE= field .......................................................................................................... 64 The HOSTID= field.......................................................................................................... 64 The EXPIRY= field ........................................................................................................... 64
Annex 2 License File details .............................................................................................. 63
11.2.1 11.2.2 11.2.3 12 12.1 12.2 13 13.1 13.2 14
Annex 3 - Compiling the 4FM Core Example ........................................................................ 65 SDK Integration in Visual Studio 2008 ................................................................................... 65 Compiling............................................................................................................................... 65 4FF content............................................................................................................................ 66 4FF content (Hierarchical view)............................................................................................. 67
Annex 4 - Firmware .4FF file ............................................................................................... 66
Annex 5 fmc645 test peripherals log................................................................................. 68
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1 Introduction
The 4FM Getting Started Guide describes the steps that a user must perform in order to use the 4FM V2.0 development kit. Windows 7 is required in order to install/use the development kit. The BSP is not tested by 4DSP under Windows 2000 and Windows XP anymore as most of our customers are already using Windows 7. The 4FM SDK is a set of tools and interfaces, and its main purpose is communicating with the various hardware manufactured by 4DSP. Additionally, Xilinx firmware projects can be created from the 4DSP firmware packages using the StellarIP software. The 4FM SDK also includes support for the FMC product line and a specific chapter is dedicated to its description
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2 Requirements and handling instructions

2.1 Hardware requirements and handling instructions
Please refer to the user manual shipped along with the hardware you have purchased and strictly follow the handling instructions. Faulty handling might yield into destroying the card and void the warranty. The most important is the temperatures. The devices should not be used at a temperature exceeding the device specifications.
2.2 Software requirements

StellarIP relies on Xilinx software tools to prepare and compile Xilinx projects. An operating Xilinx ISE design suite is required. Xilinx ISE tools need to be referenced by the PATH environment variable. Recent Xilinx ISE installers do not set this folder in the PATH environment variable anymore. Note : Typical path for ISE v13.1 is C:\Xilinx\13.1\ISE_DS\ISE\bin\nt. Modelsim is required in order to simulate projects created by StellarIP and compiled using Xilinx tools. Different simulators can be used to simulate the design, but the various Modelsim macros (compile.do) should be rewritten in consequence. Xilinx simulation libraries for Modelsim should be compiled using Xilinxs Simulation Library Compilation Wizard 4FM SDK requires Windows 7. 4FM API requires Visual Studio 2008 SP1 to be properly installed and configured. The documentation is provided as a set of PDF documents. There are no hardcopies of the documentation.
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2.3 Software requirements (Visual Studio 2008 SP1)

In order to compile an application using 4DSP APIs you have to integrate the API into Visual Studio. To do so, launch Visual Studio and select Tools (from the menu bar) then Options. Navigate to Projects and Solutions and then VC ++ Directories. You have to define a new folder in the Include files as well as in the Library Files by clicking the folder icon in the upper right corner of the dialog. The 4FM SDK Core installer installs these two folders at the following path (for a 32-bit system): Libraries : C:\Program Files\4DSP\ 4FM Core Development Kit\Libs Includes : C:\Program Files\4DSP\ 4FM Core Development Kit\Incs
Figure 1: Define a folder for "Include Files"
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2.4 Software requirements (Modelsim Xilinx Simulation Library)

A properly compiled Xilinx Simulation Library is required in order to properly simulate projects created by StellarIP. Compiling this library is straightforward. After a proper Xilinx ISE installation, a wizard to compile this library is available from the start menu.
Figure 2: Start the Xilinx's "Simulation Library Compilation Wizard"
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2.5 Software requirements (Modelsim Various Configuration)

In some cases the Compxlib fails to properly reference the simulation libraries. To make sure the Xilinx simulation libraries are properly referenced in Modelsim the global modelsim.ini found in the Modelsim folder must be altered. The following lines should be added under the [Library] node. Please note that the following paths contain {vise} and {vsim} and they should both be substituted with the actual software version you are using: UNISIM = C:\Xilinx\{ vise }\ISE_DS\ISE\vhdl\mti_se\{vsim}\nt\unisim UNIMACRO = C:\Xilinx\{ vise}\ISE_DS\ISE\vhdl\mti_se\{vsim}\nt\unimacro SIMPRIM = C:\Xilinx\{ vise}\ISE_DS\ISE\vhdl\mti_se\{vsim}\nt\simprim XILINXCORELIB = C:\Xilinx\{vise} \ISE_DS\ISE\vhdl\mti_se\{vsim}\nt\XilinxCoreLib SECUREIP = C:\Xilinx\{vise}\ISE_DS\ISE\vhdl\mti_se\{vsim}\nt\secureip CPLD = C:\Xilinx\{vise}\ISE_DS\ISE\vhdl\mti_se\{vsim}\nt\cpld Note : Modelsim.ini is a read-only file and attributes should be changed to be writable. Modelsim should be configured to supported ps ( pico seconds ) simulations. This is also defined in modelsim.ini. The simulator resolution should be set to Resolution = ps Select Runtime options from the Simulate menu and make sure to suppress warnings for both From Synopsys Packages and From IEEE Numeric Std Packages. The Default Radix should be set to Hexadecimal
Figure 3: Modelsim runtime options
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3 Software Installation
Insert the 4FM CD in a CD/DVD drive. Go to this drive via Windows explorer and double-click the setup.exe file and follow the on-screen setup instructions. You might have received the BSP electronically, in this case browse do your downloaded files.
Note: If the installation does not complete properly, make sure to right click the setup.exe and choose Start as Administrator. This might be required as the installer installs a driver and redistributables which require elevated administrator rights. You will be asked to browse for a license file during the installation. The license file should have been sent to you on the installation disk or separately in an email. It is not possible to continue without a license file. 4DSP device drivers for PCI (PMC/XMC) and Ethernet are digitally signed and can be installed and loaded on both 32 and 64 bit Windows 7 variants.
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4 Development kit components description

After a successful installation, a few components are available. These components are described below. A component is not always a different application but can be a plug-in. A plug-in is a software component that is executed by the GUI control application. The license file browsed during the installation phase dictates which components are installed
4.1 Software Overview

This section gives a hierarchical view of all the software components installed for both PCI and Ethernet based devices. 4.1.1 PCI/PCI Express installation
After installing the BSP with a license file for a PCI/PCI Express product the following components will be installed. PCI bus is available for most 4DSP hardware as well as the ML605 which is sold by Xilinx.
Firmware Upload PCB Diagnostics PCB Information Firmware Decryption
Reference Software (C/C++ Source Code)
4FM GUI Control Application
Memory Tests (DDR2, DDR3 and QDR2)
4FM Application Programming Interface (API)
4FM Device Driver
PCI(e) Bus (XMC/PMC/CompactPCI/OpenVPX)
Figure 4 : Components for a PCI/PCIe installation
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4.1.2
Ethernet installation
After installing the BSP with a license file for an Ethernet product the following components will be installed. The Ethernet interface is mainly used by Xilinx hardware as the ML605, the SP601 and the SP605. 4DSPs FC6301 CompactPCI hardware is also able to take advantage of the Ethernet interface.
Reference Software (C/C++ Source Code)
Firmware Decryption
4FM GUI Control Application ETHAPI Application Programming Interface (API)
4DSPNET NDIS Protocol Driver
1Gbps Ethernet
Figure 5 : Components for an Ethernet installation
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4.2 StellarIP overview

The staff at 4DSP has been using a tool called StellarIP internally for quite a while. StellarIP simplifies the design process by having well-structured, reusable firmware blocks. The advantages of StellarIP are: Helps creating well-structured FPGA designs (called constellation in StellarIP) Improve re-usability of firmware blocks (called star in StellarIP) Have a higher level of abstraction while creating a new constellation (FPGA design) Speedup the design cycle by automating recurring tasks: automated top-level VHDL file creation automated ISE project file creation automated Modelsim simulation script creation
While working with stellar IP it is important to remember the following terminology: Star Wormhole Constellation A functional block with a specific task. A connection between two stars. A wormhole comprises of one or more signals in either one or both directions. A collection of stars that forms the top level of a firmware design.
StellarIP does not speak HDL or C, but speaks SDL: the Stellar Description Language. Using a Stellar Definition File, a Wormhole Library, and a Star Library, StellarIP is able to create a project for both the command line and graphical Xilinx ISE tools. In other words, a Stellar Definition File defines a constellation, which is the top level of a firmware. A constellation is made of stars (functional blocks provided by 4DSP and/or created by the user). The stars are interconnected using wormholes. Wormholes are generic communication interfaces defined by 4DSP and/or the user. The StellarIP plug-in depicted in figure 8 takes the user input and calls the StellarIP tools. 4DSPs website describes a little more what StellarIP is and this information can be obtained on the page: FPGA Development Tool (Stellar IP) | 4DSP, LLC. For more detailed information, please refer to the StellarIP users manual. This BSP also includes a beta schematic design entry for StellarIP allowing the reader of creating a complete constellation graphically, connecting blocks between each other easily. The schematic design entry creates the Stellar Definition File which can be further processed by StellarIP tools.
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StellarIP is divided in three distinct tabs in the 4FM GUI Control Application. These tabs are illustrated below. The wormhole editor provides the user with a way of creating or modifying wormholes in the star library. The star editor provides the user with a way of creating or modifying stars in the star library The core StellarIP provides the user with a way of converting a StellarIP firmware into a Xilinx ISE project file.
Figure 6 : The core StellarIP
Figure 7 : The star editor
Figure 8 : The wormhole editor
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4.4 Firmware overview

4DSP are providing firmware source code as encrypted firmware package having a .4ff (4DSP Firmware File) extension. The firmware entitled by a license file will be automatically decrypted by the 4FM installer during the post installation phase. A standalone firmware file decryption utility is available within the 4FM GUI Control Application software. A decrypted folder is containing a constellation description, a star library including star documentation for every stars and a constellation documentation describing the constellation. The decrypted firmware is converted to a Xilinx ISE project file by the StellarIP software. As soon StellarIP software has converted the decrypted firmware into a Xilinx ISE project file, then the flow is a standard FPGA flow Xilinx users are used to. An overview of what StellarIP is can be found in the StellarIP overview chapter. And a detailed description of decrypted firmware architecture can be found in the Annex 4 - Firmware .4FF file
.4FF Firmware File .4FF File Decryption Utility
Constellation Description
Star Library Incl. Documentation Decrypted firmware
Constellation Documentation
Ethernet/PCIe hardware
Figure 9 : Firmware compilation chain
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4.5 Documentation
Various documentations such as User Guides are installed by the SDK installer. These documents can be found at the following paths: C:\Program Files\4dsp\4FM Core Development Kit\Documentation - 32 bit system. C:\Program Files (x86)\4dsp\4FM Core Development Kit\Documentation 64 bit system. Additionally, documentation for the FMC product line can be found at the following paths: C:\Program Files\4dsp\FMC Board Support Package\Documentation - 32 bit system. C:\Program Files (x86)\4dsp\ FMC Board Support Package\Documentation 64 bit system.
Note : firmware documentation is part of the firmware package, please refers to
4FM Firmware
and Annex 4 - Firmware .4FF file for more information about the firmware packages.
4.6 4FM Firmware (Design Files)

The firmware packages are automatically decrypted by the installer and extracted at the following paths: C:\Program Files\4dsp\Common\Firmware\Extracted - 32 bit system. C:\Program Files (x86)\4dsp\Common\Firmware\Extracted - 64 bit system. This folder contains one folder per firmware allowed by your license file. Each firmware subfolder includes documentation, StellarIP firmware and its associated test bench, and the recovery files. The recovery files are programming files ready to be uploaded to the hardware.
Note: if the firmware was not decrypted automatically by the installer, one can try extracting the
firmware manually. Please refer to Annex 1 Manual Firmware Installation for more information
4.7 4FM Firmware (Recovery Files)

The firmware recovery files are installed along with the other BSP components. This provides the user with firmware files ready to be uploaded to the hardware. These files are located under the following paths: C:\Program Files\4dsp\Common\Firmware\Recovery - 32 bit system. C:\Program Files (x86)\4dsp\Common\Firmware\Recovery - 64 bit system.
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4.8 4DSP Drivers

A driver is the main interface between the hardware and the software. This chapter gives a few information about both device drivers, the 4FM device driver and the 4DSPNET protocol driver. 4DSP drivers are digitally signed thus allowing these software component to be installed for both Windows 7 32 bit and Windows 7 64 bits. A digitally signed driver is mandatory in order to load a run flawlessly under 64 bit environments. 4.8.1 4FM PCI/PCI(e) driver
It is a well-optimized kernel mode driver. An API is available to communicate with the device driver from the user application space. The device driver is automatically installed by the SDK installer. The driver can be installed manually in the case you would need to transfer the driver to a target system. The driver files are located at the following paths (after a default installation): C:\Program Files\4dsp\4FM Core Development Kit\Driver - 32 bit system. C:\Program Files (x86)\4dsp\4FM Core Development Kit\Driver - 64 bit system. 4.8.2 4DSPNET NDIS Protocol driver
It is a driver implementing a minimalistic protocol over Ethernet. Minimalistic because there is no specific handshaking or data recovery implement as compared to TCP/IP for instance. The device driver is automatically installed by the SDK installer. The driver can be installed manually in the case you would need to transfer the driver to a target system. The driver files are located at the following paths (after a default installation): C:\Program Files\4dsp\FMC Board Support Package \Driver - 32 bit system. C:\Program Files (x86)\4dsp\ FMC Board Support Package\Driver - 64 bit system.
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4.9 4DSP APIs

Application programming interfaces (API) are provided by 4DSP to the customers. Their purpose is bringing board level control to the user application space. These application programming interfaces are compatible with Microsoft Visual Studio. 4DSP recommends and supports Microsoft Visual Studio 2008 SP1. Other Microsoft Visual Studio versions might be used but downloading and installing the Visual Studio 2008 SP1 redistributables package is a requirement. Such redistributables package can be downloaded freely on various Microsoft websites. 4.9.1 4FM (PCI API)
The API communicates with the hardware device through the 4FM device driver installed by the SDK. The API provides all the C functions one might want to call from his application. This API is meant to communicate with 4DSPs PCI or PCIe devices. The available functions allow obtaining diagnostics, reading/writing firmware registers and receiving/sending data using direct memory access (DMA) operations.
Note :
More information about the 4FM API can be found in the 4FM Programmers Guide PDF
document. Please consult this document for a detailed description. 4.9.2 ETHAPI API (Ethernet API)
The API communicates with the Windows NDIS layer and communicates with the NDIS Ethernet protocol driver. The protocol is minimalistic; no data recovery or integrity checks are implemented. The available functions allow reading/writing firmware registers and receiving/sending data through the Ethernet interface.
Note : More information about the ETHAPI API can be found in the doxyethapi CHM document.
Please consult this document for a detailed description.
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4.10 4FM GUI Control application

The 4FM GUI is a graphical user interface engine that displays plug-in components. It has a few general controls which are used to select a device. It also displays status of various plug-ins. Each plug-in is displayed as a tab in the GUI control application. The following pictures show the GUI control application having five plug-ins loaded.
Figure 10: Main graphical user input dialog
The first area contains the independent controls for the plug-ins. For instance, a user can choose which device (FM489, FM680, FC6301, VP680, ) to control. Additionally, one can send a reset command to the hardware device. Note that devices communicating over Ethernet as the ML605 cannot be controlled by this software. The second area shows all the plug-ins loaded by the graphical user interface. Figure 10 shows the 4FM GUI Control application with the StellarIP plug-in loaded and active. The third area is called the debug area and displays various debug messages sent by the plug-ins. Typically StellarIP displays crucial information on this area which can be very useful to diagnose malformed StellarIP descriptions.
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The fourth area has the status area and displays current graphical user interface status. Note the magnifying glass icon. Pressing this button opens an extended debug view which is useful for checking the debug logs. An extended debug view is available. The extended debug view can be opened using the magnifying glass button in the user interface. This window can be resized as desired and is actually a way to read important amount of text displayed in the Debug Area.
4.10.1 4FM Diagnostics/Information plug-in (PCI/PCIe hardware) The following image shows the diagnostics/information plug-in. This plug-in gives the user a quick overview of the hardware and software status. Below you will find a short description of the different status fields.
Figure 11: Diagnostics/Information plug-in view
Software information: Graphical User Interface engine version (4FM Control Version) Application Programming Interface version (4FM API Version) Device driver version (4FM Driver Version)
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Board information: FPGA A firmware revision (FPGA A Revision) is the firmware version currently loaded in FPGA A. FPGA A PCI revision is the version of the PCI interface module also in FPGA A. FPGA A firmware I.D. is an identification number in FPGA A firmware. FPGA B device type is the FPGA type for FPGA B. FPGA B revision is the version string for the firmware currently active in FPGA B. FPGA B firmware I.D. is an identification number in FPGA B firmware. CPLD revision is the CPLD firmwares version. Serial Number is the board serial number programmed by the factory before the board is shipped to a customer.
Board diagnostics: Voltage readings of the different power rails. FPGA A temperature and FPGA B temperature for 4DSP hardware with two FPGAs. FPGA temperatures graph.
Note: Devices communicating over Ethernet as the ML605 are not supported by this plug-in!
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4.10.2 4FM Registers/Update plug-in (PCI/PCIe hardware) This plug-in allows basic interaction with the hardware as well as loading new FPGA configurations to the onboard flash. For some boards it is possible to directly upload a new configuration to the FPGA B device.
Figure 12: Registers/Update plug-in view
Clock Tree Settings: This area allows displaying frequencies from the clock tree. Changing the Selection combo box control will make the plug-in display the current frequency for the selected clock. Additionally, the frequency synthesizer parameters can be changed in order to change the onboard clock synthesizer frequency. Timeout: This area allows modification of the default DMA timeout value. The value has to be entered in milliseconds. The Once Timeout sets a timeout value (in milliseconds) for the next operation only. Registers: Reading and writing Custom Registers (Only available on FM48x hardware series). Reading and writing the 32bit wide User ROM non-volatile value.
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Reading and writing Stellar IP registers. The text field on the left represent an address and the text field on the right side represent the actual value. A stellarIP register is 32bit wide and actually transfer value to a specific address in the firmware register space.
FPGA A/B Firmware Update: This area allows programming firmware into the 4DSP hardware, either to FPGA A or FPGA B. Browsing to a .hex (or .pof in case of Altera hardware) file and pressing the Load button are the only steps required to upload a firmware into the hardware. The Write Flash checkbox control tells the plug-in to program the selected firmware into the FLASH memory instead of only programming the FPGA. A power cycle is required after programming the flash in order to load the new configuration into the FPGA. Directly programming the FPGA (with the check box control left unchecked) does not require a power cycle. The new Firmware is ready after programming. This type of programming is volatile which means the uploaded firmware will not persist with a power cycle.
Note 1: Direct FPGA B (to FPGA device) update/upload is not supported by default on FM680
devices. Only FM680 board with a CPLD version 1.3 and above can be directly be updated from the software. FPGA B update/upload is not supported for VP680 and FC6301 devices.
Note 2: Devices communicating over Ethernet as the ML605 are not supported by this plug-in!
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4.10.3 4FM Memory Test plug-ins (PCI/PCIe hardware) There are several plug-ins to test the BLAST memory on our boards. Three plug-ins are available (DDR2, DDR3 and QDR2 tests) and the correct plug-in is loaded for a given hardware. If you have a board with both DDR2 and QDR2 BLASTs, then two plug-ins will be loaded in the graphical user interface. All three plug-ins have the same interface.
Figure 13: DDR2 memory test plug-in view
Test Settings: This area allows configuration of the operating frequency and the number of loops for the test. Typically the reference firmware allows the memory test to run with a base frequency of 130 MHz. DMA Transfer Speed: This area displays the direct memory access speed for the last test. Read (from hardware to host), write (from host to hardware) and average are displayed by the user interface. The verify check box control need to be unchecked in order to obtain DMA transfer speed information.
Note 1: DDR3 memory banks actually operate at twice the synthesizer frequency. Setting the clock
synthesizer to 200MHz in the DDR3 memory test plug-in causes the DDR3 to be clocked at 400MHz.
Note 2: Devices communicating over Ethernet as the ML605 are not supported by this plug-in!
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4.10.4
4FM Firmware Installer Plug-in
This plug-in does not require any hardware be attached to the computer. The firmware packages are shipped as an encrypted firmware file, and this plug-in allows retrieving firmware sources from one of the available firmware packs. It is normally not required to decrypt the firmware manually unless you have received a dedicated firmware package from 4DSP. The installer automatically decrypts and extracts the firmware you are entitled to during the installation process. Please refer to 4FM Firmware for more information about this. This plug-in comes with a firmware package where you can find all the general firmwares. A general firmware is a firmware part of the standard board support package. The firmwares are reference designs that allow access to the different peripherals attached to the FPGAs on the PCB. The database also includes the recovery files which are ready to be uploaded to the hardware. If you have received a demo license, you will not be able to obtain firmware sources. In this case you can only access the recovery files.
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5 StellarIP
This chapter describes the first steps taken when using StellarIP. It is a step by step instruction on how to use StellarIP. Each paragraph is dedicated to a specific task and they should be taken in the correct order. This chapter uses some pre created designs installed along with the 4DSP development kit. These design are call training materials and are described in the Training material description chapter. Two StellarIP training projects are installed with StellarIP and are available for all the hardware sold by 4DSP. And one training material is available for the ML605 only.
Note 1 : The training materials are sorted by interface type (Ethernet or PCI). Note 2: Never upload a firmware not targeting your specific hardware! 5.1 Firmware project creation
The purpose of this paragraph is to describe the steps required to create a firmware project that can be compiled using the Xilinx ISE utilities. We will use the trainmaterial_step1 StellarIP project to generate the Xilinx project file as well as simulate the design using Modelsim.
Note:
This chapter assumes C:\Program Files\4dsp\4FM Core Development Kit\StellarIP\Training
Material\Firmware and children have been copied to a local folder. This chapter will use {path} representing the actual path you have been copying the folder into. For example, if you have copied C:\Program Files\4dsp\4FM Core Development Kit\StellarIP\Training Material\Firmware to C:\, {path} is then C:\. Make sure you have read/write access to the target folder as the tools expects complete read/write/modify access policy on this folder.
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5.1.1
StellarIP plug-in configuration
First of all browse for a Stellar IP Definition File. In this case the trainmaterial_step1 StellarIP definition file found here: {path}\{interface}\Step 1\{projectname}\implement\{sdfname}.sdf StellarIP will automatically update the library path text field unless the User Defined check box is checked . Make sure the following options are NOT checked: Compile Project using Xilinx XST. Having this control checked makes StellarIP invoke the Xilinx command line tools to compile the firmware without any action from the user. Generate .hex files from XST results. Having this control checked makes StellarIP generate a programming file (.hex) ready to be uploaded into the 4DSP hardware.
Note : At the time of writing, the training material firmware are available for FM680, FC6301 and
VP680 4DSP hardware as well as the Xilinxs ML605. Substitute {projectname} and {sdfname} in the path above with the actual names for the hardware you have purchased from 4DSP or Xilinx. 5.1.2 Launch StellarIP
This is as straightforward as pressing the Generate button and wait for it to finish.
Figure 14: StellarIP view after successful generation.
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5.1.3
Examine StellarIP results
StellarIP has created a complete Xilinx ISE project which includes a few files worth mentioning. In chapter StellarIP plug-in configuration we have browsed to a path containing a StellarIP Definition File (.sdf). The StellarIP Definition File was part of the Implement folder and the StellarIP output is created in the Output folder. By default, the output folder is found at the following path: {path}\{interface}\Step 1\{projectname}\output\{projectname}\. Available after StellarIP generation: compile.do is a TCL macro for Modelsim. This file compiles the complete design and is typically called by the testbench compile.do macro. This gets Modelsim ready to simulate the design. trainmaterial_step1.bat is a batch file for Windows. It will invoke Xilinx tools (command line) to compile the project. trainmaterial_step1.xise/ise is Xilinx ISE Navigator files. These files can be loaded into Xilinx Project Navigator like any other Xilinx ISE project. trainmaterial_step1.h is a software header with addresses of all the stars part of our constellation. In other words, this is the constellations mapping table. Src is a sub folder where all the VHDL sources are located.
Figure 15: Output folder created by StellarIP
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5.2 Simulating StellarIP results

First start Modelsim, and the select File and Change Directory. Browse to the following firmware folder: {path}\{interface}\Step 1\{projectname}\simulate\modelsim. Then select Tools then Tcl then Execute Macro and select compile.do in the file dialog. The design is going to be compiled. Please wait for the compilation to finish and then add some signals to the waveform view. Right click on the main top level and select Add > To Wave > All items in region. A new dialog showing the wave will appear.
Figure 16: Selection of all the signals
Go back to the main Modelsim window and at the bottom you will see a text area named Transcript. You can then type run 200 us to move the simulation up to 200 microseconds. At this time the waveforms can be viewed from the Wave view as for a standard programmable logic project. You can again type run 200 us to move the simulation up to 400 microseconds. Some additional information is available on Modelsims debug view: # ** Warning: DMA Push/Pull 2K # Time: 267505100 ps Iteration: 0 Instance: /tb_trainmaterial_step1/fpga_a # ** Note: DMA Push, Size 2048 bytes # Time: 272600 ns Iteration: 0 Instance: /tb_trainmaterial_step1/fpga_a # ** Note: DMA Pull, Size 2048 bytes
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# Time: 275744 ns Iteration: 0 Instance: /tb_trainmaterial_step1/fpga_a # ** Note: Ready with reading SIP CMD script! # Time: 276744 ns Iteration: 0 Instance: /tb_trainmaterial_step1/fpga_a # ** Warning: Testbench ended # Time: 286744 ns Iteration: 0 Instance: /tb_trainmaterial_step1/fpga_a Additionally, the file output.txt found {path}\{interface}\Step 1\{projectname}\simulate\modelsim can be opened to ensure the data contained is as expected. The training material step1 design loops back DMA data so the file output.txt should match input.txt.
Note : input.txt is bigger than output.txt. 5.3 Modifying simulation behaviour

The test bench used for this simulation actually reads a file from the modelsim folder. This file is called sip_cmd.sip and can be found at the following location: {path}\{interface}\Step 1\{projectname}\simulate\modelsim This file is a script and this script can be changed thus modifying the simulation behaviour. Commands available in the script are among the following: WAIT = {value} REG_GET = {address} REG_SET = {address} {value} DMAPUSH = {size} DMAPULL = {size} Wait for the specified amount of time in micro second(us). Read a 32 bit value at a given address. Write a 32 bit value at a given address Send an amount of bytes using DMA operation. Note that the data is actually read from the input.txt file. Receive an amount of byte using DMA operation. Note that the data is actually wrote to the output.txt file.
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5.4 Open and compile the project in Xilinx ISE

From the start menu, go to Xilinx ISE Design Suite > ISE Design Tools > Project Navigator. Browse to the .xise file located in {path}\{interface}\Step 1\{projectname}\output. Xilinx ISE Navigator loads the project providing the user with a known and proven compilation flow. Additionally, one can check the Compile Design using XST check box in StellarIP and then the design is going to be compiled by Xilinx tools automatically as soon you press the Generate button. In this case one does not even need to open the project in ISE Navigator.
Figure 17: Design successfully compiled using ISE Project Navigator
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6 StellarIP Star Creation

4DSP provides the end user with a consequent set of intuitive stars (IP-Cores). These stars are generic and can be used on most of the 4DSP hardware. Memory controllers, data routers, command routers and daughter board interface stars are provided to the end users by 4DSP. In most of the cases custom stars have to be created. This chapter explains the steps required to extend the training material step 2 with a dummy star providing the host with a few additional read/write registers in the firmware. These register can be read/written by the host computer.
Figure 18 : StellarIPs star editor component
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6.1 Preparation
Lets prepare a training material step 3 folder along the other training material. The idea here is duplicating the step2 folder (found by default on {path}\Firmware\{interface}). Name this folder Step 3 and place this folder somewhere on your harddisk where you have read/write/modify access rights for.
Note : pre created Step3 training materials are already existing and can be found in the same
firmware folder. This is why it makes sense to duplicate Step two folders somewhere else on your hard disk. We should also rename the StellarIP files in this folder from {id}_trainmaterial_step2.* to {id}_trainmaterial_step3.*. The files to be renamed are found by default on {id}_step3\{projectname}\implement. For example, a file ml605_trainmaterial_step2_lx240t.big should be renamed to ml605_trainmaterial_step3_lx240t.big. Lets also modify ml605_trainmaterial_step3_lx240t.sdf. We have to change the project name (PROJ_NAME), the project ID (PROJ_ID), the project description (PROJ_DESC), the author name (PROJ_AUTHOR) as well as the project constraint file location (PROJ_CONSTRAINTS). Modified lines are showed below:
PROJ_NAME={projectname}; PROJ_DESC=FM680 training material (step 3); PROJ_ID=555; PROJ_AUTHOR=Trainee; PROJ_CONSTRAINTS={projectname}.ucf;
Note : substitute {projectname} for both PROJ_NAME and PROJ_CONSTRAINTS with the actual
project name, the name of the .sdf is in fact {projectname}. As an example if your sdf file is called ml605_trainmaterial_step3_lx240t.sdf, then {projectname} inside this file is ml605_trainmaterial_step3_lx240t
At this stage it is good habit to try compiling the design making sure the design is still compiling properly.
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The Star Selection drop-down list in the Star Editor plug-in shows stars available in the library.
Figure 19 : Star Selection view
6.2 Adding a custom star

There are two ways to add a new star: either recreate everything from scratch or use the star cloning feature. The idea of cloning is to clone a previously existing star and modify the cloned star afterwards. Pressing Add an empty or cloned star to the library button triggers the Star creation dialog where we are going to uncheck the Clone Stars source files(.nfo, .lst, .vhd) and name the new star as sip_regonly. As soon we are back to the main Star Editor view we have to press the Save current star to file button saving the current star (sip_regonly) into the library.
Figure 20 : Star creation dialog view
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6.3 Configuring the custom star

Using the Star View, please create the following wormholes into the sip_regonly star by right-right clicking anywhere in the Star View and selecting Add: A wormhole named cmdclk_in of type cmdclk_in A wormhole named cmd_in of type cmd_in A wormhole named rst of type rst_in A wormhole named cmd_out of type cmd_out A wormhole named generic of type generic_def
Still using the Star View, please configure the Number Registers field to 4 and make sure Include Register Code is checked. This tells StellarIP that the star sip_regonly has four registers. You may refer to the picture below showing proper configuration of the Star Editor plug-in. Do not forget to press the Save current star to file button in order to save your changes to library itself.
Figure 21 : Proper "Star Editor" configuration for our "sip_regonly" star 4FM Get Started Guide www.4dsp.com
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6.4 Generate support code for the custom star

The last step is generating the actual star code. StellarIP will do that automatically as soon the Generate HDL skeleton from current star button is pressed. Pressing the Generate HDL skeleton from current star button triggers the Browse for Folder dialog where we browse to our HDL support code. This path is where all the stars are already located. Typically if you have created the Step3 duplicate in C:\MyDsn then the resulting path to save the library would be C:\MyDsn\555_ml605_trainmaterial_step3\star_lib Now click the Make New Folder button and make a folder named to sip_regonly.
Figure 22 : Creation of the folder for the new star
Pressing Ok button actually creates the VHDL code for this star. Successful generation of a star yield into something equivalent to the following log:
INFO INFO INFO INFO INFO INFO INFO : Created the top level star skeleton. : Translated stellar_cmd template. : Translated stellar_regs template. : Added registers into the entity. : Replaced component declaration into the file. : Replaced component instantiation into the file. : Created the initial star .lst file
The output folder (C:\MyDsn\555_ml605_trainmaterial_step3\star_lib\sip_regonly) should now contain five files: sip_regonly.lst, sip_regonly.nfo, sip_regonly.vhd, sip_regonly_stellar_cmd.vhd and sip_regonly_stellar_regs.vhd.
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The last step to have a valid star is to modify the info file (.nfo) for the star. The file should be modified in the output folder (C:\MyDsn\555_ml605_trainmaterial_step3\star_lib\sip_regonly). The .nfo file has two lines and is generally names {starname}.nfo. The first line is the star ID number and the second one is the version. In this case we are creating a .nfo file with only two ASCII lines:
STAR_ID=0999 STAR_VERSION=0200
We have successfully added a custom star to the library and to the support code area. The star does nothing besides allowing the host to read/write registers into it at the moment.
6.5 Incorporating our new star into the definition file

We can now configure our constellation description file with the new star. In the projects Implement folder, locate and open the .sdf file with a text editor. Add a star declaration line ( STAR , ID=..., FILE=;) corresponding to the star we have just added. The new line added should be like the following:
STAR sip_regonly ,ID=0 ,FILE=sip_regonly\sip_regonly.lst;
We connect sip_regonly stars inputs. The following line should be added to the .sdf file:
--connect regonly inputs sip_regonly.0(rst) sip_regonly.0(cmdclk_in) sip_regonly.0(cmd_in) <= sip_clkrst_fm680.0(rst_out); <= sip_ifpga_sl.0(cmdclk_out); <= sip_ifpga_sl.0(cmd_out);
Note : for a ml605-ethernet, sip_ifpga_sl should be replaced with sip_mac_engine and

sip_clkrst_fm680 should be replaced with sip_mac_engine. In order to understand more about this you might want to check the pre-created step3 firmwares. We only have to modify one connection in the command mux (cmd3_in) as follows:
sip_cmd12_mux.0(cmd3_in) becomes sip_cmd12_mux.0(cmd3_in) <= tiedto0; <= sip_regonly.0(cmd_out);
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6.6 Compile the new design

As described in the chapter StellarIP (Firmware project creation), you can compile the project substituting training material step2 with training material step3.
6.7 Verifying our modifications

A simple way to verify if our star has been properly inserted by StellarIP is to check the projects header file (.h). This file includes definition for all the stars including their addresses. We can see in the constellation header (trainmaterial_Step3.h) that the regonly star is part of our design, we can also see that the ID and version match what we have placed into the .nfo file earlier. The start address is 0x2402 and the end address is 0x2405 which is indeed what the four registers are.
6.8 Uploading a firmware (PCI/PCIe hardware)

On chapter StellarIP (Firmware project creation) we have generated a project using StellarIP and compiled the project using Xilinx Project Navigator. In this chapter we will explain how to upload the firmware to the hardware. Two options are available: the first one is to directly upload the firmware via the JTAG chain using Xilinx Impact and a JTAG programmer while the second method is to upload the firmware into the FLASH memory. Uploading a bit file using a JTAG is outside the scope of this manual so only the second option is described below. 6.8.1 Convert the .bit file into a .hex file (bit2hex)
The .bit file previously created needs to be converted to a programming file (.hex) in order to be uploaded into the flash device. A bit file conversion tool is available and has been installed/referenced by the installer. Browse to the C:\Program Files\4dsp\4FM Core Development Kit\Bins folder. Drag and drop trainmaterial_step1.bit file onto bit2hex icon. The .bit file has been generated previously and can be found at the following location: C:\Program Files\4dsp\4FM Core Development Kit\StellarIP\Training Material\Firmware\{interface}\Step 3\projectname}\output\. The bit2hex application will generate a programming file using Xilinx Impact and this file will be created in the same folder as trainmaterial_step1.bit is. 6.8.2 Convert the .bit file into a .hex file (shell extension)
On Windows 7, the SDK includes a kernel extension one can use to easily convert a .bit file into a .hex file. It is available when right clicking a .bit file and choosing Convert to programming file (.hex).
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The .bit file is going to be converted to a .hex file and the .bit file will be deleted. Note that this process can take up to two minutes and no specific information will be displayed on the screen. 6.8.3 Upload the firmware into hardware
Now that we have a .hex programming file we will use the 4FM GUI Control application and the Registers/Update plug-in. We want to upload a firmware into FPGA B because FPGA A should not be changed unless explicitly requested by 4DSP. Browse to the .hex file just created and press the Load button. As soon the operation succeeds, you should do a power cycle of the computer. After the computer has rebooted start the 4FM GUI control application, select the hardware, and switch to the Diagnostics/Information plug-in. The FPGA B firmware ID has changed and now reflects the training material step1 as expected.
6.9 Test the firmware using StellarIPs Script Parser (PCI/PCIe hardware)
During our simulation we have looked and modified the sip_cmd.sip file on chapter Modifying simulation behaviour. 4DSP provides the customers with an application which parses this file and communicates with the hardware through the API and the device driver. It is generally convenient to quickly inspect firmware behavior; this is possible without the requirement of coding a line of software. This application is a command line application and has been referenced by the SDK installer which can be called from any folder in your system. The syntax of this application is the following:
4FM SIP Script Parser.exe {Device Type} {Device Number} {Script Name}
Device Type is the device type you have purchased from 4DSP (FM489, FM680, FC6301) Device Number is always 0 (zero) unless you have several 4DSP hardware devices in your system. Script Name is the name of the script needed to be parsed by the application.
Open a command prompt windows and change directory (cd) to the modelsim folder:
cd {path}\{interface}\Step 3\{projectname}\simulate\modelsim 4FM Get Started Guide www.4dsp.com
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Then launch the application:

"4FM SIP Script Parser.exe" {deviceype} 0 sip_cmd.sip
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6.10 Test the firmware using training materials reference application

Both of the training materials (step1 and step2) are accompanied by reference software. These reference softwares are actually reading/writing registers and receiving/sending data using DMA operations. They can be loaded and compiled using Microsoft Visual Studio 2008. The step1 software project can be found at the following path: C:\Program Files\4dsp\4FM Core Development Kit\StellarIP\Training Material\Software Pressing CTRL-F5 in visual studio will compile and execute the application.
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7 Training materials
Training materials are provided to the customers: step1 and step2. These examples are very similar to each other and both have a firmware and a software project. The firmware is meant to be processed by StellarIP and the software is meant to be compiled by Microsoft Visual Studio. Make sure to use the correct training material for the device you are targeting. If you are targeting a VP680 device, then use the VP680 training material during your tests. If the training material for your device does not exist, then please email support@4dsp.com for help. Please check the StellarIP definition file (.sdf) to make sure the actual FPGA device supported by the training material matches the FPGA device you are targeting. Modify the sdf only if required. In order to modify a design to a SX375T, change:
TRGT_FPGA_TYPE=XC6VLX240T-1FF1759; ( old )
To:
TRGT_FPGA_TYPE=XC6VSX375T-1FF1759; ( new )
7.1 Step 1
Step1 material can be found at the following location: C:\Program Files\4dsp\4FM Core Development Kit\StellarIP\Training Material\Firmware\{interface}\Step 1 There you will find the files the first constellation is made from. This constellation includes the bare minimum firmware targeting FPGA B. The StellarIP Definition File (.sdf) is to be found under the implement folder. Step1 is likely to be used as a skeleton for your own project. The .sdf file declares following stars and the top-level diagram is depicted in Figure 23: sip_cid This star is optional but recommended. It allows the host application to retrieve various information as the firmware ID given in the Stellar Definition File (.sdf). This star is not used in the step but will be used later on. sip_clkrst_fm680 This star is required. It provides the firmware blocks with the required clocks and reset signals available from the inter-FPGA interface. A Firmware requires reset signals and clocks. This star provides the user with several clock and reset phases and frequency.
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sip_ifpga_sl
This star is a bridge between FPGA A and FPGA B. It has a command wormhole as well as a data wormhole. The commands and data are forwarded by FPGA A providing a communication interface between the host computer and FPGA B.
sip_cmd12_mux
Every star has a command wormhole output able to return register data to the host. This multiplexer allows to "multiplex" 12 command wormholes to one command wormhole.
SIP IFPGA SL
SIP CID
SIP CMD12 MUX
SIP CLKRST
data
Cmd_in
Cmd_out
Figure 23: training material 1 top level diagram.
In this constellation, the sip_ifpga_sl star has its data input wormhole connected to its data output wormhole. This provides a loop-back mechanism. Any data send to the board up to 4096 bytes will be echoed by the firmware. The software flow is as the following: 1) Two 4kB (4096 bytes) aligned buffers are allocated using Microsoft's _aligned_malloc() function. 2) The 4DSP hardware is opened and then initialized using _4FM_OpenDevice(), _4FM_ResetDevice() and _4FM_SelectTarget(). 3) The output DMA buffer is filled with random data using rand(). 4) The output DMA buffer containing random data is sent to the hardware(firmware) using _4FM_SendData(). 5) The input DMA buffer obtains data from the hardware(firmware) using _4FM_ReceiveData(). 6) Both DMA buffers are then compared and should be equal. Note1 : The ML605 ethernet training material are limited to 1kB transfer and therefore the 4kB above should be reduce to 1kB (1024 bytes). Note 2 : SIP IFPGA SL can be substituted with SIP HOST IF on the FC6301/VP680/ML605 training material
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7.2 Step 2
Step2 material can be found at the following location: C:\Program Files\4dsp\4FM Core Development Kit\StellarIP\Training Material\Firmware\{interface}\Step 2 Here you can find the files the training material step2 constellation is made from. This constellation includes the bare minimum a firmware targeting FPGA B. Additionally it includes an adder star. The adder star has a command input and output wormhole, two configuration registers as well as a data input and a data output wormhole. The StellarIP Definition File (.sdf) file is to be found under the implement folder. Step2 is also likely to be used as a skeleton for your own project. A top level diagram of this constellation is depicted in Figure 24. The .sdf file declares following stars: sip_cid This star is optional but recommended. It allows the host application to retrieve various information as the firmware ID given in the Stellar Definition File (.sdf). This star is not used in the step but will be used later on. sip_clkrst_fm680 This star is required. It provides the firmware blocks with the required clocks and reset signals available from the inter-FPGA interface. A Firmware requires reset signals and clocks. This star provides the user with several clock and reset phases and frequency. sip_ifpga_sl This star is a bridge between FPGA A and FPGA B. It has a command wormhole as well as a data wormhole. The commands and data are forwarded by FPGA A providing a communication interface between the host computer and FPGA B. sip_cmd12_mux Every star has a command wormhole output able to return parameters to the host. This multiplexer allows to "multiplex" 12 command wormholes to one command wormhole. sip_adder This star can receive a 64 bit wide data stream ( on the data_in port ) and it can output a 64 bit data stream ( on the data_out port ). It also has two 32 bit wide configuration registers representing the value to add on the input data stream. data_out[i] = data_in[i] + (Register2<<32|Register1).
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SIP Adder
SIP IFPGA SL
SIP CID
SIP CMD12 MUX
SIP CLKRST
data
Cmd_in
Cmd_out
Figure 24: Training material step 2 top level diagram
In this constellation, the sip_ifpga_sl star output wormhole is connected to the adder star's data input wormhole. On the other hand, the sip_ifpga_sl star input wormhole is connected to the adder star's data output wormhole. The sip_ifpga_sl star command output is connected to the adder star's command input wormhole. The software flow is as the following: 1) Two 4kB (4096 bytes) aligned buffers are allocated using Microsoft's _aligned_malloc() function. 2) The output DMA buffer is filled with zero memset(). 3) The 4DSP hardware is opened and then initialized using _4FM_OpenDevice(), _4FM_ResetDevice() and _4FM_SelectTarget(). 4) The adder star in the firmware is configured via 2 configuration registers modified using _4FM_Write(). 5) The output DMA buffer containing zero data is sent to the hardware(firmware) using _4FM_SendData(). 6) The input DMA buffer obtains data from the hardware(firmware) using _4FM_ReceiveData(). 7) The expected value pointed by any index is computed. 8) The input DMA buffer is verified. Note 1 : The ML605 ethernet training material are limited to 1kB transfer and therefore the 4kB above should be reduce to 1kB (1024 bytes). Note 2 : SIP IFPGA SL can be substituted with SIP HOST IF on the FC6301/VP680/ML605 training material
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7.3 Step 3
Step3 was created on chapter StellarIP Star Creation: C:\Program Files\4dsp\4FM Core Development Kit\StellarIP\Training Material\Firmware\{interface}\Step 3
7.4 Step 4
This training material is not yet described but is actually an extension of Step 1 training material providing a blockRAM based FIFO for the ML605-Ethernet interface. It provides transfer up to 64kB.
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8 Evaluating FMC AD/DA product using Xilinx Development kits (ML605, SP601, SP605)
1) 2) 3) Make sure the development board (either SP601 or ML605) is powered down. In case of ML605, make sure the PHY jumper setting on the development board selects GMII/MII interface mode. This is the factory default jumper setting. Plug the FMC card on the development board. Use the LPC connector on the ML605 (J63) for LPC boards or use the HPC connector on the ML605 (J64) for HPC boards.
FMC (LPC) FMC (HPC)
USB JTAG Jumpers Ethernet
Figure 25: ML605 development board

USB JTAG
FMC (LPC)
Ethernet
Figure 26: SP601 development board
4)
Connect the USB cable that comes with the development board to the USB JTAG connection on the development board. Connect the other end of the cable to your host computer.
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5)
6)
Connect the Ethernet cable that comes with the development board to the Ethernet connection on the development board. Connect the other end of the cable to your host computer (only direct connection without Ethernet switch/hub is supported). Power up the development board.
Make sure there is proper air flow across the FMC card when power is supplied to the board. A minimum airflow of 300 LFM is recommended. 4DSPs warranty does not cover boards on which the maximum allowed temperature has been exceeded.
7) Load the reference firmware from C:\Program Files\4dsp\Common\Firmware\Recovery. The FMC reference firmware are found among the following folders: a. 078_ml605_fmc110 b. 088_ml605_fmc150 c. 089_ml605_fmc126 d. 092_sp601_fmc150 e. 095_ml605_fmc204 f. 098_sp605_fmc150 g. 104_ml605_fmc125 h. 111_ml605_fmc108 i. 112_ml605_fmc104 j. 113_ml605_fmc103 k. 114_ml605_fmc107 8) Xilinx Impact can be used to directly load the .bit files to the FPGA using Boundary Scan. Choose the bit file that reflects your development board and FMC card, for example: a. ml605_fmc110.bit needs to be used for evaluation of the FMC110 on a ML605 development board. b. sp601_fmc104.bit needs to be used for evaluation of the FMC104 on a SP601 development board. 9) From a command window browse to C:\Program Files\4DSP\FMC Board Support Package\Bins and run the application that matches your FMC card. Refer to Table 1. A list of Ethernet devices is shown. Look for the Ethernet device that connects to the development board. 10) Call the application, here is the application usage:
FMCxxxApp.exe {interface type} {device type} {device index} {clock mode}
Where interface type is either 0 (PCI) or 1 (Ethernet), device type is a board as the ML605, device index is the NDIS device index found about on 9) and clock mode can be either 0 (Internal clock) or 1 (External Clock).
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11)
12)
The sample data is stored in the folder C:\Program Files\4DSP\FMC Board Support Package\Bins for each channel an ASCII file and a binary file is created (bufx.txt (ASCII) and bufx.bin (Binary)). The DAC outputs (if applicable) will show a sine wave. FMC series FMC10x series FMC110 series FMC204 series FMC12x series FMC150 series FMC Types FMC108, FMC107, FMC104, FMC103 FMC110 FMC204 FMC122, FMC125, FMC126 FMC150
Table 1: Application overview
Application Fmc10xApp.exe Fmc110App.exe Fmc204App.exe Fmc12xApp.exe Fmc150App.exe
Note : If the access right are not correct, the application will not store any buffer to hard disk. If this would happen, then copy the compiled application somewhere you have write access, typically the Desktop is a place every user has got write access by default.
8.1 Documentation
For each board type a user manual is installed in C:\Program Files\4DSP\FMC Board Support Package\Docs. The firmware (constellation) documentation as well as star (ip core) documentation is found in the .4ff files. More information about firmware and 4ff files can be found in Firmware overview chapter.
8.2 Reference Firmware Matrix

4DSP FMC product FMC108 (HPC) FMC107 (LPC) FMC104 (LPC) FMC103 (LPC) FMC110 (HPC) SP601 (Spartan-6) SP605 (Spartan-6) ML605 (Virtex-6)
X V1 V1 V1 X
X V1 V1 V1 X
V V V V V
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FMC204 (HPC) FMC122 (LPC) FMC125 (HPC) FMC126 (HPC) FMC150 (LPC)
X V1 X X V
X V1 X X V
V V V V V
Table 2: Compliancy matrix

1
Reference firmware not yet released. Please contact 4DSP for more information
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9 Evaluating FMC DSP product using Xilinx Development kits (ML605)

9.1 Quick start
This paragraph provides short introduction on what the development framework looks like and then describes the steps required in order to get started with framework. A typical FMC-DSP development system is comprised of a host computer, an ML605 evaluation kit from Xilinx and a FMC645 mezzanine board.
ML605-FPGA
Microblaze Processor HOST Computer (USB Port + Ethernet)
FMC645-DSP
GMII(1Gbps) EMAC PASS THRU
Figure 27: Elements constituting the FMC-DSP environment
Note that the framework expects the host computer to have a 1Gbps Ethernet port (10Mbps and 100Mbps are not supported by the ML605 FPGA firmware).
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9.1.1
Prepare the host computer
The TCP/IP settings in windows should be changed for the Ethernet interface about to receive connection to the ML605. The settings should reflect the settings on the image below. Note that this interface must support 1Gbps (one Giga bit per seconds) as the firmware does not support 10/100Mbps speeds.
Figure 28: Valid TCP/IPv4 settings for the framework
The virtual com driver required by the CP2102 chip on the ML605 should be downloaded on the Silicon Labs website. A direct link to the actual installer is CP210x driver download. Please reboot your host computer if prompted to do so.
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9.1.2 -
Prepare and connect ML605 to the host computer An USB cable between ML605s JTAG and the host computer. An USB cable between ML605s UART and the host computer. An Ethernet cable between ML605s Ethernet connector and the host computer. The Ethernet interface on the host computer should support 1Gbps as 10/100Mbps are not supported by the FPGA firmware.
Three cables should be connected between the ML605 and the host computer:
The FMC6xx mezzanine should be attached to the ML605s HPC FMC connector. 9.1.3 Programming ML605 FPGA device (Virtex 6 LX240T)
The FPGA on ML605 should be programmed with a firmware in order to operate properly. The required FPGA programming file (.bit) is provided by 4DSP and is to be found in the same folder as the FLASH programming file. These items are found i the recovery portion of the firmware files installed by this installer. The default path for these recovery files is C:\Program Files\4DSP\Common\Firmware\Recovery\196_ml605_fmc645. Xilinx iMPACT should be used in order to upload the FPGA programming file (.bit) in the FPGA. More information about firmware and recovery files can be found in the following chapter: 4FM Firmware (Recovery Files) 9.1.4 Programming ML605 Flash device (Optional)
If the FLASH device is not programmed, then impact should be used to program the FPGA programming file (.bit) into the FPGA each time ML605 is power cycled. This is equivalent of repeating instructions in the Programming ML605 FPGA device (Virtex 6 LX240T) paragraph again and again. The required FLASH programming file (.mcs) is provided by 4DSP and is to be found in the same folder as the FPGA programming file. These items are found in the recovery portion of the firmware file installed by this installer. The default path for these recovery files is C:\Program Files\4DSP\Common\Firmware\Recovery\196_ml605_fmc645. More information about firmware and recovery files can be found in the following chapter: 4FM Firmware (Recovery Files)
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Procedure: 1) Configure ML605s S2 dip switch block as the following (S2.1=Off, S2.2=On, S2.3=Off, S2.4=On, S2.5=Off and S2.6=Off). 2) Attach an USB cable from ML605s JTAG port to the host computer. 3) Power up ML605. 4) Open Xilinx IMPACT and choose Boundary Scan from the left pane 5) Right click on the right pane and and choose Initialize Chain from the contextual menu. 6) On the chain representation, double click SPI/BPI above xc6lv240t. 7) In the ADD Prom File dialog browse to the correct FLASH programming file (.mcs) and press OK. 8) In the Select Attached SPI/BPI choose BPI PROM, 28F256P30, 16 and NOT USED and press OK. 9) Click on the FLASH device above xc6vlx240t and double click Program from the iMPACT Processes on the left pane. 10) Leave all the default settings in the Device Programming Properties dialog and press OK. 11) Wait for about 20-25 minutes this is the time required to complete the FLASH upload process. 9.1.5 Verify FPGA firmware initialization
After programming the FPGA using iMPACT or having the FPGA configuration stored into ML605 FLASH it is mandatory to check for proper firmware initialization. A wrong firmware initialization indicates that the FPGA firmware is not ready for operation. Note that pressing CPU RST, SW10, causes the complete ML605 to be reset and the FPGA firmware initialization restarts so press that if you see an incorrect LEDs status. Note that an FMC645 mezzanine board should be attached to the HPC connector in order to have LEDs displaying a proper initialization status.
Figure 29: GPIO LEDs showing status of a proper firmware initialization
The FPGA firmware initialization status is displayed on ML605s GPIO LEDs and it is important that this LEDs display Ready status.
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9.1.6
Check which virtual COM (UART) port is featured by the device driver
While following paragraph Prepare the host computers instructions, we have installed a virtual COM port driver downloaded from Silicon Labs website. The driver will kick in as soon the ML605 is powered up and an USB cable is connected between ML605s UART connector and the host computer. Looking at Windowss device manager in the Ports (COM & LPT) category indicates which COM port the ML605 is mapped to through the virtual COM port. In our case the com port name is COM5 as the following screen capture shows. This is the actual com port argument we will be passing to the test application later on.
Figure 30: Which COM port is featured by the system
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9.1.7
Description of the FMC645 Test Peripheral Application
4DSP provides a reference application able to check all the DSP interfaces. The DSP device is in charge of testing various DSP interfaces and is controlled by the host computer through a processor implemented in the ML605 FPGA. This application is provided as source code and as a precompiled executable. The precompiled binary is the component we are going to use on the next chapter. Complete execution of the application takes 5 to 10 minutes and goes through testing the following interfaces: 9.1.8 I2C PCI GPIO EMIFA MCBSP ETHERNET Executing the FMC645 Test Peripheral Application
In a command prompt window, navigate (cd) to FMC board support package binary folder (default location is C:\Program Files\4DSP\FMC Board Support Package\Bins) and execute the application. cd C:\Program Files\4DSP\FMC Board Support Package\Bins fmc645_microblaze_test_peripherals.exe COM5
Note that COM5 passed as argument should be replaced the actual COM port found while following instructions on paragraph Check which virtual COM (UART) port is featured by the device driver. An example of correct console output can be seen in Annex (Annex 5 fmc645 test peripherals log) 9.1.9 Obtaining more information, technical support
Please refer to the FMC645 or the FMC667 user manuals for a detailed description of the BSP as well as detailed instruction on how to compile the FPGA firmware, the Microblaze software as well the DSP software. In case of technical problems, please register to the 4DSP support forum (4DSP Forum) indicating the serial number of your mezzanine card.
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10 Annex 1 Manual Firmware Installation

The firmware is automatically decrypted and extracted by the installer during the installation. Instructions are provided below to manually decrypt the firmware if needed. Note that the firmware package contains a lot of different firmware. For example, if you purchased an FM482 you will not have a license line for FC6301; hence you will not be able to decrypt FC6301 firmware. Do not attempt to install any other firmware that is not specific to your hardware. Note that this step does not cover uploading a firmware into the hardware but only the decryption and extraction process. Without a decryption license you for a specific firmware you are only able to access recovery files. These files are ready to be uploaded in the firmware. The recovery firmware files have a .hex extension and are located at the following paths: C:\Program Files\4DSP\Common\Firmware\Recovery (32-bit) C:\Program Files (x86)\4DSP\Common\Firmware\Recovery (64-bit) The encrypted firmware packages have a .4ff extension and are located at the following path: C:\ Program Files\4DSP\Common\Firmware\ (32-bit) C:\ Program Files (x86)\4DSP\Common\Firmware\ (64-bit)
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10.1 Select a input firmware package file

Open the 4FM GUI, select your device from the drop-down menu, and wait for the plug-ins to load. Select the FW Installer tab, locate Input Firmware and click the button marked on the righthand side. Choose a firmware package file. In this example we are installing an FM482 firmware. We have the correct license code for FM482.
Figure 31: Browsing to a firmware file.
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10.2 Select an output folder

Locate Output Folder and click the button marked on the right-hand side. Choose an output folder where the firmware will be created. All firmware will be installed in a subfolder. Note: you do not need to create a subfolder by yourself.
Figure 32: Browsing to an output folder
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10.3 Install the firmware

As soon you have selected an input and an output file, you may launch the installation process by pressing the Install The Firmware button. The progress is updated in real time in the debug area. After a while the decompression starts and the following view can be seen:
Figure 33: The firmware installer decompresses the data
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10.4 In case of trouble

If for some reason the installation does not go through, please pay attention to the log of events in the main debug area. Make sure your license file is installed properly. For example, if you are trying to install an FM482 firmware then you need to have an FM482 line in your license file. The license should be as the next one. Obviously, sign, keys and such will be different in your license code. In order to install a firmware, the license line NOTICE= field should be set to SOURCE and the KEY= field should have a 64 digits key.
PRODUCT=FM482 VERSION=2009.4 SN=12345678 CUSTNR=0 DELIVERYNR=0 NOTICE=SOURCE KEY=123460937B26B5765426AD4CDF79E198863EBC51863EF65A7EA6F75B4D962151 EXPIRY=NEVER HOSTID=ANY SIGN="AC3I 6PAA SVQJ WZY3 BBYY 9WRS XT5F SBKB 4CGR ZPKX P24J NQ25 8TT7 PNYE SPAS BM6Q 52TF NXRN AEES 5Y53 NREB GUAS X32D Q35H HWAG 96IR KEAR M95U 9SAC 22YI 7NUA 6E8K 5GSR RJ28 G6EJ C3RW IT65 JUEB I7JV H2QW G4WQ MFKE H57R IPFT BKII FBKJ S2DD 2WGD 7WUE CH6Q MFIB TJE5 9PHA"
Following is an example log of events after a successful installation:

INFO wait.. STATUS : Processing firmware package 'fm482_feb09_fpgaA_ddr_test.4ff', please : Reading from file 'fm482_feb09_fpgaA_ddr_test.4ff'
STATUS : Closing 'C:\Documents and Settings\Arnaud Maye\Desktop\FW_POOL\Firmware 4FF\fm482_feb09_fpgaA_ddr_test.4ff' STATUS INFO STATUS : Computing CRC of file 'fm482_feb09_fpgaA_ddr_test.4ff', please wait : Successfully verified 'fm482_feb09_fpgaA_ddr_test.4ff' integrity. : DeObfsucating 'fm482_feb09_fpgaA_ddr_test.4ff'
ERROR : Computing CRC of the code block in 'fm482_feb09_fpgaA_ddr_test.4ff', please wait INFO STATUS INFO STATUS STATUS STATUS STATUS : Successfully verified 'fm482_feb09_fpgaA_ddr_test.4ff' integrity. : Successfully checked out a license for the selected .4FF file : Decrypting the code block , please wait... (can take up to 10 minutes) : Computing CRC of 'temp.7z' : Verified decryption... The file is ready to be uncompressed... : Decompressing 'temp.7z' : The firmware is ready to be used
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11 Annex 2 License File details

11.1 Introduction
All development kits from version 2 and up require a license for each software component, in order to run. As soon the core graphical user interface tries to load a plug-in, the plug-in will first check to see that the information in the license line matches the license code stored in the license file. If the correct license code cannot be found, the plug-in will not load. The same mechanism is used to install the firmware packages. If you do not have a license for a specific firmware package, you cannot install the package. The license code is specific. For each different firmware package, a DEMO license does not allow you to install a firmware package. However a SOURCES license allows a firmware package to be installed. A license line can be either floating (can be used on any computer) or locked to a specific computer. 4DSPs license policy allows customer to obtain either floating or locked license files. Please contact the 4DSP sales department if the license you have received does not suit your requirement. If you have received a development kit on loan or on rent then it is likely your license is going to have an expiration date. As soon the expiration date has passed, the plug-ins will refuse to load and you will have to contact 4DSP support to obtain an extended evaluation period.
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11.2 License format

PRODUCT=FM482 VERSION=2009.4 SN=12345678 CUSTNR=0 DELIVERYNR=0 NOTICE=SOURCE KEY=12345678 EXPIRY=NEVER HOSTID=ANY SIGN="AC3I 9PHA"
This is a sample license. Any modification to the license file will render the license invalid. You are required one of these lines per product. 11.2.1 The NOTICE= field The notice field helps to understand what kind of license you have received. As of the date of this documents writing, 4DSP is issuing the following type of license codes: DEMO. This is a demo license file. These licenses are generally locked to a computer hardware ID as well as set with an expiration date. A DEMO license does not support installing any firmware. However you are allowed to use all the installed recovery files without any restriction. SOURCE. This is the license our customers receive which allows the licensee to install and decrypt firmware package files. These licenses are typically purchased as floating licenses without an expiration date.
11.2.2 The HOSTID= field The HOSTID field allows a customer to understand what kind of license he has received. So far, 4DSP is issuing the following type of license codes: ANY. In this case the license can be used on any computer. However, please consult the EULA to ensure you are allowed to do that, especially if you have an agreement for a maximum number of seats with 4DSP. {ID}. If a code is there instead ANY. Then your license code will only operate on the machine with the same ID code. The computer ID is displayed in the main graphical user interface caption (HOSTID=nnnnnn).
11.2.3 The EXPIRY= field The HOSTID field allows a customer to understand what type of license he has received. As of the date of this document, 4DSP is issuing the following type of license codes: NEVER. This license code does not expire. {DATE}. This license operates until {DATE} is reached.
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12 Annex 3 - Compiling the 4FM Core Example

12.1 SDK Integration in Visual Studio 2008
In order to compile an application using this SDK you have to integrate the SDK in Visual Studio. To do so, launch Visual Studio and select Tools in the menu bar and then Options. Navigate to Projects and Solutions and then VC ++ Directories. You have to define a new folder in the Include files as well as in the Library Files by clicking the folder icon in the upper right-hand corner of the dialog. The 4FM SDK Core installer installs these two folders at the following path on a 32 bit system: (Libraries) : C:\Program Files\4dsp\4FM Core Development Kit\Libs (Includes) : C:\Program Files\4dsp\4FM Core Development Kit\Incs
Figure 34: Define a folder for "Include Files"
12.2 Compiling
The 4FM.vcproj Visual Studio project file can be opened and compiled like any other application sources.
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13 Annex 4 - Firmware .4FF file

The firmware packages are shipped as .4ff file and this stands for 4DSP Firmware File. 4ffs can be seen as an archive. The archive is heavily encrypted and signed and can only be decrypted by a user entitled to use this specific firmware. Please refer to the Firmware Installation chapter to understand how to decrypt a firmware using 4DSP tools.
13.1 4FF content

A decrypted firmware is a folder with several sub folders inside: A doc folder containing the firmware documentation. An implement folder containing the actual StellarIP source files for the firmware An output folder (empty or not). This folder will be populated at the moment the firmware is processed by StellarIP. A simulate firmware containing the simulation files for the firmware. A star_lib folder containing the firmware ipcores (star) provided by 4DSP for this specific firmware. A release_notes.txt
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13.2 4FF content (Hierarchical view)

Project name implement
output
doc
Firmware Documentation files
simulate
vhdl Test bench vhdl files
modelsim compile.do sip_cmd.sip input.txt output.txt
Star_lib
sip_xx
modelsim
IP specific Simulation scripts
library.xml (stellar IP library file)
sip_files
IP specific Files required for stellar IP flow
testbench
IP specific Testbench vhdl files
vhdl
IP specific vhdl sources
doc
IP specific documentation
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14 Annex 5 fmc645 test peripherals log

Welcome to the 4DSP FMC645 Peripherals test application! -----------------------------------------------------------------------Opening communication ports (Only UART): Done
-----------------------------------------------------------------------Checking StellarIP firmware attributes Firmware ID Firmware FW Version Number of FW stars sip_ub_fmc645 address : 196 : 1 : 5 : 0x0 Firmware SW Build Code : 1332412368 Firmware FW Build Code : 0
StellarIP attribute Test results : Test Succeeded!
-----------------------------------------------------------------------Testing I2C Bus on FMC645 I2C Test results : Test Succeeded!
-----------------------------------------------------------------------Now that I2C is verified, lets check board diagnostics, please wait...
Checking Board Diagnostics: Temp ADT Temp TMSC6455 3V3 1V8 OK (38C) OK (38C)
on FMC645 OK (3.2V) on FMC645 OK (1.8V)
1V25 on FMC645 OK (1.2V) 1V25 on FMC645 OK (1.2V) 2V5 3V3 0V9 on FMC645 OK (2.5V) on FMC645 OK (3.2V) on FMC645 OK (0.9V)
Diagnostics Test results : Test Succeeded!
-----------------------------------------------------------------------Now that I2C is verified, lets check 24LC02B chip, please wait... sip_fmc645_test address : 0xc0009000 Writing 256 bytes to the EEPROM
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.............................................................................................. .............................................................................................. .......................................................... Verifying 256 bytes in the EEPROM .............................................................................................. .............................................................................................. .......................................................... EEPROM verification finished with (0) error(s) 24LC02B Test results : Test Succeeded!
-----------------------------------------------------------------------Testing I2C communication from host to the TMS320C6455 device... Uploading the DSP software task to the DSP, please wait...(100%) I2C Test results : Test Succeeded!
-----------------------------------------------------------------------Measuring frequencies Stellar IP Clock : 100.00 MHz DSP CLKIN1 DSP CLKIN2 DSP CLK 50MHZ DSP CLK 125MHZ DSP SYSCLK4 : : : : 40.00 MHz 25.00 MHz 50.00 MHz 75.00 MHz (dsp clock = 1200.00 MHz)
: 125.00 MHz
-----------------------------------------------------------------------Testing GPIO on the FMC645... DSP Software about to be uploaded to DSP is 'fmc645_gpio_ack.hex' Argument1 (8 Bit) about to be passed to DSP is '0x00' Argument2 (8 Bit) about to be passed to DSP is '0x00' Uploading the DSP software task to the DSP, please wait...(100%) Waiting DSP to advertise himself as ready... Done! Sending first argument to DSP software... Done! Sending second argument to DSP software... Done! Telling DSP to start executing the DSP software... Done! Wait DSP software to indicate end of execution... Done! Reading error code register 1 from the DSP software... Done! Reading error code register 2 from the DSP software... Done! Status code 1 received from DSP software '0x0' Status code 2 received from DSP software '0x0' GPIO Test results: Status = Test Succeeded!
-----------------------------------------------------------------------Testing MCBSPs on the FMC645... DSP Software about to be uploaded to DSP is 'fmc645_mcbsp_ack.hex'
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Argument1 (8 Bit) about to be passed to DSP is '0x00' Argument2 (8 Bit) about to be passed to DSP is '0x00' Uploading the DSP software task to the DSP, please wait...(100%) Waiting DSP to advertise himself as ready... Done! Sending first argument to DSP software... Done! Sending second argument to DSP software... Done! Telling DSP to start executing the DSP software... Done! Wait DSP software to indicate end of execution... Done! Reading error code register 1 from the DSP software... Done! Reading error code register 2 from the DSP software... Done! Status code 1 received from DSP software '0x0' Status code 2 received from DSP software '0x0' MCBSP Test results: Status = Test Succeeded!
-----------------------------------------------------------------------Testing SRIO on the FMC645... DSP Software about to be uploaded to DSP is 'fmc645_srio_ack.hex' Argument1 (8 Bit) about to be passed to DSP is '0x00' Argument2 (8 Bit) about to be passed to DSP is '0x00' Uploading the DSP software task to the DSP, please wait...(100%) Waiting DSP to advertise himself as ready... Done! Sending first argument to DSP software... Done! Sending second argument to DSP software... Done! Telling DSP to start executing the DSP software... Done! Wait DSP software to indicate end of execution... Done! Reading error code register 1 from the DSP software... Done! Reading error code register 2 from the DSP software... Done! Status code 1 received from DSP software '0x0' Status code 2 received from DSP software '0x0' SRIO Test results: Status = Test Succeeded!
-----------------------------------------------------------------------Testing EMIFA on the FMC645... DSP Software about to be uploaded to DSP is 'fmc645_emifa_ack.hex' Argument1 (8 Bit) about to be passed to DSP is '0x00' Argument2 (8 Bit) about to be passed to DSP is '0x00' Uploading the DSP software task to the DSP, please wait...(100%) Waiting DSP to advertise himself as ready... Done! Sending first argument to DSP software... Done! Sending second argument to DSP software... Done! Telling DSP to start executing the DSP software... Done! Wait DSP software to indicate end of execution... Done! Reading error code register 1 from the DSP software... Done! Reading error code register 2 from the DSP software... Done! Status code 1 received from DSP software '0x4' Status code 2 received from DSP software '0x4'
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EMIFA Test results: Status = Test Succeeded!
-----------------------------------------------------------------------Testing DDR2 Memory on the FMC645 (512MBytes)... DSP Software about to be uploaded to DSP is 'fmc645_ddr2_ack.hex' Argument1 (8 Bit) about to be passed to DSP is '0x40' Argument2 (8 Bit) about to be passed to DSP is '0x00' Uploading the DSP software task to the DSP, please wait...(100%) Waiting DSP to advertise himself as ready... Done! Sending first argument to DSP software... Done! Sending second argument to DSP software... Done! Telling DSP to start executing the DSP software... Done! Wait DSP software to indicate end of execution... Done! Reading error code register 1 from the DSP software... Done! Reading error code register 2 from the DSP software... Done! Status code 1 received from DSP software '0x3' Status code 2 received from DSP software '0x0' DDR2 Test results: Status = Test Succeeded!
-----------------------------------------------------------------------Now that DSP is hot after DDR2 test, lets check board diagnostics, please wait...
1V25 on FMC645 OK (1.2V) 1V25 on FMC645 OK (1.2V) 2V5 3V3 0V9 on FMC645 OK (2.5V) on FMC645 OK (3.2V) on FMC645 OK (0.9V)
Diagnostics Test results : Test Succeeded!
-----------------------------------------------------------------------Testing EMAC on the FMC645... Before to continue further, please connect an ethernet cable between ML605 and your host... Configure your HOST TCPIP/V4 Settings as the following: IP ADDRESS : GATEWAY NETMASK : : 192.168.254.2 (Host address) 192.168.254.1 (DSP address) 255.255.255.0
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As soon this is done please press RETURN to continue Uploading the DSP software task to the DSP, please wait...(100%) Waiting 25 seconds to making sure the link is up... %%%%%%%%%%%%%%%%%%%%%%%%% Trying to connect to the DSP using TCP/IP: Done Writing 10 registers to the DSP address space (Via TCPIP), please wait... Reading 10 registers back from the DSP address space (Via TCPIP), please wait... 0x00000000 : 0x00000000 0x00000001 : 0x00000001 0x00000002 : 0x00000002 0x00000003 : 0x00000003 0x00000004 : 0x00000004 0x00000005 : 0x00000005 0x00000006 : 0x00000006 0x00000007 : 0x00000007 0x00000008 : 0x00000008 0x00000009 : 0x00000009 Comparing 10 registers read back from the Microblaze address space, please wait... 0x00000000 : 0x00000000 (OK) 0x00000001 : 0x00000001 (OK) 0x00000002 : 0x00000002 (OK) 0x00000003 : 0x00000003 (OK) 0x00000004 : 0x00000004 (OK) 0x00000005 : 0x00000005 (OK) 0x00000006 : 0x00000006 (OK) 0x00000007 : 0x00000007 (OK) 0x00000008 : 0x00000008 (OK) 0x00000009 : 0x00000009 (OK) Ethernet Test results : Test Succeeded! You should be able to ping 192.168.254.1 (the DSP)
-----------------------------------------------------------------------Finished, lets check board diagnostics again, please wait...
1V25 on FMC645 OK (1.2V) 1V25 on FMC645 OK (1.2V) 2V5 on FMC645 OK (2.5V)
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3V3 0V9
Diagnostics Test results : Test Succeeded! Finished
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4FM GETTING STARTED GUIDE

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4DSP APIs ............................................................................................................................... 18

4FM GUI Control application ................................................................................................ 19