Dept 34 LV 3 14909

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Text: Charles H. Roth, Jr.
Fundamentals of Logic Design

5th Edition 2004 THOMSON BROOKS/COLE
Unit 1
Introduction Number Systems and Conversion
Unit 01
Unit 1
z Introduction
Number Systems and Conversion

1.1
Digital Systems and Switching Circuits 1.2 Number Systems and Conversion 1.3 Binary Arithmetic 1.4 Representation of Negative Numbers
9Addition of 2s Complement Numbers 9Addition of 1s Complement Numbers
1.5
Binary Codes
Unit 01 3
Digital Systems and Switching Circuits

z Digital system The physical quantities or signals can assume only discrete values Greater accuracy z Analog system The physical quantities or signals may vary continuously over a specified range
Unit 01
Unit 01

z
Design of digital systems
System design 9 Breaking the overall system into subsystems 9 Specifying the characteristics of each subsystem 9 E.g. digital computer : memory units, arithmetic unit, I/O devices, control unit Logic design 9 Determining how to interconnect basic logic building blocks to perform a specific function 9 E.g. arithmetic unit : binary addition: logic gates, Flip-Flops, interconnections Circuit design 9 Specifying the interconnection of specific components such as resistors, diodes, and transistors to form a gate, flip-flop or other logic building block 9 E.g. Flip-Flop: resistors, diodes, transistors
Unit 01 6

z Many of subsystems of a digital system take the
form of a switching network
Switching Networks
9 Combinational Networks
No memory
9 Sequential Networks
Combinational Circuits + Memory
Unit 01

z Positional notation
Base 10:
Base 2:
Unit 01

z Base R:
Any positive integer R(R>1) can be chosen as the radix or base of a number system.
where
0 ai R 1 .
Unit 01 9

Example:
For bases greater than 10, more than 10 symbols are needed to represent the digits. In hexadecimal (base 16), A presents 1010, B presents 1110, C presents 1210, D presents 1310, E presents 1410, F presents 1510.
Unit 01 10

z Convert a decimal integer to base R
N = an R n 1 + an 1 R n 2 + L + a2 R1 + a1 = Q1 , remaider a0 R Q1 = an R n 2 + an 1 R n 3 + L + a3 R1 + a2 = Q2 , remaider a1 R Q2 = an R n 3 + an 1 R n 4 + L + a4 R1 + a3 = Q3 , remaider a2 R
This process is continued until we finally obtain an.

Unit 01 11

z Example : Convert 5310 to binary.
Unit 01
12

z Convert a decimal fraction to base R
This process is continued until we have obtained a sufficient number of digits.

Unit 01 13

z Example: Convert 0.62510 to binary.
Unit 01
14

z Example: Convert 0.710 to binary.
Unit 01
15

z Example: Convert 231.34 to base 7.
Unit 01
16

z Conversion from binary to hexadecimal
( and conversely)
One
hexadecimal digit corresponds to four binary digits (bits)
(306.D)16
= (0011 0000 0110 1101) 2 3 0 6 D
Unit 01
17
Binary Arithmetic
z Addition
Example: Add 1310 and 1110 in binary.
Unit 01
18
Binary Arithmetic
z Subtraction
Examples:
Unit 01
19
Binary Arithmetic
z Multiplication
Example:
Unit 01
20
Binary Arithmetic
z Division Example: 145/11=13 --- 2
Unit 01
21
Representation of Negative Numbers

z 2s Complement Number System Positive Number N 9 N is represented by a 0 followed by the magnitude.
Negative
Number N
9N is represented by its 2s complement, N*. If the word length is n,
N*=2n-N
Unit 01 22

z 1s Complement Number System Positive Number N 9 N is represented by a 0 followed by the magnitude
Negative Number N 9N is represented by its 1s complement N . If the word length is n,
N = (2 1) N
n
N*=2n-N=(2n-1-N)+1= N +1
Unit 01
23

z Sign and Magnitude Binary Numbers
Unit 01
24
Addition of 2s Complement Numbers

z Addition of n-bit signed binary numbers

Any carry from the sign position is ignored. n=4
Unit 01
25
A + B = A* + B = ( 2 n A) + B = 2 n + ( B A) 2 n ( B > A, carry) Throwing away the last carry is equivalent to subtractin g 2 n , so the result is ( B A).
Unit 01
26

A B = A* + B* = (2n A) + (2n B) = 2n + 2n ( A + B) 2n ( A + B 2n1 , carry) Discardingthe last carry yields 2n ( A + B) = ( A + B)* , which is the correct representa tion of ( A + B).
Unit 01
27

Example: Add -8 and +19 in 2s complement for a word length of n=8.
Unit 01
28

z Addition of n-bit signed binary numbers Add the last carry ( end-around carry) to the nbit sum in the position furthest to the right.
n=4
Unit 01
29
A + B = A + B = (2 n 1 A) + B = 2 n + ( B A) 1 2 n ( B > A, carry) The end - around carry is equivalent to subtracting 2 n and adding 1, so the result is ( B A).
Unit 01
30

A B = A + B = (2 n 1 A) + (2 n 1 B ) = 2 n + [2 n 1 ( A + B )] 1 2 n ( A + B < 2 n 1 , carry) Discarding the last carry yields 2 n 1 ( A + B) = ( A + B), which is the correct representation of ( A + B ).
Unit 01
31

Example: Add -11 and -20 in 1s complement for a word length of n=8.
Unit 01
32
Binary Codes
z
Weighted code w3-w2-w1-w0 weighted code a3a2a1a0 a3a2a1a0= w3a3+w2a2+w1a1+w0a0 Binary-Coded-Decimal, BCD; 8-4-2-1BCD code 0101=0.8+1.4+0.2+1.1=5 6-3-1-1 code 0101=0.6+1.3+0.1+1.1=4 z Excess-3 code 8-4-2-1 code + 0011 The code of i is the 1s complement of code 9-i z 2-out-of-5 code

Exactly 2 out of 5 bits are 1 Error-checking properties The codes for successive decimal digits differ in exactly on bit. American Standard Code for Information Interchange
z z
Gray code
ASCII code
Unit 01
33
Binary Codes
Unit 01
34
Binary Codes
Unit 01
35
Homework
z 1.1 (b); z 1.2 (b); z 1.4 (c); z 1.5 (b); z 1.7 (a), (c); z 1.9 z 1.16 (b); z 1.17 (b); z 1.24 z 1.25 (a);
Unit 01
36
Unit 2
Boolean Algebra
Unit 2
z Boolean Algebra 2.1 Introduction 2.2 Basic Operations 2.3 Boolean Expressions and Truth Tables 2.4 Basic Theorems 2.5 Commutative, Associative, and Distributive Laws 2.6 Simplification Theorems 2.7 Multiplying Out and Factoring 2.8 Demorgans Laws
Unit 02 2
Introduction
z George Boole developed Boolean algebra
in 1847 and used it to solve problems in mathematical logic. z Boolean Algebra A Boolean algebra is an algebra (B; . , + , ;0, 1) consisting of a set B (which contains at least two elements 0 and 1) together with three operations, the AND (Boolean product) operation . , the OR (Boolean sum) operation +, and the NOT (complement) operation , defined on the set, such that
Unit 02 3
Introduction

A0. Closure: For any x,y, and z of B, x.y, x+y, x are in B A1. Idempotent: x.x=x x+x=x A2. Commutative: x.y=y.x xy=yx A3. Associative: x. (y.z)=(x.y) .z=x . y . z x+ (y+z)=(x+y) +z=x + y + z A4. Absorptive: x . (x + y)=x x +(x . y)=x A5. Distributive: x . (y + z)=(x . y) +(x . z) x +(y . z)=(x + y) . (x + z) A6. Zero( null, smallest), 0 , and One( universal, largest), 1 , elements are in B x . 1=1 . x=x x + 0=0 + x=x A7. Complement For every x in B, there exists a unique x in B such that x . x=0, x + x=1
Unit 02 4
Introduction
z Example: Two-element Boolean Algebra
(Switching Algebra) B2=({0,1}; . ,+, ; 0,1) AND

.
OR + 0 1 0 0 1 1 1 1
Unit 02
NOT 0 1 1 0
0 1
0 0 0 1 0 1
Introduction
z Example: Four-element Boolean Algebra
B4=({0,a,b,1} ; . ,+, ; 0,1) AND OR . 0 a b 1 + 0 a b 0 0 a b 0 0 0 0 0 a a a 1 a 0 a 0 a b b 1 b b 0 0 b b 1 1 1 1 1 0 a b 1
1 1 1 1 1
NOT 0 1 a b b a 1 0
Unit 02
Introduction
z An element of a Boolean algebra B is
called a constant on B.
e.g. 0,a,b,1 in B4. z A symbol that may represent any one of
element of B is called a (Boolean) variable on B. e.g. x,y,z,
Unit 02
Introduction
z A Boolean expression over an algebra
system (B; . ,+, ; 0,1) is defined as follows:

1. 2. 3. 4.
Any element of B ( constant) is a Boolean expression. Any variable name is a Boolean expression. If e1 and e2 are Boolean expression, then e1, e2, e1+e2, e1.e2 are Boolean expressions. Any expression that can be constructed by a finite number of applications of the above rules, and only such a expression is a Boolean expression.
Unit 02
Introduction
z A function f(x1,x2,,xn),
f :B B
n
from Bn to B is called a Boolean function if it can be specified by a Boolean expression of n variables x1,x2,,xn . f(a,b,c)=abc+ab+bc z Each appearance of a variable or its complement in an expression is referred to as a literal. f(a,b,c)=abc+ab+bc has 3 variables, a,b, and c, 7 literals(a, b , c, a, b, b, c ).
Unit 02 9
Basic Operations
z The basic operations of Boolean algebra are
AND, OR, and NOT (complement, or inverse).

NOT (Complement)
0 = 1 1 = 0 X = 1 if X = 0 and X = 0 if X = 1
Inverter
Unit 02
10
Basic Operations
AND
Operation
9Omit the symbol ., A . B=AB
AND Gate
Unit 02
11
Basic Operations
OR
operation
OR Gate
Unit 02
12
Boolean Expressions and Truth Tables

z Order in which the operations are perform
ParenthesesComplentationANDOR z Circuits for expressions

AB + C
[ A(C + D )] + BE
Unit 02 13
Truth Table
z If an expression has n variables, the number of different
combinations of values of the variables is 2n. Therefore, a truth table for n-variable expression will have 2n rows. ( 2n ) z There are 2 functions of n variables.
Unit 02
14
Truth Table
z
AB + C = ( A + C )( B + C )
Unit 02
15
Basic Theorems
z
Unit 02
16
Basic Theorems
z
Unit 02
17
Basic Theorems
z Switching Circuits
Unit 02
18
Commutative, Associative, and Distributive Laws

z Commutative Laws z Associative Laws
z Distributive Laws
Unit 02
19
Multiple-Input Gates
z Associative Laws for AND and OR
operations.
(AB)C=A(BC)=ABC (A+B)+C=A+(B+C)=A+B+C
Unit 02
20
Proof of Boolean Theorems

z By Truth Table Example: X+YZ=(X+Y)(X+Z)
X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 YZ 0 0 0 1 0 0 0 1 X+YZ X+Y X+Z 0 0 0 1 1 1 1 1
Unit 02
(X+Y)(X+Z) 0 0 0 1 1 1 1 1
21
0 0 1 1 1 1 1 1
0 1 0 1 1 1 1 1
Proof of Boolean Theorems

z By basic laws: Example: X+YZ=(X+Y)(X+Z)
Unit 02
22
Simplification Theorems
z Useful Simplification Theorems
z Proof
Unit 02
23
Simplification Examples
z Example: Simplify Z =[A+ BC + D+ EF][A+ BC +(D+ EF)]
Sol:
Z = X = A + BC
z Example: Simplify
Z = ( AB + C )( BD + C E ) + ( AB + C )
Sol:
Let ( AB + C) = Y , BD + CE = X then Z = ( AB + C)(BD + CE) + ( AB + C) = Y X + Y = X + Y = BD + CE + ( AB + C)

Unit 02 24
Simplification Examples
z Example: Find the output Y of the following
circuit and design a simpler circuit having the same output.
Sol: Y = (AB + (AB + B))B + A

= (AB + B)B + A = ABB + B + A = B + A
The resulting circuit contains only one OR gate.
Unit 02
25
Multiplying Out and Factoring

z Sum-of-products (SOP)
An expression is said to be in sum-of-products form when all products are the products of only single variables.
AB + CDE + AC E , A + B + C + DE are in SOP form, ( A + B)CD + EF is not in SOP form.
z Product-of-sums (POS)
An expression is said to be in product-of-sums form when all sums are the sums of only single variables.
( A + B)(C + D + E )( A + C + E ) , ABC ( D + E ) are in POS form, (A + B)(C + D) + EF is not in POS form.
Unit 02
26

z Using the ordinary distributive law
X(Y+Z)=XY+XZ to multiply out an expression to obtain a sum-of-products form. z Using the second distributive law X+YZ=(X+Y)(X+Z) to factor an expression to obtain a product-of-sums form.
Unit 02 27

z Example: Multiply out (A+BC)(A+D+E).
Sol-1:
Multiply out the original expression completely and then eliminating redundant terms: (A+BC)(A+D+E)=A+AD+AE+ABC+BCD+BCE =A(1+D+E+BC)+BCD+BCE =A+BCD+BCE Use (X+Y)(X+Z)=X+YZ :
Sol-2:
(A+BC)(A+D+E)=A+BC(D+E)=A+BCD+BCE
Unit 02
28

z Example: Factor
A + BCD.
Sol:
A + BCD = ( A + B)( A + CD ) = ( A + B)( A + C )( A + D)
z Example: Factor AB + C D .
Sol:
AB + C D = ( AB + C )( AB + D) = ( A + C )( B + C )( A + D)( B + D)
z Example: Factor C D + C E + GH .
Sol:
C D + C E + GH = C (D + E ) + GH = (C + GH)(D + E + GH) = (C + G)(C + H)(D + E + G)(D + E + H)

Unit 02 29
DeMorgans Laws
z DeMorgans laws
( X + Y ) = X Y ( XY ) = X + Y
z Proof using a truth table
Unit 02
30
DeMorgans Laws
z n variables DeMorgans Laws
X3 ... X n ( X 1 + X 2 + X 3 + ... + X n ) = X 1X 2 + X3 + ... + X n ( X 1 X 2 X 3 ... X n ) = X 1 + X 2

z One-step rule for applying DeMorgans
Laws , x2 , L , xn ,1,0,,+) [ f ( x1 , x2 , L , xn ,0,1,+,)] = f ( x1

x x + 0 1 x x + 1 0
Unit 02
31
DeMorgans Laws
z Example: Find the complement of
( AB + C ) D + E
Sol-1:
Sol-2:
[( AB + C ) D + E ] = [( A B + C ) D + E ] = (( A + B ) C ) + D) E
Unit 02 32
Shannons Theorem
z Shannons Theorem
, x2 , L , xn ,1,0,,+) [ f ( x1 , x2 , L , xn ,0,1,+,)] = f ( x1
Proof:
f ( x1 , x2 , L, xn ,0,1,+,) = f1 ( x1 , x2 , L, xn ,0,1,+,) + f 2 ( x1 , x2 , L, xn ,0,1,+,) or f ( x1 , x2 , L, xn ,0,1,+,) = f1 ( x1 , x2 , L, xn ,0,1,+,) f 2 ( x1 , x2 , L, xn ,0,1,+,) Then [ f ( x1 , x2 , L, xn ,0,1,+,)] = [ f1 ( x1 , x2 , L, xn ,0,1,+,)] [ f 2 ( x1 , x2 , L, xn ,0,1,+,)] or [ f ( x1 , x2 , L, xn ,0,1,+,)] = [ f1 ( x1 , x2 , L, xn ,0,1,+,)] + [ f 2 ( x1 , x2 , L, xn ,0,1,+,)] Repeat the same argument for f1 and f 2 , and so forth, until DeMorgan' s Laws are applied to every variable of each term of f.
Unit 02
33
Duality
z Given a Boolean expression, the dual is
formed by replacing AND with OR, OR with AND, 0 with 1, 1 with 0. D [ f ( x , x , L , x , 0 , 1 , + , )] = f ( x1 , x2 , L , xn ,1,0,,+ ) z Dual 1 2 n z The dual of an expression may be found by complementing the entire expression and then complement each individual variable. z Positive and Negative Logic.
Unit 02 34
Duality
z Example: Find the dual of
F = a b + c + 1 d (0 + e)
Sol:
F = a b + c + 1 d ( 0 + e ) F = (a + b) c [0 + d + (1 e)] = (a + b)c[0 + d + (1 e)] FD = (a + b)c[0 + d + (1 e)]
Unit 02
35
Duality
z Theorem: Given that two Boolean
expressions which contains the same variables are equal, the duals are equal.
F = G F D = G D.
Proof: F = G F = G.
If we replace each variable in F and G by its complement, this will not destroy the equality since this is equivalent to substituting one variable for another on both sides of the equation. z If a theorem is true, so is its dual.
Unit 02 36
Duality
z Example: F = G F D = G D .
F=X(Y+Z), G=XY+XZ, F=G FD=X+YZ, GD=(X+Y)(X+Z), FD= GD

F = G F = G . F = X(Y + Z), F D = X + Y Z, F = X + Y Z , G = XY + XZ G = (X + Y)(X + Z) G = (X + Y )( X + Z )
D
F = G X + Y Z = (X + Y )( X + Z ) Complement each variable , X + Y Z = (X + Y)(X + Z) Hence , F D = G D .

Unit 02 37
Homework
z 2-1 z 2-3 z 2-4 z 2-7 z 2-10 z 2-13 z 2-15
Unit 02
38
Unit 3
Boolean Algebra (Continued)
Multiplying Out and Factoring Expressions

z Multiplying out
X (Y + Z ) = XY + XZ ( X + Y )( X + Z ) = X + YZ ( X + Y )( X + Z ) = XZ + X Y z Factoring XY + XZ = X (Y + Z )
X + YZ = ( X + Y )( X + Z ) XZ + X Y = ( X + Y )( X + Z )
Unit 03

z Example: Prove that
( X + Y )( X + Z ) = X + YZ
= X + XZ + XY + YZ = X + XY + YZ = X + YZ
Proof: (1) (2)
( X + Y )( X + Z ) = XX + XZ + YX + YZ
(a) X = 0, ( 0 + Y)( 0 + Z) = YZ (b)X = 1, ( 1 + Y)(1 + Z) = 1 1 = 1
0 + YZ = YZ 1 + YZ = 1
z Example: Prove that
( X + Y )( X + Z ) = XZ + X Y
Proof:
(X + Y)(X + Z) = XX + XZ + YX + YZ = 0 + XZ + X Y + YZ = XZ + X Y + (X + X )YZ = XZ + X Y + XYZ + X YZ = XZ( 1 + Y) + X Y( 1 + Z) = XZ + X Y

Unit 03 3

z Example: Multiplying out (POS => SOP) ( A + B + C)(A + B + D)(A + B + E)(A + D + E)(A + C)
Sol:
Unit 03

z Example: Factoring (SOP => POS) AC+ ABD + ABE+ ACDE
Sol:
Unit 03
Exclusive-OR and Equivalence Operations

z Exclusive-OR:
0 0 = 0 0 1 = 1 1 0 = 1 11 = 0
z Truth table and gate for X Y
X Y =1 if and only if X=1 or Y=1 and X and Y are not both 1.

Unit 03 6

z X Y = X Y + XY z Theorems apply to exclusive OR:
Unit 03

z Proof of the distributive law X (Y Z ) = XY XZ
Proof:
Unit 03

z The equivalence operation( ) is defined by
z The truth table for X Y is
(X Y) =1 if and only if X = Y .
Unit 03 9

z z
( X Y ) = XY + X Y
Equivalence is the complement of exclusive-OR:
( X Y ) = ( X Y + XY ) = ( X + Y )( X + Y ) = XY + X Y = ( X Y )
Alternate symbol for the equivalence gate
The equivalence gate is also called an exclusive-NOR gate.
Unit 03
10

z Example:
Unit 03
11
The Consensus Theorem

z The consensus theorem:
XY + X Z + YZ = XY + X Z
Proof:
z The dual form ( X + Y )( X + Z )(Y + Z ) = ( X + Y )( X + Z )

Unit 03 12

z Example: Simplify
AC D + ABD + BCD + ABC + ACD Sol-1: ACD + ABD + BCD + ABC + ACD
(BD)(BC) = BCD = AC D + A BD + ABC + ACD 4 terms.
Sol-2:
AC D + ABD + BC D + ABC + AC D O NO N (AD)(BD) = ABD (BC)(AC) = ABC = AC D + BCD + ACD 3 terms.
Unit 03
13

z Example: Simplify
F = ABCD + BCDE + AB + BCE
Sol: Find consensus terms,
ABCD + BCDE = ABCD + BCDE + ACDE ABCD + A B = ABCD + AB + (BCD)B + (ACD)A BCD E + BC E = BCDE + BCE + 0 + 0 A B + BCE = AB + BCE + ACE
Add the consensus term ACDE to F.
F = AB + BCE + ACDE
Unit 03 14
Algebraic Simplification of Switching Expressions

z 1.Combining terms:
Use the theorem XY + XY = X to combine two terms.

z 2.Eliminating terms:
Use X + XY = X to eliminate redundant terms; then try to apply the consensus theorem XY + X Z + YZ = XY + X Z to eliminate any consensus terms.
Unit 03 15

z 3.Eliminating literals:
Use the theorem X + X Y = X + Y to eliminate redundant literals. z 4.Adding redundant terms: Adding xx , multiply by ( x + x) , adding yz to xy + xz , or adding xy to x .
y = y + xx y = y ( x + x) = yx + yx xy + xz = xy + xz + yz x = x + xy
Unit 03
16

z Example: Simplify
WX + XY + X Z + WY Z
Sol:
Unit 03
17

z Example : Simplify
ABCD + ABCD + ABD+ ABCD + ABCD+ ACD + BCD
Sol:
Unit 03
18
Proving Validity of an Equation

z
Determine if an equation is valid:
1. Construct a truth table and evaluate both side s of the equation for all combinations of the values of the variables. 2. Manipulate one side of the equation by applying various theorems until it is identical with the other side. 3. Reduce both sides of the equation independently to the same expression. 4. It is permission to perform the same operation on both sides of the equation provided the operation is reversible. ( complement is reversible, multiplication and addition are not reversible) x+y=x+z does not imply y=z ( e.g. x=1,y=0, z=1) xy=xz does not imply y=z ( e.g. x=0, y=0, z=1)
Unit 03
19

z Example: Show that
ABD + BCD + ABC + ABD = BC D + AD + ABC Sol-1:
Unit 03
20

ABD + BCD + ABC + ABD = BC D + AD + ABC Sol-2: Let F ( A, B, C , D) = ABD + BCD + ABC + ABD
1
F2 ( A, B, C , D) = BC D + AD + ABC (1) A = 0, F1 (0, B, C , D) = BD + BCD = B ( D + CD ) = B( D + C ) = BD + BC F2 (0, B, C , D) = BC D + BC = B(C D + C ) = B( D + C ) = BD + BC F1 (0, B, C , D) = F2 (0, B, C , D) (2) A = 1, F1 (1, B, C , D) = BCD + BC + BD = B(CD + C ) + BD = B( D + C ) + BD = BD + BC + BD = D + BC F2 (1, B, C , D) = BC D + D = D + BC F1 (1, B, C , D) = F2 (1, B, C , D) F1 ( A, B, C , D) = F2 ( A, B, C , D)
Unit 03
21

ABC D + ( A + BC )( A + C D) + BC D + ABC = ABCD + AC D + ABD + ABCD + BC D
Sol: First, we will reduce the left side:
Unit 03
22

Sol (cont.): Now we will reduce the right side:
Because both sides of the original equation were independently reduced to the same expression, the original equation is valid.
Unit 03
23
Homework
z 3.6 z 3.7 z 3.8 z 3.10 z 3.11 z 3.19 z 3.22 (a),(d),(g) z 3.25 (b),(e) z 3.28 (a)
Unit 03
24
Unit 4
Application of Boolean Algebra Minterm and Maxterm Expansions
Unit 4
z Application of Boolean Algebra
Minterm and Maxterm Expansions

1. Conversion of English Sentences to Boolean Equations 2. Combinational Logic Design Using truth Table 3. Minterm and Maxterm Expansions 4. General Minterm and Maxterm Expansions 5. Incompletely Specified Functions 6. Examples of Truth Table Construction 7. Design of Binary Adders and Subtracters
Unit 04 2
Conversion of Sentences to Boolean Equation

z The three main steps in designing a single-
output combinational switching circuit are:

1. Find a switching function which specifies the
desired behavior of the circuit. 2. Find a simplified algebraic expression for the function. 3. Realize the simplified function using available logic eldments.
Unit 04 3

z Translate sentences into Boolean
equation
Example:
Mary watches TV if it is Monday night and she has finished her homework.
Define two-valued variables:
F=1 if Mary watches TV is true; otherwise, F=0. A=1 if it is Monday night is true; otherwise A=0. B=1 if she has finished her homework is true; otherwise B=0.
F=A.B, F is true if A and B are both true.

Unit 04 4
Example: An alarm circuit is to be designed which operates as follows: The alarm will ring if and only if the alarm Z A switch is on and the door is not closed or it is B after 6 P.M. and the window is not closed. C D
Z = AB + CD
Z = A( B + CD)
Unit 04 5
Combinational Logic Design Using a Truth Table

Example: Design a switching circuit with three
inputs A, B, and C and one output f. The input A,B, and C represent the first, second, and third bits, respectively, for a binary number N. f=1 if N 0112 and f=0 if N < 0112 . Sol-1:
Unit 04

Sol-1 (cont.): Derive an algebraic expression for
f from the truth table by using the combinations of values of A,B, and C for which f=1. f = ABC + ABC + ABC + ABC + ABC = ABC + AB + AB = ABC + A = A + BC The circuit is
Unit 04
Sol-2: First write f as a sum of products, and then complement the result. f is 1 for input combinations ABC=000, 001, 010, so
f = ABC + ABC + ABC

f = ( f ) = ( ABC + ABC + ABC ) = ( A + B + C )( A + B + C )( A + B + C ) ( Three 3 - input OR gates and one 3 - input AND gate) = ( A + B )( A + B + C ) [Two OR gates and one AND gate] = A + BC
Unit 04

z Minterm
A minterm of n variables is a product of n literals in which each variable appears exactly once in either true or complement form, but not both. z Maxterm A maxterm of n variables is a sum of n literals in which each variable appears exactly once in either true or complement form, but not both.
Unit 04

z Minterm and Maxterm for three variables
Unit 04
10

z Minterm expansion or
Standard sum of products

When a function is written as a sum of minterms, this is referred to as a minterm expansion or standard sum of products.
z Examples: f ( A, B, C ) = ABC + ABC + ABC + ABC + ABC
f ( A, B, C ) = m3 + m4 + m5 + m6 + m7 f ( A, B, C ) = m(3,4,5,6,7)
Unit 04 11

z Maxterm expansion or
Standard product of sums

When a function is written as a product of maxterms , this is referred to as a maxterm expansion or standard product of sums.
z Example: f ( A, B, C ) = ( A + B + C )( A + B + C )( A + B + C )
f ( A, B, C ) = M 0 M 1M 2 f ( A, B, C ) = M (0,1,2)
Unit 04 12

z Complement of a function f .
Example:
f ( A, B, C ) = m3 + m4 + m5 + m6 + m7 f = (m3 + m4 + m5 + m6 + m7 ) m4 m5 m6 m7 = M 3M 4 M 5M 6 M 7 = m3 f ( A, B, C ) = M 0 M 1M 2 + M 1 + M 2 = m0 + m1 + m2 f = ( M 0 M 1M 2 ) = M 0
Unit 04
13

z Converting a general switching
expression to a mniterm or maxterm expansion

Using a truth table Algebraically : Introduce the missing variable
in each term by applying X + X = 1 (minterm expansion) or applying XX = 0 (maxterm expansion).

Unit 04 14

z Example: Find the minterm expansion of f (a, b, c, d ) = a(b + d ) + acd
Sol:
Unit 04
15

z Example: Find the maxterm expansion of f (a, b, c, d ) = a(b + d ) + acd
Sol:
Unit 04
16
General Minterm and Maxterm Expansions

z General Truth Table for Three Variables
There are 256 different functions of three variables. n 2 There are 2 different functions of n variables.
Unit 04 17

z The minterm expansion of a general function of 3 variables
If
F = a0 m0 + a1m1 + a2 m2 + ... + a7 m7 = ai mi i =0 ai = 1 , minterm mi is present in the expansion; if ai = 0 ,
the corresponding minterm is not present. z The maxterm expansion of a general function of 3 variables
F = (a0 + M0 )(a1 + M1)(a2 + M2 )...(a7 + M7 ) =

If
ai = 1, ai + Mi =1, ai = 0
i=0
(ai
+ Mi )
maxterm
Mi
is not present in the
expansion; if present.
, the corresponding maxterm
Mi
is
Unit 04
18

z Minterm expansion for
i =0
F 7 7 F = [ (ai + M i )] = aiM i =
i =0
i =0
aimi
F are present
Note that all minterms which are not present in in F .

z Maxterm expansion for
7 7
F
7 i=0
F = [ ai mi ] = (ai + mi) = (ai + Mi )

i=0 i=0
Note that all maxterms which are not present in F are present in F .
Unit 04
19

z General Minterm and Maxterm Expansions for n
variables
F=
2 n 1 i =0
2
ai mi =
n
2 n 1 i =0
(ai + M i )
= ( a i + M
i=0 2
n
F =
i= 0
a i m
Unit 04
20

z Given minterm expansions for two functions
f1 =
2 n 1 i=0
am
i
f2 =
2 n 1 j =0
2 n 1 j =0
bjm j
the product is
f1 f 2 = [
=
2 n 1 i =0 2 1
n
ai mi ][
bjm j ] =
2 n 1 2 n 1
i =0
aibi mi
m mi m j = i 0
i =0 j =0 i = j,
aib j mi m j
i j.
the sum is
f1 + f 2 = (ai + bi )mi
i =0 2 n 1
Unit 04
21

z Example: Find the product and the sum of
f1 = m(0,2,3,5,9,11) and f 2 = m(0,3,9,11,13,14) .
Sol: f1 f 2 = m(0,3,9,11)
f1 + f 2 = m(0,2,3,5,9,11,13,14).
Unit 04
22
Using Minterm Expansion to Prove Validity of An Equation

AC + BC + AB = AB + BC + AC
Proof:
AC + BC + AB = A(B + B)C + ( A + A)BC + AB(C + C) = ABC + ABC + ABC + ABC + ABC + ABC 3 1 4 0 7 6 = m(0,1,3,4,6,7) AB + BC + AC = AB(C + C) + ( A + A)BC + A(B + B)C = ABC + ABC + ABC + ABC + ABC + ABC 1 0 7 4 6 3 = m(0,1,3,4,6,7) AC + BC + AB = AB + BC + AC
Unit 04 23

z Conversion between minterm and maxterm
expansions of F and F
GIVEN FORM Minterm Expansion of F Minterm Expansion of F Maxterm Expansion of F -------------Minterm nos. are those nos. not on the maxterm list of F
DESIRED FORM Maxterm Expansion of F

Maxterm nos. are those nos. not on the minterm list of F
Minterm Expansion of F
List minterms not present in F
Maxterm Expansion of F
Maxterm nos. are the same as minterm nos. of F List maxterms not present in F
--------------
Minterm nos. are the same as maxterm nos. of F
Unit 04
24

z Conversion between minterm and maxterm
expansions of F and F
f = m(3,4,5,6,7)
GIVEN FORM
DESIRED FORM Maxterm Expansion of F

M (0,1,2)
m(0,1,2)
Maxterm Expansion of F
M (3,4,5,6,7)
--------------
f = M (0,1,2)
m(3,4,5,6,7)
--------------
m(0,1,2)
M (3,4,5,6,7)
Unit 04
25
Shannons Expansion Theorems

z Shannons expansion theorems:
(a) f ( x1 , x2 , L , xn ) = x1 f (1, x2 , L , xn ) + x1' f (0, x2 , L , xn ) (b) f ( x1 , x2 , L , xn ) = [ x1 + f (0, x2 , L , xn )] [ x1' + f (1, x2 , L , xn )]
z Proof:
(a) x1 = 1, f (1, x2 , L , xn ) = 1 f (1, x2 , L , xn ) + 0 f (0, x2 , L , xn ) x1 = 0, f (0, x2 , L , xn ) = 0 f (1, x2 , L , xn ) + 1 f (0, x2 , L , xn ) (b) x1 = 1, f (1, x2 , L , xn ) = [1 + f (0, x2 , L, xn )] [0 + f (1, x2 , L , xn )] = f (1, x2 , L , xn ) x1 = 0, f (0, x2 , L , xn ) = [0 + f (0, x2 , L , xn )] [1 + f (1, x2 , L, xn )] = f (0, x2 , L , xn )
Unit 04 26

z Example:
f (a, b, c) = (ab)c + a(b + c) f (a, b, c) = a[(1b)c +1 (b + c)]+ a[(0b)c + 0 (b + c)] = a(bc +b + c) + a(c) f (a, b, c) =[a + (0b)c + 0 (b + c)][a + (1 b)c +1 (b + c)] = (a + c)(a +bc +b + c)
Unit 04
27

( a ) f ( x1 , x2 , L , xn ) = x1 f (1, x2 , L , xn ) + x1' f (0, x2 , L , xn ) =
' x1[ x2 f (1,1, x3 , L , xn ) + x2 f (1,0, x3 , L , xn )] ' + x1' [ x2 f (0,1, x3 , L , xn ) + x2 f (0,0, x3 , L , xn )]
= x x f (0,0, x3 , L , xn )
' ' 1 2
x1 x2 0 0 0 0 1 1
xn f 0 1 1
f(1,1,,1) f(0,0,,0)
+ x1' x2 f (0,1, x3 , L , xn )
' + x1 x2 f (1,0, x3 , L , xn )
+ x1 x2 f (1,1, x3 , L , xn ) =L = x x Lx
' ' 1 2 ' ' n 1 n
x f (0,0, L ,0,0)
f(0,0,,1)
' ' + x1' x2 L xn 1 x n f ( 0,0, L ,0,1) ' ' + x1' x2 L xn 1 xn f (0,0, L ,1,0)
+L + x1 x2 L xn 1 xn f (1,1, L ,1,1)
Unit 04
28

(b) f ( x1 , x2 , L , xn ) = [ x1 + f (0, x2 , L , xn )] [ x1' + f (1, x2 , L , xn )]
' = [ x1 + x2 + f (0,0, x3 , L , xn )][ x1 + x2 + f (0,1, x3 , L , xn )] ' + [ x1' + x2 + f (1,0, x3 , L , xn )][ x1' + x2 + f (1,1, x3 , L , xn )]
=L = [( x1 + x2 + L + xn 1 + xn ) + f (0,0, L ,0,0)]
' ) + f (0,0, L ,0,1)] [( x1 + x2 + L + xn 1 + xn
x1 x2 0 0 0 0 1 1
xn f 0 1 1
f(1,1,,1) f(0,0,,0)
L
' ' ' [( x1' + x2 + L + xn 1 + xn ) + f (1,1, L ,1,1)]
f(0,0,,1)
Unit 04
29
Incompletely Specified Functions

z Incompletely Specified Function
A function contains dont care terms. z
Example 1: The output of subcircuit N1 drives the input of the subcircuit N2. Assume that there are no combinations of values for w,x,y, and z which cause A,B, and C to assume values of 001 or 110..
The function F is incompletely specified.

Unit 04 30
Incompletely Specified Functions

z Example 1(cont.):
F = m(0,3,7) + d (1,6) F = M (2,4,5) D (1,6)
1. Assign 0 to both Xs F = A B C + A BC + ABC = A B C + BC 2. Assign 1 to the first X and 0 to the second --- simplest solution
F = ABC + ABC + ABC + ABC = AB + BC

3. Assign 0 to the first X and 1 to the second
F = ABC + ABC + ABC + ABC = ABC + ABC + AB
4. Assign 1 to both Xs
F = ABC + ABC + ABC+ ABC + ABC= AB + BC+ AB

Unit 04 31
Examples of Truth Table Construction

z Example 2: Design an adder which adds two
2-bit binary numbers to give a 3-bit binary sum. The circuit has 4 inputs and 3 outputs :
Unit 04
32

z Example 2(cont.):
The output functions are :

X ( A, B, C , D) = m(7,10,11,13,14,15) Y ( A, B, C , D ) = m(2,3,5,6,8,9,12,15) Z ( A, b, C , D ) = m(1,3,4,6,9,11,12,14)
Unit 04
33

z Example 3: Design an error detector for 6-3-1-1 binary-codeddecimal digits. The output (F) is to be 1 iff the four input (A,B,C,D) represent an invalid code combination.
Sol:
Unit 04
34

z Example 3(cont.):
The output function is
The realization using AND and OR gates is
Unit 04
35

z Example 4: Design the circuit so that the
output (Z) is 1 iff the decimal number represented by the inputs (A,B,C,D) is exactly divisible by 3. Assume that only valid 8-4-2-1 BCD digits occur as inputs.
Sol: The digits 0,3,6,9 are exactly divisible

by 3, so Z=1 for ABCD=000,0011,0110, and 1001.
Unit 04
36

z Example 4(cont.):
The truth table
The output function

Z = m(0,3,6,9) + d (10,11,12,13,14,15)
Unit 04
37
Design of Binary Adders and Subtracters

z Half Adder:
Unit 04
38

z Full Adder:
Unit 04
39

z
The logic equation for the full adder:
Unit 04
40

z
The logic circuit of full adder:
Unit 04
41

z 4-Bit Parallel Adder
Adds two 4-bit unsigned binary numbers
Unit 04
42

z 4-Bit Parallel Adder
Unit 04
43

z Binary Subtracter Using Full Adders:
Subtraction of binary numbers is moat easily accomplished by adding the complement of the number to be subtracted.
Unit 04
44

z Full Subtracter
xi=0 yi=1bi=1
Unit 04
45

z Parallel Subtracter : Direct subtraction can be accomplished by employing a subtracter.
Unit 04
46
Homework
z1 z2 z5 z7 z9 z 20 z 23 z 25 (c),(d)
Unit 04
47
Unit 5
Karnaugh Maps
Unit 5
z Karnaugh Maps 5.1 Minimum Forms of Switching Functions 5.2 Two- and Three- Variable Karnaugh Maps 5.3 Four-Variable Karnaugh Maps 5.4 Determination of Minimum Expressions Using Essential Prime Implicants 5.5 Five-Variable Karnaugh Maps 5.6 Other Uses of Karnaugh Maps 5.7 Other Form of Karnaugh Maps
Unit 05 2
Introduction
z Simplification by using the algebraic
techniques
1. The procedures are difficult to apply in systematic way. 2. It is difficult to tell when you have arrived at a minimum solution.
z Karnaugh Map (K-Map) An useful tool for simplifying and manipulation switching functions of three or four variables. Faster and Easier
Unit 05
Minimum Forms of Switching Functions

z Sum-of-products expression
- Two-level AND-OR gate network Example:
z Product-of-sums expression
- Two-level OR-AND gate network Example:
Unit 05

z Minimum sum-of products A sum of product terms Has a minimum number of terms (AND gates) Has a minimum number of literals (number of gate inputs) Minimum two-level AND-OR network z Minimum Product-of-sums A product of sum terms Has a minimum number of factors ( OR gates) Has a minimum number of literals (number of gate inputs) Minimum two-level OR-AND network
Unit 05

z Example: Find the minimum sum-ofproducts of F (a, b, c) = m(0,1,2,5,6,7) .
Sol:
3 terms, 6 literals
Unit 05 6

z Example: Find the minimum product-of-sums
of
( A + B + C + D)( A + B + C + D)( A + B + C + D)( A + B + C + D)( A + B + C + D)( A + B + C + D)
Sol:
Unit 05
Two- and Three- Variable Karnaugh Maps

z 2- variable Karnaugh Maps
Example:
Unit 05

z 2- variable Karnaugh Maps
Example:
Unit 05

z 3-variable Karnaugh Maps
Unit 05
10

z Adjacent Cells
Two cell which differ in just one variable are said to be adjacent. 2k adjacent calls can be combined.
Unit 05
11

z
If F is given as a minterm (maxterm) expansion, the map by placing 1s(0s) in the squares which correspond to the minterm ( maxterm) and then by filling in the remaining squares with 0s(1s).
Example: F(a,b, c) = m1 + m3 + m5 = M0M2M4M6M7
Unit 05
12

z If a function is given in algebraic form,
plot its Karnaugh Map. Example: f (a, b, c) = abc + bc + a
Unit 05
13

z Simplify a function using Karnaugh Map
Example: F = m(1,3,5)
Unit 05
14

z Simplify a function using Karnaugh Map
Example: Simplify the complement of

F = m(1,3,5)
Unit 05
15

z Illustrate the Consensus Theorem
Example:
xy + xz + yz = xy + xz
Unit 05
16

z Minimum sum-of-products is not unique. f = m(0,1,2,5,6,7) Example:
Unit 05
17
Four- Variable Karnaugh Maps

z 4-Variable Karnaugh Maps
Unit 05
18

z Example: f (a, b, c, d ) = acd + ab + d
Unit 05
19

z Example: Simplify f1 = m(1,3,4,5,10,12,13)
f 2 = m(0,2,3,5,6,7,8,10,11,14,15)
Unit 05
20

z Simplify a function with dont care Example: f = m(1,3,5,7,9) + d (6,12,13)
All the 1s must be covered, but the Xs are only used if they will simplify the resulting expression.
Unit 05
21

z Find a minimum product-of-sums
1. Find a minimum sum-of-products for F 2. Complement F using DeMorgans Theorem Example: Find a minimum product-of-sums for
f = xz + wyz + wyz + xy
f = yz + wxz + wxy f = ( f ) = ( y + z)(w + x + z)(w+ x + y)
Unit 05
22
Determination of Minimum Expansions Using Essential Prime Implicants

z Cover: A switching function f(x1,x2,,xn) is said to
cover another function g(x1,x2,,xn), if f assumes the value 1 whenever g does. z Implicant : Given a function F of n variables, a product term P is an implicant of F iff for every combination of values of the n variables for which P=1 , F is also equal 1.That is, P=1 implies F=1. z Prime Implicant: A prime implicant of a function F is a product term implicart which is no longer an implicant if any literal is deleted from it. z Essential Prime Implicant: If a minterm is covered by only one prime implicant, then that prime implicant is called an essential prime implicant.
Unit 05 23

z On a Karnaugh Map
Any single 1 or any group of 1s (2k 1s, k=0,1,2,) which can be combined together on a map of the function F represents a product term which is called an implicant of F. A product term implicant is called a prime implicant if it cannot be combined with another term to eliminate a variable. If a minterm is covered by only one prime implicant, then that prime implicant is called an essential prime implicant.
Unit 05
24

z Examples
f=wx+yz, g=wxy g=1 (w=1,x=1,y=0) implies f=1.1+0.z=1, f covers g. g is a product term, g is an implicant of f. g is not a prime implicant. The literal y is deleted from wxy, the resulting term wx is also an implicant of f. h=wx is a prime implicant. The deletion of any literal (w or x) results a new product (x or w) which is not covered by f. [w=1 does not imply f=1 (w=1,x=0,y=0,z=0 imply f=0)]
Unit 05
25

z Example:
Unit 05
26

z
The minimum sum-of-products expression for a function consists of some (but not necessarily all) of the prime implicants of a function. z A sum-of-products expression consisting a term which is not a prime implicant cannot be minimum. z The essential prime implicant must be included in the minimum sum-of-products. z In order to find the minimum sum-of-products from a map, we must find a minimum number of prime implicants which cover all of the 1s on the map.
Unit 05
27

z Example:
Unit 05
28

z Example:
Essential prime implicants:
BD, BC , AC
Unit 05
29

z Procedure to Find a Minimum Sum of
Products Using a Karnaugh Map
1.Choose a minterm (a 1) which has not yet been covered. 2.Find all 1s and Xs adjacent to that minterm. 3. If a single term covers the minterm and all of the adjacent 1s and Xs, then that term is an essential prime implicant, so select that term. 4. Repeat steps 1,2, and 3 until all essential prime implicants have been chosen. 5. Find a minimum set of prime implicants which cover the remaining 1s on the map. If there is more than one such set, choose a set with a minimum number of literals.
Unit 05
30

z Example: Simplify the function
f ( A, B, C , D) = m(0,1,2,4,5,7,11,15).
= A C + A B D + ACD
A BD + or BCD

31
Unit 05

f ( A, B, C , D) = m(4,5,6,8,9,10,13) + d (0,7,15)
f = A B + A B D + A C D essential prime implicants
Unit 05
32

z Notes on the simplification of a function Some functions have no essential prime implicants.
Unit 05
33

z Notes on the simplification of a function To find a minimum sum-of-products expression, all essential prime implicants must selected FIRST.
Unit 05
34
5-Variable Karnaugh Maps

z 5-variable Karnaugh Map
Unit 05
35

z Example : Simplify the function
F( A, B, C, D, E) = m(0,1,4,5,13,15,20,21,22,23,24,26,28,30,31)
Unit 05
36

F ( A, B, C, D, E ) = m(0,1,3,8,9,14,15,16,17,19,25,27,31)
Unit 05
37

F ( A, B, C, D, E ) = m(0,1,3,8,9,14,15,16,17,19,25,27,31)
Unit 05
38
Other Forms of Karnaugh Maps

z Veitech diagram:
Unit 05
39

z Other forms of 5-Variable Karnaugh Maps
f ( x1 , x2 , x3 , x4 , x5 ) = x1' f (0, x2 , x3 , x4 , x5 ) + x1 f (1, x2 , x3 , x4 , x5 ) = x1' g 0 ( x2 , x3 , x4 , x5 ) + x1 g1 ( x2 , x3 , x4 , x5 )
Unit 05
40

Unit 05
41

F ( A, B, C , D, E ) = m(0,1,4,5,13,15,20,21,22,23,24,26,28,30,31)
Unit 05
42

F ( A, B, C , D, E ) = m(0,1,3,8,9,14,15,16,17,19,25,27,31)
Unit 05
43

Unit 05
44

Unit 05
45

Unit 05
46
Homework
z1 z2 z4 z5 z 7 (b),(d) z 10 (b) z 12 z 19 z 21 (b) z 27
Unit 05
47
Unit 6
Quine-McCluskey Method (-)
Quine-McCluskey Method
z Quine-McCluskey Mathod 6.1 Determination of Prime Implicants 6.2 The Prime Implicant Chart 6.3 Petricks Method() 6.4 Simplification of Incompletely Specified Functions 6.5 Simplification Using Map-Entered Variables 6.6 Conclusions
Unit 06 2
z Cover: A switching function f(x1,x2,,xn) is said to
cover another function g(x1,x2,,xn), if f assumes the value 1 whenever g does. z Implicant : Given a function F of n variables, a product term P is an implicant of F iff for every combination of values of the n variables for which P=1 , F is also equal 1.That is, P=1 implies F=1. z Prime Implicant: A prime implicant of a function F is a product term implicart which is no longer an implicant if any literal is deleted from it. z Essential Prime Implicant: If a minterm is covered by only one prime implicant, then that prime implicant is called an essential prime implicant.
Unit 06 3
z On a Karnaugh Map
Any single 1 or any group of 1s (2k 1s, k=0,1,2,) which can be combined together on a map of the function F represents a product term which is called an implicant of F. A product term implicant is called a prime implicant if it cannot be combined with another term to eliminate a variable. If a minterm is covered by only one prime implicant, then that prime implicant is called an essential prime implicant.
Unit 06
z A systematic simplification procedure z Input: minterm expansion
Output: a minimum sum of products Method:

1. Generate all prime implicants Eliminate as many literals as possible from each term by systematically applying the theorem XY+XY=X 2. Find the minimum solution Use a prime implicant chart to select a minimum set of prime implicants which contain a minimum number of literals.
Unit 06 5
z Example: F(a,b,c)=abc+abc+abc+abc
All Implicants: abc,abc,abc,abc ab,bc,ac Prime Implicants: ab,bc,ac Essential Prime Implicants: bc,ac Minimum sum of products: F(a,b,c)=bc+ac
Unit 06 6
z Quine-McCluskey Method: 1. Find all of the prime implicants of the function. 2. Construct the prime implicant table and find the essential prime implicants of the function. 3. Include the essential prime implicants in the minimal sum.
Unit 06
z Quine-McCluskey Method: 4. Manipulate the prime implicant table. 94-1. Delete all essential prime implicant from the prime implicant table, 94-2. Determine and delete the dominated rows and dominating columns in the table, 94-3. Find the (secondary) essential implicants. 5. Repeat Steps 3 and 4 as many times as they are applicable until a minimal cover of the function is found.
Unit 06 8
Determination of Prime Implicants

z Find all of the prime implicants (1). Represent each minterm by a binary code. (2). Find the decimal number for each binary code. (3). Define the number of 1s in binary number as the index of the number.
9 (3-1). Group all the binary numbers of the same index into a group. 9 (3-2). List all the groups in a column in the index ascending order. 9 (3-3). Within each group, the binary number are listed in the ascending order of their decimal-number equivalent.
Unit 06 9

(4).
Start with the terms in the set of lowest index; compare them with those, if any, in the set whose index is 1 greater, and eliminate all redundant variables by XY+XY=X. (5). Check off all the terms that entered into the combinations. The ones that are left are prime implicants. (6). Repeat Steps (4) and (5) until no further reduction is possible.
Unit 06 10

z Example: Find all of the prime implicants of the function f (a, b, c, d ) = m(0,1,2,5,6,7,8,9,10,14)
Unit 06
11

z Example: Find all of the prime implicants of the function f (a, b, c, d ) = m(0,1,2,5,6,7,8,9,10,14)
Unit 06
12

z Example (Cont.):
Minimum form ???
Unit 06
13
The Prime Implicant Chart

z Construct the Prime Implicant Table
(Chart) and find the Essential Prime Implicants of the function

(1)
Construct the prime implicant table
9(1-1) Each column carries a decimal number at the top which correspond to the one of the minterm in the given function, 9(1-2) The column are assigned by such a number in ascending order, 9(1-3) Each row corresponds to one of the prime implicants, P1,P2,.
Unit 06 14

(2)
Make a cross under each decimal number that is a term contained in the prime implicant represented by that row. (3) Find all the columns that contain a single cross and circle them; place an asterisk * at the left of those rows in which you circle a cross.
The rows marked with an asterisk are the essential prime implicants.
Unit 06
15

z Example:
Unit 06
16

z Example:
Unit 06
17

z Example with a cyclic prime implicant
table
F = m(0,1,2,5,6,7)
Sol: Find all of the prime implicants
Unit 06
18

z Sol(cont.): Select P1 first.
The minimum sum of products

Unit 06
F = ab + bc + ac
19

z Sol(cont.): Select P2 first.
The minimum sum of products
F = ac + bc + ab
The minimum sum of product is not unique.
Unit 06
20
Petricks Method
z A technique for determining all minimum
sum-of-products solutions from a prime implicant table.

z Before applying Petricks method, all
essential prime implicants and minterms they cover should be removed from the table.
Unit 06 21
Petricks Method
z Petricks Method 1. Label the rows of the table, P1,P2, 2. Form a logic function P(P1,P2,), which is true when all of the minterms in the table have been covered. 3. Reduce P to a minimum sum of products using (X+Y)(X+Z)=X+YZ and X+XY=X. 4. Select one solution that has minimum number of prime implicant, minimum number of literals.
Unit 06 22
Petricks Method
z Example: F = m(0,1,2,5,6,7)
Unit 06
23
Petricks Method
Example (cont.): In order to cover minterm 0, we must choose P1 or P2 ; therefore, the expression P1+P2 must be true. cover 0 P1+P2 1 P1+P3 2 P2+P4 5 P3+P5 6 P4+P6 7 P5+P6
Unit 06 24
Petricks Method
Example (cont.):
P = (P 1+P 2 )(P 1+P 3 )(P 2 +P 4 )(P 3+P 5 )(P 4 +P 6 )(P 5 +P 6) =1
Using ( X + Y )( X + Z ) = X + YZ and the distributive law
Unit 06
25
Petricks Method
Example (cont.):
P=P 1P 4P 5 +P 1P 2P 5P 6 +P 2P 3P 4P 5 +P 2P 3P 5P 6
Use X + XY = X to delete redundant terms from P

+P 1P 3P 4P 6 +P 1P 2P 3P 6 +P 2P 3P 4P 6 +P 2P 3P 6 =P 1P 4P 5 +P 1P 2P 5P 6 +P 2P 3P 4P 5 +P 1P 3P 4P 6 +P 2P 3P 6 3 implicants 4 4 4 3
Two minimum solutions:
F=P 1+P 4 +P 5 = a b + bc + ac F = P2 + P3 + P6 = ac + bc + ab
Unit 06 26
Simplification of Incompletely Specified Functions

z Modify the Quine-McCluskey procedure Finding the Prime Implicants 9Treat the dont care terms as if they were required minterms. Forming the Prime Implicant Table 9The dont cares are not list at the top of the table.
Unit 06
27

z Example: Simplify
F ( A, B, C , D) = m(2,3,7,9,11,13) + d (1,10,15)
Sol: Treat the dont cares (1,10,15) as required minterms
Unit 06
28

z Sol(cont.): The dont cares are not list
at the top of the table
Unit 06
29
Simplification Using Map-Entered Variables

z Map-Entered Variables
A modification of the Karnaugh Map z Quine-McCluskey Method

Can
be used with functions with a fairly large number of variables. Not very efficient for functions that have many variables and relatively few terms
Unit 06
30

z Map-Entered Variables
Example:
F ( A, B, C , D) = ABC + ABC + ABCD + ABCD + ( ABC )
where (ABC) is dont care. D appears in only two terms,

choose D as a map-entered variable.
F( A, B, C, D) = ABC + ABC + ABCD + ABCD+ ( ABC) = ABC + ABC + ( ABC)D + ( ABC)D + ( ABC) = m1 + m3 + m2 D + m7 D + (m5 )
Unit 06
31
Example (cont.):
Unit 06
32

z Map-Entered Variables Example:
G ( A, B, C , D, E , F ) = m0 + m2 + m3 + Em5 + Em7 + Fm9 + m11 + m15 + (m1 ) + (m10 ) + (m13 )
Unit 06
33

z General Method of Simplifying Functions
Using Map-entered Variables
If a variable Pi is placed in square mj of a map of function F, this means that F=1 when Pi=1 and the variable are chosen so that mj=1.
F = MS 0 + P 1 MS1 + P 2 MS 2 + ... MSi : M inimum S um
Unit 06
34

MS0 is the minimum sum obtained by setting P 1 = P 2 = ... =.0 MS is the minimum sum obtained by setting 1
P 1 = 1, Pj = 0( j 1)
and replacing all 1s on the map
with dont cares. MS is the minimum sum obtained by setting i Pi = 1, Pj = 0( j i ) and replacing all 1s on the map with dont cares. The resulting expression for F is
F = MS0 + P 1MS1 + P 2 MS 2 + ...
The expression will not generally be minimum if the variables P1,P2, are dependent (e.g. P1=E, P2=E,).
Unit 06
35

z Map-Entered Variables Example: Use Map-entered Variables to simplify the function
F ( A, B, C , D) = ABC + ABC + ABCD + ABCD + ( ABC )
where (ABC) is dont care. Sol: D appears in only two terms, choose D as a map-entered
variable.
F( A, B, C, D) = ABC + ABC + ABCD + ABCD+ ( ABC) = ABC + ABC + ( ABC)D + ( ABC)D + ( ABC) = m1 + m3 + m2 D + m7 D + (m5 )
Unit 06 36
Sol (cont.):
Unit 06
37

z Sol(cont.):
F ( A, B, C , D) = ABC + ABC + ABC D + ABCD + ( ABC )
F = AC + D (C + AB ) = AC + CD + ABD
Unit 06 38

z Example: Use the Map-Entered Variables method
to simplify the function
G ( A, B , C , D , E , F ) = m0 + m2 + m3 + Em5 + Em7 + Fm9 + m11 + m15 + ( m1 ) + ( m10 ) + ( m13 )
Let P1=E, P2=F.
Unit 06
39

z Example (cont.):
MS0 : The minimum sum obtained by setting P1=P2=0 MS1 : The minimum sum obtained by setting P1=1, P2=0 MS2 : The minimum sum obtained by setting P1=0, P2=1 (E=F=0). (E=1. F=0). (E=0, F=1).
G = MS 0 + P 1 MS1 + P 2 MS 2 = ( A B + ACD ) + E ( A D ) + F ( AD ) = AB + ACD + EAD + FAD

Unit 06 40
Homework
z 9 (c) z 12 (a), (b) z 15 z 20
Unit 06
41
Unit 7
Multi-Level Gate Circuits NAND and NOR Gates
Unit 7
z
Multi-Level Gate Circuits NAND and NOR Gates

7.1 Multi-Level Gate Circuits 7.2 NAND and NOR Gates 7.3 Design of Two-Level Circuits Using NAND and NOR Gates 7.4 Design of Multi-Level Circuits NAND and NOR Gates Circuits 7.5 Circuit Conversion Using Alternative Gate Symbols 7.6 Design of Two-Level, Multi-Output Circuits Determination of Essential Prime Implicants for Multiple-Output Realization 7.7 Multiple-Output NANA and NOR Circuits
Unit 07
Multi-Level Gate Circuits

z Level: The maximum number of gates cascaded in
series between a circuit input and the output is referred to as the number of level of gates.
z Example:
Unit 07

z Circuit of AND and OR gates : A circuit composed
only of AND and OR gates.

AND-OR Circuit: A two-level circuit composed of a level of

AND gates followed by an OR gate at the output
OR-AND Circuit OR-AND-OR Circuit: A three-level circuit composed of a level of OR gates followed by a level of AND gates followed by an OR gate at the output AND and OR Circuit: A circuit composed only of AND and
OR gates, no particular ordering of gates.
Unit 07

z Increasing/reducing the number of levels Increasing the number of levels 9Reduce the required number of gates 9Reduce the number of gate inputs 9Increase gate delays Reducing the number of levels 9Reduce gate delays, speed up the operation of the digital system
Unit 07

z Example:
z 4 levels
6 gates 13 gate inputs
Unit 07

z Example (cont.):
z 3 levels
6 gates 19 gate inputs
Unit 07
Example of Multi-level Design Using AND and OR Gates

z Example: Find a circuit of AND and OR gates to realize f ( a, b, c, d ) = m(1,5,6,10,13,14)
Sol: Simplify f by using a Karnaugh Map:
Unit 07

z Sol (cont.): Two-level AND-OR gate circuit
Unit 07

z Sol (cont.): Three-level circuit
f = acd + bcd + bcd + acd = cd (a + b) + cd (a + b)
Unit 07
10

z Sol (cont.): A two-level OR-AND circuit
corresponds to a product-of-sums expression.
f = cd + abc + cd + abc f = (c + d )(a + b + c)(c + d)(a + b + c)
Unit 07
11

z Sol (cont.): Three-level AND-OR-AND circuit
f = [c + d (a + b)][c + d (a + b)] f = (c + ad + bd )(c + ad + bd )
Unit 07
12
NAND and NOR Gates

z NAND gate: An AND gate followed by an NOT gate
z n-input NAND gates: n=2 F = ( AB ) = A + B n=3 F = ( ABC ) = A + B + C
+ ... + X n F = ( X 1 X 2 ... X n ) = X 1 + X 2
Unit 07
13
NAND and NOR Gates

z NOR gate: An OR gate followed by an NOT gate
z n-input NOR gates: n=2 F = ( A + B ) = AB n=3 F = ( A + B + C ) = ABC

... X n F = ( X 1 + X 2 ... + X n ) = X 1X 2
Unit 07
14
Functionally Complete
z A set of logic operations is said to be
functionally complete if any Boolean function can be expressed in terms of this set of operations. z {AND,OR,NOT} is functionally complete. z Any set of logic gates which can realize AND,OR, and NOT is also functionally complete. z {NAND} is functionally complete. z {NOR} is functionally complete. z {AND,OR} is not functionally complete.
Unit 07 15
z {AND,NOT} is functionally complete.
z {OR,NOT} is functionally complete.
Unit 07
16
z {NAND} is functionally complete.
z Any switching function can be realized
using only NAND gates.

Unit 07 17
z {NOR} is functionally complete.
using only NOR gates.

Unit 07 18
z {3-input minority} is functionally
complete.
Unit 07
19
z {3-input minority} is functionally
complete.
using only 3-input minority gates.

Unit 07 20
z Procedure for determining if a given set of
gates is functionally complete
1. Write out a minimum SOP expression for the function realized by each gate.
9 If no complement appears in any of these expressions, then NOT cannot be realized. 9 If complement appears in one of these expressions, then NOT can be realized. (assume that 0 and 1 are available as gate inputs)
2. Attempt to realized AND and OR ( NOT is now available). Once AND or OR has been realized, the other one can always be realized using DeMorgans Laws. XY = ( X + Y )
Unit 07 21
Design of Two-level Circuits Using NAND and NOR Gates

z Convert a two-level AND-OR or OR-
AND circuit to a circuit composed of NAND gates or NOR gates. Using

F = ( F )
Unit 07
22

z Example: Convert a minimum SOP form to
other two-level form
Unit 07
23

z Example (cont.):
Unit 07
24

z Example (cont.): Convert a minimum POS form to get a two-level NOR-NOR circuit. Obtain the minimum POS for F from a Karnaugh map.
Unit 07
25

z Example (cont.):
Unit 07
26

z
There are 16 possible two-level forms composed of AND, OR, NAND, and NOR gates.
Class
1. AND-OR, NAND-NAND, OR-NAND, NOR-OR Class 2. OR-AND, NOR-NOR, AND-NOR, NAND-AND Class 3. AND-AND, OR-OR, OR-NOR, AND-NAND,
NAND-NOR, NAND-OR, NOR-NAND, NOR-AND The forms in Class 3 are degenerated in the sense that they cannot realize all switching functions. For example, the NAND-NOR form can realized only a product of literals and not a sum of products.
Unit 07
27

z Procedure for designing a minimum two-
level NAND-NAND circuit

1.Find
a minimum sum-of-products expression for F. 2.Draw the corresponding two-level ANDOR circuit. 3.Replace all gates with NAND gates leaving the gate interconnections unchanged. If the output gate has any single literals as inputs, complement these literals.
Unit 07 28

z Transformation of step 3:
In general, F is a sum of literals ( l1 , l2 , L ) and products(P1 , P2 ,L)
F = l1 + l2 + ... + P 1 + P 2 + ... ...P 2...) F = (l1l2 1P
Unit 07
29

z Procedure for designing a minimum two-
level NOR-NOR circuit

1.Find
a minimum product-of-sums expression for F. 2.Draw the corresponding two-level ORAND circuit. 3.Replace all gates with NOR gates leaving the gate interconnections unchanged. If the output gate has any single literals as inputs, complement these literals.
Unit 07 30

z Transformation of step 3:
In general, F is a product of literals ( l1 , l2 , L ) and sums( S1 , S 2 L )
F = l1l2 S1S 2 ...

+ ... + S1 + S 2 ...) F = (l1 + l2
Unit 07
31
Design of Multi-level NAND- and NOR-Gate Circuits

z Procedure for designing Multi-level NAND-
gate circuits
1.Simplify the switching function to be realized. 2.Design a multi-level circuit of AND and OR gates. The output gate must be OR. AND (OR) gate outputs cannot be used as AND- (OR-) gate inputs. [ AND and OR gates alternate throughout the circuit.] 3.Number the levels starting with the output gate as level 1. Replace all gates with NAND gates, leaving all interconnections between gates unchanged. Leave the inputs to levels 2,4,6, unchanged. Invert any literals which appear as input to levels 1,3,5,.
Unit 07 32

z Example: Realize F1 using NAND gates.
] + hij + k F1 = a[b + c(d + e) + f g
Sol:
Unit 07
33

z Procedure for designing Multi-level NOR-gate
circuits
1.Simplify the switching function to be realized. 2.Design a multi-level circuit of AND and OR gates. The output gate must be OR. AND (OR) gate outputs cannot be used as AND- (OR-) gate inputs. [ AND and OR gates alternate throughout the circuit.] 3.Number the levels starting with the output gate as level 1. Replace all gates with NOR gates, leaving all interconnections between gates unchanged. Leave the inputs to levels 2,4,6, unchanged. Invert any literals which appear as input to levels 1,3,5,.
Unit 07 34
Circuit Conversion Using Alternative Gate Symbols

z Inverter:
z AND, OR, NAND, and NOR Gates
Unit 07
35

z Example:
Unit 07
36

z Example:
Unit 07
37
General Procedure for Converting AND-OR Circuits to NOR Circuits

z Converting NOT, OR, AND gates:
z Deleting two contiguous inverters
(bubbles).
Unit 07 38

z Example:
Unit 07
39

z Example:
Unit 07
40
General Procedure for Converting AND-OR Circuits to NAND Circuits

z Converting NOT, OR, AND gates:
z Deleting two contiguous inverters
(bubbles).
Unit 07 41
General Procedure for Converting AND-OR Circuits to NAND Circuits

z Example:
Unit 07
42
Design of Two-Level, MultipleOutput Circuits

z Example: Design a circuit with four inputs and three outputs which realizes the functions F1 ( A, B, C , D) = m(11,12,13,14,15)
F2 ( A, B, C , D) = m(3,7,11,12,13,15) F3 ( A, B, C , D ) = m(3,7,12,13,14,15)
Sol: Each function is realized individually.

The cost of the resulting circuit is 9 gates and 21 gate inputs.
Unit 07
43

z Sol (cont.):
F1 ( A, B, C , D) = m(11,12,13,14,15) = AB + ACD
F2(A,B,C,D) = m( 3,7 ,11,12 ,13,15 ) = ABC + CD
F3(A,B,C,D) = m( 3,7 ,12 ,13,14 ,15 ) = ACD + AB

Unit 07 44

z Sol (cont.):
Unit 07
45

z Sol (cont.): Use the common terms to save gates. F1=AB+ACD F2=ABC+CD=ABC+ACD+ACD F3=ACD+AB
Unit 07
46

z Sol (cont.):
4 AND gates 3 OR gates

z
In realizing multiple-output circuits, the use of a minimum sum-of-product implicants for each function does not necessarily lead to a minimum cost solution for the circuit as a whole.
Unit 07
47

z Example: Design a circuit with four inputs and three outputs which realizes the functions
f1 = m(2,3,5,7,8,9,10,11,13,15) f 2 = m(2,3,5,6,7,10,11,14,15) f3 = m(6,7,8,9,13,14,15)
Unit 07
48

z Sol (cont.):
Unit 07
49

z
Sol (cont.): f1= bd + bc + ab f2= c + abd f3= bc + abc + { abd or avd } 10 gates (7 AND gates and 3 OR gates) with 25 gate inputs f1= bd + bc + ab = abd + abd + abc + bc f2= c + abd f3= bc + abc + abd 8 gates (5 AND gates and 3 OR gates) with 22 gate inputs
Unit 07
50

z Some of the prime implicants essential to an
individual function may not be essential to the multiple-output realization.
Unit 07
51

z Solution with maximum number of
common terms may not be the best solution.
Unit 07
52
Multiple-Output NAND and NOR Circuits

z Example: Design a multiple-output NOR circuit to
realize the functions:
F1 = [(a + b)c + d ](e + f ) F2 = [(a + b)c + g ](e + f )h

If all
Sol: Realize the functions as AND-OR circuit.
of the output gates are OR(AND) gates, direct conversion to a NAND(NOR)-gate circuit is possible.
Unit 07
53
Multiple-Output NAND and NOR Circuits

z Sol (cont.):
Unit 07
54
Homework
z 2 (b) z6 z8 z 13 (a) z 17 z 24 z 32 z 39
Unit 07 55
Unit 8
Combinational Circuit Design and Simulation Using Gates
Unit 8
z Combinational Circuit Design and
Simulation Using Gates

8.1
Review of Combinational Circuit Design 8.2 Design of Circuits with Limited Gate Fan-In 8.3 Gate Delays and Timing Diagrams 8.4 Hazards in Combinational Logic 8.5 Simulation and Testing of Logic Circuits
Unit 08
Design of Circuits with Limited Gate Fan-In

z Fan in: The number of inputs on each gate z Example: Realize f (a, b, c, d ) = m(0,3,4,5,8,9,10,14,15)
using 3-input NOR gates.
Sol:
Unit 08

z Sol (cont.):
f=abcd+abcd+abc+abc+acd requires three 3-input gates, two 4-input gates, and one 5-input gate. f=bd(ac+ac)+ac(b+d)+abc f=[b+d+(a+c)(a+c)][a+c+bd][a+b+c] ----- --------------------requires four 2-input gates, four 3-input gates ( or eight 3-input gates).
Unit 08 4

z Sol (cont.): The resulting NOR-gate
circuit is
Unit 08

z Example: Realize the functions f1, f2 and f3 using only 2-input NAND gates and inverters. Sol.
Unit 08

Sol (cont.):Minimize each function separately,
Each function requires a 3-input OR gate. Factor to reduce the number of gate inputs:
Unit 08

Sol (cont.): f3=abc+b(a+c) =a(bc)+b(a+c) =a(b+c) +b(a+c)
Unit 08
Gate Delays and Timing Diagrams

z Propagation delay : If the change in output is delayed by time , , with respect to the input, we say that this gate has a propagation delay of . z Propagation delay in an inverter
Unit 08

z Timing Diagram
Example: Assume that each gate has a propagation delay of 20 ns (nanoseconds).
Unit 08
10

z Example: Circuit with and delay element
Unit 08
11
Hazards in Combinational Logic

z The unwanted switching transients may
appear in the output when different paths from input to output have different propagation delays. z Static 1- hazard: If , in response to any single input
change and for some combination of propagation delays, a circuit output may momentarily go to 0 when it should remain a constant 1, we say that the circuit has a static 1-hazard.
z Static 0- hazard: If , in response to any single input

change and for some combination of propagation delays, a circuit output may momentarily go to 1 when it should remain a constant 0, we say that the circuit has a static 0-hazard.
Unit 08 12

z Dynamic hazard: If, when output is supposed to change from 0 to 1 (or 1 to 0), the output may change three or more times, we say that the circuit has a dynamic hazard.
Unit 08
13

z Example: Circuit with a static 1-hazard
Assume that each gate has a propagation delay of 10 ns. If A=C=1, then F=B+B=1. F should remain a constant 1 when B changes from 1 to 0.
Unit 08
14

z Procedure for detecting hazards in a
two-level AND-OR circuit

1.Write
down the SOP expression for the
circuit. 2.Plot each term on the map and loop it. 3.If any two adjacent 1s are not covered by the same loop, a 1-hazard exists for the transition between the two 1s. For an nvariable map, this transition occurs when one variable changes and the other n-1 variables are held constant.
Unit 08 15

z Eliminating hazards
Add a loop to cover two adjacent 1s.
Unit 08
16

z Example: A circuit with several 0-hazards F=(A+C)(A+D)(B+C+D)
A=0, B=1, D=0, C changes from 0 to 1 Gate delay : 3 ns for NOT, 5 ns for AND/OR
Unit 08
17

Example (cont.):
Unit 08
18

Example (cont.):
Unit 08
19

Example (cont.):
Eliminating the 0-hazards by looping additional prime implicants that cover the adjacent 0s that are not covered by a common loop.
F = ( A + C)(A + D)(B + C + D)(C + D)(A + B + D)(A + B + C)
Unit 08
20

z Procedure for designing a circuit which is free
of static and dynamic hazards:
1. Find a SOP expression (Ft) for the output in which every pair of adjacent 1s is covered by a 1term. A two-level AND-OR circuit based on this Ft will be free of 1-, 0-, and dynamic hazards. 2. If a different form of the circuit is desired, manipulate Ft to the desired form by simple factoring, DeMorgans laws, etc. Treat each xi and xi as independent variables to prevent introduction of hazards. 3. Start with a POS expression in which every pair of adjacent 0s is covered by a 0-term to design a hazard-free two-level OR-AND circuit.
Unit 08 21
Simulation and Testing of Logic Circuits

z As logic circuits become more and more
complex, it is very important to simulate a design before actually building it. z Reasons for simulation
1. Verification that the design is logically correct, 2. Verification that the timing of the logic signals is correct, 3. Simulation of faulty components in the circuit as an aid to finding tests for the circuit.
Unit 08
22

z Simulator for combinational logic 1. Apply inputs to the first set of gates, and calculate the outputs of those gates. 2.Fed the outputs of the gates which changed in Step1 into the next level of gate inputs. Calculate the outputs of gates. 3. Repeat Step 2 until no more changes in gate inputs occur. The circuit is then in a steady-state condition, and the outputs may read. 4. Repeat Step 1 through 3 every time a circuit input changes.
Unit 08 23

z
Unit 08
24

z Four-valued logic simulation
X : do not know the logic value Z : has no logic signal ( high impedance)
Unit 08
25

z If a circuit is wrong for some set of input
signals, this may be due to :

1.
Incorrect design 2. Gates connected wrong 3. Wrong input signal to the circuit 4. Defective gates 5. Defective connecting wires
Unit 08
26

z Example: The function is realized by the circuit. F = AB(C D + CD) + AB(C + D)
Unit 08
27

z Fault Diagnosis:
Unit 08
28
Homework
z1 z3 z5 z7 z 10 z Designed Programs
Unit 08
29
Unit 9
Multiplexers, Decoders, and Programmable Logic Devices
Unit 9
z
Multiplexers, Decoders, and Programmable Logic Devices

9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders 9.5 Read-Only Memories 9.6 Programmable Logic Devices (PLD) Programmable Logic Arrays (PLA) Programmable Array Logic (PAL) 9.7 Complex Programmable Logic Devices (CPLD) 9.8 Field Programmable Gate Arrays (FPGA) Decomposition of Switch Functions
Unit 09
Introduction
z
Integrated Circuits (ICs)
Small-scale integration (SSI) 9 NAND, NOR, AND, OR, inverter, Flip-Flop 9 1-4 gates, 6 inverters, 1-2 Flip-flops Medium-scale integration (MSI) 9 Adder, multiplexer, decoder, register, counter 9 12-100 gates Large-scale integration (LSI) 9 Memories, microprocessors 9 100- a few thousand gates Very-large-scale integration (VLSI) 9 Microprocessors, FPGA, Application-specific integrated circuit (ASIC), 9 Several thousand gates or more
Unit 09 3
Introduction
z Programmable logic devices (PLDs) Programmable logic arrays (PLAs) Programmable array Logic devices (PALs) Complex programmable logic devices (CPLDs) Field-programmable gate arrays (FPGAs)
Unit 09
Multiplexers
z Multiplexers (MUX, or data selector)
A MUX has a group of data inputs and a group of control inputs. The control inputs are used to select one of the data inputs and connect it to the output terminal.
z 2-to 1 MUX

A=0, Z=I0 A=1, Z=I1 Z=AI0+AI1
Unit 09
Multiplexers
z 4-to-1, 8-to-1, 2n-to-1 MUX
z Logic equation for 8-to-1 MUX Z = ABC I 0 + ABCI1 + ABC I 2 + ABCI 3
+ ABC I 4 + ABCI 5 + ABC I 6 + ABCI 7

Unit 09 6
Multiplexers
z Logic Diagram for 8-to-1 MUX
Unit 09
Multiplexers
z Logic equation for 2n-to-1 MUX
2 n 1 k =0
Z=
mk I k
where mk is a minterm of the n control variables and I k is the corresponding data input
Unit 09 8
Multiplexers
z Quad Multiplexer Used to Select Data
A=0, (z0z1z2z3)=(x0x1x2x3) A=1, (z0z1z2z3)=(y0y1y2y3)

Unit 09 9
Multiplexers
z Quad Multiplexer with Bus Input and Output
z A=0, Z=X
A=1, Z=Y
Unit 09
10
Three-State Buffers
z
A gate output can only be connected to a limited number of other device inputs without degrading the performance of a digital system. z A buffer may be used to increase the driving capability of a gate output.
F =C
Unit 09 11
Three-State Buffers
z A logic circuit will not operate correctly if
the outputs of two or more gates or other logic devices are directly connected to each other. z Use of three-state logic permits the outputs of two or more gates or other logic devices to be connected together.
Unit 09
12
Three-State Buffers
z Three-state buffer (Tri-state buffer)
Enable input B=1, output C=A, when B=0, C acts like an open circuit, C is effectively disconnected from the buffer output so that no current can flow. This is referred to a Hi-Z (high-impedance) state of the output because the circuit offers a very high resistance or impedance to the flow of current.
Unit 09 13
Three-State Buffers
z Four kinds of Three-State Buffers
Unit 09
14
Three-State Buffers
z Data Selection Using Three-State
Buffers
D=BA+BC
Unit 09 15
Three-State Buffers
z Circuit with Two Three-State Buffers
Unit 09
16
Three-State Buffers
z Three-state Bus A bus is driven by three-state buffers z 4-Bit Adder with four sources for one
operand

Use a 4-to-1 MUX to select one of several sources Set up a three-state bus
Unit 09
17
Three-State Buffers
z Bi-directional I/O Pin
Buffer
is enabled, Output Buffer is disabled, Input
Unit 09
18
Decoders and Encoders

z Decoder

Generates all of minterms Exactly one of the outputs lines will be 1 for each combination of the values of the input variables.
z 3-to-8 Decoder
Unit 09
19

z 4-to-10 Line Decoder with Inverted Output
Unit 09
20

z 4-to-10 Line Decoder
Unit 09
21

z n-to-2n line decoder Generate all 2n minterms (or maxterms) of the n input variables Outputs 9Noninverted i=0,1,2,,2n-1 yi=mi , 9Inverted yi=mi=Mi , i=0,1,2,,2n-1
Unit 09
22

z Use decoder and gates to realize a
function z Example: Realize the following functions using a

decoder.
f1 (a, b, c, d ) = m1 + m2 + m4 f 2 (a, b, c, d ) = m4 + m7 + m9
Sol:
m2 m4 ) f1 = (m1 m7 m9 ) f 2 = (m4
Unit 09 23

Sol:
m2 m4 ) f1 = (m1 m7 m9 ) f 2 = (m4
Unit 09
24

z Encoder
The inverse function of a decoder

z 8-to-3 Priority Encoder
Unit 09
25
Read-Only Memories
z Read-Only Memory (ROM)
Consists of semiconductor devices that interconnected to store binary data
Unit 09
26
Read-Only Memories
n m 2 z A m ROM can realize m functions
(F1,F2,Fn) of n variables. z A ROM consists of a decoder and a memory array.
Unit 09
27
Read-Only Memories
z Multiple-output combinational circuits
can be realized using ROMs. z Example: Realize the following functions using ROM.
Unit 09
28
Read-Only Memories
z Sol:
Unit 09
29
Read-Only Memories
z Example: Design a code converter that converts a 4-bit
binary number to a hexadecimal digit and outputs the 7-bit ASCII code.
Unit 09
30
Read-Only Memories
, the ROM needs z Sol: Because A5 = A4 , A6 = A4
only five outputs. The ROM size is 16 words by 5 bits. The decoder is a 4-to-16 decoder.
Unit 09
31
Read-Only Memories
z Types of ROMs Mask-programmable ROMs Programmable ROMs (PROMs) Electrically Erasable Programmable ROMs (EEPROMs, E2PROMs) Flash memories Flash memory has built-in programming and erase capability so that data can be written to it while it is in place in a circuit without the need for a separate programmer.
Unit 09
32
Programmable Logic Devices

z Programmable Logic Device (PLD)
A general name for a digital integrated circuit capable of being programmed to provide a variety of different logic functions.
Lower
cost Changes in design

9Changing the programming of PLD 9Without having to change the wiring
Unit 09
33
Programmable Logic Arrays

z Programmable Logic Array (PLA) Perform the same basic function as a ROM A PLA with n inputs and m outputs can realize m functions of n variables.
Unit 09
34

z Example: Realize the following
functions using PLA.
Unit 09
35

z Sol:
Unit 09
36

z Sol (cont.): AND-OR equivalent circuit
Unit 09
37

z Sol (cont.): PLA Table
Unit 09
38

z Example: Use PLA to realize f1,f2, and f3. z Sol: Construct the PLA table
Unit 09
39

z Sol (cont.):
Unit 09
40
Programmable Array Logic

z Programmable Array Logic (PAL)

A special case of the PLA in which the AND array is programmable and the OR array is fixed Less expensive than the more general PLA Easier to program
z Symbols
Unit 09
41

z Example:
Unit 09
42

z Example: Implement a full adder using a PAL. z Sol:
Unit 09
43
Complex Programmable Logic Devices

z
Complex Programmable Logic Devices (CPLDs) z Architecture of Xilinx XCR3064XL CPLD
Unit 09
44

z
Xilinx XCR3064XL CPLD
4 function blocks (FBs) 9 Each FB has 16 associated macrocells (MC1, MC2,).

Each macrocell contains a flip-flop and multiplexers that route signals from the FB to the I/O block or to the interconnect array (IA)
9 Each FB is a programmable AND-OR array that is configured as a PLA. The IA selects signals from the macrocell outputs or I/O blocks and connects them back to FB inputs. A signal generated in one FB can be used as an input to any other FB. The I/O blocks provide an interface between the bidirectional I/O pins on the IC and the interior of the CPLD.
Unit 09
45

z Data Flow in XCR3064XL CPLD
Unit 09
46
Field Programmable Gate Arrays

z Layout of a Typical FPGA
Unit 09
47

z Field Programmable Gate Arrays (FPGAs)
An FPGA is an IC that contains an array of identical logic cells with programmable interconnections. The user can program the functions realized by each logic cell and connections between the cells. The interior of the FPGA consists of an array of logic cells, also called configurable logic blocks (CLBs). The array of CLBs is surrounded by a ring of input-output interface blocks (I/O blocks). The I/O blocks connect the CLB signals to IC pins. The space between the CLBs is used to route connections between the CLB outputs and inputs.
Unit 09
48

z
Simplified Configurable Logic Block (CLB)
2 Function generators ( implemented as lookup tables, LUTs) 9 4 I/Ps, can implement any function of up to 4 variables 2 Flip-flops (D-FFs) 5 MUXs for routing signals within CLB.
Unit 09
49

z Lookup table (LUT) A reprogrammable ROM Stores the truth table for a function
Unit 09
50
Decomposition of Switching Functions

z Decomposition
In order to implement a switching function of more than n variables using n-variable function generators, the function must be decomposed into subfunctions where each subfunctions requires only n variables or less.
z Shannons Expansion Theorem
Unit 09
51

z Example:
Unit 09
52

z Function Expansion Using a
Karnaugh Map
f 0 = cd + bc + cd
Unit 09
f1 = c + bd
53

z Realization of Five-Variable Function
with 4-input Function Generators
Unit 09
54

z Realization of Six-Variable Function with
4-input Function Generators
Unit 09
55
Unit 09
56
Homework
z 12 (a) z 15 z 21 z 23 z 26 z 30
Unit 09
57

Dept 34 LV 3 14909

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Text: Charles H. Roth, Jr.

Fundamentals of Logic Design

Number Systems and Conversion

Digital Systems and Switching Circuits

Digital Systems and Switching Circuits

Design of digital systems

Digital Systems and Switching Circuits

form of a switching network

Number Systems and Conversion

Number Systems and Conversion

Number Systems and Conversion

Number Systems and Conversion

N = an R n 1 + an 1 R n 2 + L + a2 R1 + a1 = Q1 , remaider a0 R Q1 = an R n 2 + an 1 R n 3 + L + a3 R1 + a2 = Q2 , remaider a1 R Q2 = an R n 3 + an 1 R n 4 + L + a4 R1 + a3 = Q3 , remaider a2 R

This process is continued until we finally obtain an.

Number Systems and Conversion

Number Systems and Conversion

This process is continued until we have obtained a sufficient number of digits.

Number Systems and Conversion

Number Systems and Conversion

Number Systems and Conversion

Number Systems and Conversion

hexadecimal digit corresponds to four binary digits (bits)

= (0011 0000 0110 1101) 2 3 0 6 D

Example: Add 1310 and 1110 in binary.

Representation of Negative Numbers

9N is represented by its 2s complement, N*. If the word length is n,

Representation of Negative Numbers

Negative Number N 9N is represented by its 1s complement N . If the word length is n,

Representation of Negative Numbers

Addition of 2s Complement Numbers

Any carry from the sign position is ignored. n=4

Addition of 2s Complement Numbers

Addition of 2s Complement Numbers

Addition of 2s Complement Numbers

Addition of 1s Complement Numbers

Addition of 1s Complement Numbers

Addition of 1s Complement Numbers

Addition of 1s Complement Numbers

(Switching Algebra) B2=({0,1}; . ,+, ; 0,1) AND

B4=({0,a,b,1} ; . ,+, ; 0,1) AND OR . 0 a b 1 + 0 a b 0 0 a b 0 0 0 0 0 a a a 1 a 0 a 0 a b b 1 b b 0 0 b b 1 1 1 1 1 0 a b 1

element of B is called a (Boolean) variable on B. e.g. x,y,z,

system (B; . ,+, ; 0,1) is defined as follows:

AND, OR, and NOT (complement, or inverse).

9Omit the symbol ., A . B=AB

Boolean Expressions and Truth Tables

ParenthesesComplentationANDOR z Circuits for expressions

Commutative, Associative, and Distributive Laws

Proof of Boolean Theorems

Proof of Boolean Theorems

Let ( AB + C) = Y , BD + CE = X then Z = ( AB + C)(BD + CE) + ( AB + C) = Y X + Y = X + Y = BD + CE + ( AB + C)

circuit and design a simpler circuit having the same output.

Sol: Y = (AB + (AB + B))B + A

Multiplying Out and Factoring

( A + B)(C + D + E )( A + C + E ) , ABC ( D + E ) are in POS form, (A + B)(C + D) + EF is not in POS form.

Multiplying Out and Factoring

Multiplying Out and Factoring

Multiplying Out and Factoring

A + BCD = ( A + B)( A + CD ) = ( A + B)( A + C )( A + D)

C D + C E + GH = C (D + E ) + GH = (C + GH)(D + E + GH) = (C + G)(C + H)(D + E + G)(D + E + H)

X3 ... X n ( X 1 + X 2 + X 3 + ... + X n ) = X 1X 2 + X3 + ... + X n ( X 1 X 2 X 3 ... X n ) = X 1 + X 2

Laws , x2 , L , xn ,1,0,,+) [ f ( x1 , x2 , L , xn ,0,1,+,)] = f ( x1