Basic Finite State Machines

Basic Finite State Machines

Finite State Machines

Binary encoded state machines
The number of flip-flops is the smallest number m such that 2 m n, where n is the number of states in the machine. Next state logic equations are dependent on all of the flip-flops in the implementation. Natural for CPLDs, where CPLDs have high fan-in logic gates. There may be unused states.

Basic Finite State Machines

Finite State Machines

Gray encoded state machines
Similar to binary encoded state machines. State sequence has the property that only one output changes when sequencing between states. Can have lower power Can be asynchronously sampled in some systems. There may be unused states.

Basic Finite State Machines

Finite State Machines

One-Hot Finite State Machines
One flip-flop for each state in the machine Normal operation has exactly one flip-flop set; all other flip-flops reset. Next state logic equations for each flip-flop depend solely on a single state (flip-flop) and external inputs. Natural for FPGAs, which dont have high fanin logic gates and an abundance of flip-flops.] There will be unused states
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Finite State Machines

Modified One-Hot Finite State Machines
n-1 flip-flops for an n-state machine Normal operation has zero or one flip-flop set
The all zeros state is a legitimate state

There will be unused states

Basic Finite State Machines

Finite State Machines

Linear Feedback Shift Register (LFSR)
The number of flip-flops is the smallest number m such that 2 m n, where n is the number of states in the machine. Shift register with XOR feedback Maximal length shift registers can have 2m-1 states. Can modify the circuit to support 2m states.

Basic Finite State Machines

Finite State Machines

Example Linear Feedback Shift Register

Two or four taps

Basic Finite State Machines 7

Finite State Machines

Johnson Ring Counter
Also called twisted-ring or Mobius counter For n flip-flops, it will have 2n states. Shift register with inverted feedback Unmodified, it will have unused states Can modify the circuit to support 2n-1 states.

Basic Finite State Machines

Encoding Efficiency: Binary vs. One Hot

50 Binary of Gray Code One Hot Coding Modified One Hot Coding 40

Number of Flip-Flops

30

20

10

0 0 10 20 30 40 50

Number of States
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Finite State Machines

CAE Tools - Synthesizers
Generates logic to implement a function, guided by the user. Typically does not generate logic for either fault detection or correction, important for military and aerospace applications.

Basic Finite State Machines

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Finite State Machines

Lockup State
A state or sequence of states outside the normal flow of the FSM that do not lead back to a legal state.

Basic Finite State Machines

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Lockup States
Sample State Machine
Reset

Home Ping Three

One

Two
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Library IEEE; Use IEEE.Std_Logic_1164.All; Entity Onehot_Simple_Act Is Port ( Clk : In Std_Logic; Reset : In Std_Logic; Ping : Out Std_Logic ); End Onehot_Simple_Act; Library IEEE; Use IEEE.Std_Logic_1164.All; Architecture Onehot_Simple_Act of Onehot_Simple_Act Is Type StateType Is ( Home, One, Two, Three ); Signal State : Statetype; Begin M: Process ( Clk, Reset ) Begin If ( Reset = '1' ) Then State <= Home; Else If Rising_Edge (Clk) Then Case State Is When Home => When One => When Two => When Three => End Case; End If; End If; End Process M; O: Process (State) Begin If (State = Home) Then Ping <= '1'; Else Ping <= '0'; End If; End Process O; End Onehot_Simple_Act; 13

Enumeration
State State State State <= <= <= <= One; Two; Three; Home;

Next-state Logic All states covered

Basic Finite State Machines

Lockup States
A Synthesized One-Hot Implementation

Typical ring counter with lockup states was synthesized.

Basic Finite State Machines

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Lockup States
Another Synthesized One-Hot Implementation

Note: Results depend on version of synthesis software. This circuit was synthesized with the same product used in the previous slide. Note this is a modified one-hot FSM.
Basic Finite State Machines 15

Lockup States
Yet Another Synthesized One-Hot Implementation (free product)

Modified one-hot state machine (reset logic omitted) for a 4-state, twophase, non-overlapping clock generator. A NOR of all flip-flop outputs and the home state being encoded as the zero vector adds robustness. Standard one-hot state machines [Q3 would be tied to the input of the first flip] have 1 flip-flop per state, with exactly one flipflop set per state, presenting a non-recoverable SEU hazard.
Basic Finite State Machines 16

Lockup States
A Safe One-Hot Implementation (Synthesized)

Reset flip-flops. Note second one is on falling edge of the clock. This implementation uses 6 flip-flops.
Basic Finite State Machines 17

Lockup States
A Safe One-Hot Implementation (Synthesized)

Reset flip-flops. Note second one is on falling edge of the clock. This implementation uses 6 flip-flops.
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Lockup States - Binary Encoding

Home Ping

Four

One

Three unused states. (Five, Six, Seven)

Two Three

Basic Finite State Machines

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Lockup States
Binary Encoding
Type Signal StateType Is ( Home, One, Two, Three , Four); State : Statetype; Case State Is When Others => State <= Home;

When Others refers to the logical states in the VHDL enumeration, not the physical implementation. Also, states that are not reachable can be deleted, depending on the software and settings.
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Two Most Common Finite State Machine (FSM) Types

Binary: Smallest m (flip-flop count) with 2m n (state count), highest encoding efficiency.
Or Gray Coded, a re-mapping of a binary FSM

One Hot: m = n, i.e., one flip-flop per state, lowest encoding efficiency.
Or Modified One Hot: m = n-1 (one state represented by 0 vector).
Basic Finite State Machines 21

Issue: How To Protect FSMs Against Transient Errors (SEUs and MEUs):
Illegal State Detection Adding Error Detection and Correction (EDAC) Circuitry

Basic Finite State Machines

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Binary and Gray Codes

FSM State Sequences
0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Binary sequence can have 0 (hold), 1, 2, ..., n bits changing from state to state. Gray code structure ensures that either 0 (hold) or 1 bit changes from state to state. Illegal states in either type are detected in the same way, i.e., by explicit decoding.

3-bit Reflected Gray Code

Basic Finite State Machines

Binary Code

23

Gray Code
Illegal Transition Detection
inputs Next State Logic State Bit Register outputs

Last State Register

Bit-wise XOR

>1 logic 1

illegal transition

False illegal transition indications can also be triggered by errors in the Last State Register, and doubling the number of bits doubles the probability of an SEU.
Basic Finite State Machines 24

One Hot FSM Coding

Many (2n-n) unused states - not "reachable" from VHDL2. Illegal state detection circuitry complex One Hot Binary Code Parity (odd) will Coding detect all SEUs, not MEUs "The Impact of Software and CAE Tools on SEU in Field
1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
25

Programmable Gate Arrays," R. Katz, et. al., IEEE Transactions on Nuclear Science, December, 1999. Basic Finite State Machines

One Hot FSM Coding Example of Lockup

7 1 0 0 0 0 1 0 0 6 0 1 0 0 0 0 1 0 5 0 0 1 0 0 0 0 1 4 0 0 0 1 0 0 0 0 3 0 0 0 0 1 0 0 0 2 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1

SEU

FSM is locked up.

One Hot FSM without protection.

Basic Finite State Machines 26

Modified One Hot FSM Coding

7 1 0 0 0 0 0 0 0 6 0 1 0 0 0 0 0 0 5 0 0 1 0 0 0 0 0 4 0 0 0 1 0 0 0 0 3 0 0 0 0 1 0 0 0 2 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 6 0 1 0 0 0 0 0 0 5 0 0 1 0 0 0 0 0 4 0 0 0 1 0 0 0 0 3 0 0 0 0 1 0 0 0 2 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1

Modified One Hot Coding Note: Sometimes used by synthesis when one hot FSM specified. Modified one hot codings use one less flip-flop.
Basic Finite State Machines 27

One Hot Coding

Modified One Hot FSM

Illegal State Detection
Error detection more difficult than for one hot
1 0 upsets result in a legal state. Parity will not detect all SEUs. If an SEU occurs, most likely the upset will be detectable

Recovery from lockup sequence simple

If all 0's (NOR of state bits), then generate a 1 to first stage. If multiple 1's (more difficult to detect), then will wait until all 1's are "shifted out."
Basic Finite State Machines 28

Discuss Hamming Codes (to be included)

Basic Finite State Machines

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Is There a Best FSM Type, and Is It Best Protected Against Transient Errors By Circuit-Level or System-Level EDAC?
Circuit-level EDAC
Expensive in power and mass if used to protect all circuits Can be defeated by multiple-bit transient errors Can be defeated by clock upset

System-level EDAC
Required for hard-failure handling Relies on inherent redundancy in system, high-level error checking, and some EDAC hardware
Basic Finite State Machines 30

But It Gets Worse

Some synthesizers may replicate flip-flops.
Block A Block B

Block C

Block D

Block A Block B

Block C

Block D

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And Worse ...

Backend software may also replicate flipflops This can be bad if the flip-flop is used to synchronize an asynchronous signal.

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And Yet Worse ...

Logic Translation/Optimization Original

Optimized
Yes, the designer used this point to synchronize signals and drive a motor. The short circuit was bad.
Basic Finite State Machines 33

What Can You Do?

Some Helpful Hints and Points for Discussion
CONTROL Your Design
Schematic vs. HDL Constant encodings vs. enumeration
Manual State Assignment

Dont leave unused states - add Dummy States

Add logic to trick the synthesizer to think they are used as otherwise they may be optimized out. This may include adding a test signal to sequence through unused states as well as bringing out dummy outputs.
Basic Finite State Machines 34

What Can You Do?

More Helpful Hints and Points for Discussion
Ban All FPGAs

Basic Finite State Machines

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What Can You Do?

More Helpful Hints and Points for Discussion
Monitor Your Design
Check The Synthesizer Listings
Number of flip-flops
Too many flip-flops; replication? Too few flip-flops; eliminated your TMR or parity?

Reports of replication Is the state assignment one that you asked for? Sometimes the synthesizer thinks it knows best.

Basic Finite State Machines

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What Can You Do?

More Helpful Hints and Points for Discussion
Monitor Your Design (continued)
Check Flip-Flop Reports
Has it moved flip-flops into the I/O cells with perhaps poor SEU performance? Substituted an S-Module based flip-flop for your CModule based one? Did the synthesizer generate TMR the way you asked for it or just ignore you?
Basic Finite State Machines 37

What Can You Do?

More Helpful Hints and Points for Discussion
Monitor Your Design (continued)
Check Auxiliary Files
Check list of cells that the optimizer deleted

Generate Schematics for Critical Areas of Synthesized Logic

This may uncover some rather interesting surprises. Send them to me for the next seminar; win a free Diet Coke.
Basic Finite State Machines 38

What Can You Do?

More Helpful Hints and Points for Discussion
Verify your design thoroughly
Do not rely solely on simulation!!!!!

Look and think. Do not rely on these tools to do your thinking for you.

Basic Finite State Machines

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