MAX+PLUS II Tutorial Manual

Version 3.0

304-487
Computer Architecture Laboratory

Prepared by:
Albert Au
Victor Tyan
Boonchuay Supmonchai
Prof. Ted Szymanski

January 18, 1999

Email: ta487@ece.mcgill.ca
Website: www.ece.mcgill.ca/courses/304-487

Acknowledgement :

Partial software and hardware support from

the "Altera University Program" is gratefully acknowledged.
 Table of Contents
1. Introduction
1.1 Running MAX+PLUS II .................................................2
1.2 Overview of MAX+PLUS II .............................................3

2. Creating a design in VHDL

2.1 Example: A binary sorting node ..........................................4
2.2 Entering VHDL code ......................................................6
2.3 Checking your VHDL code ...............................................6

3. Compiling your VHDL code

3.1 Brief description of compiler stages .....................................7
3.2 Setting compiler options ..................................................8
3.2.1 Selecting a device family .........................................8
3.2.2 Selecting a global project logic synthesis style ................9
3.2.3 Turning on the smart recompile command .....................9
3.2.4 Enabling compilation for VHDL-93 ...........................10
3.3 Running the compiler ....................................................10

4. MAX+PLUS II Simulator
4.1 Function simulation versus Timing simulation .......................11
4.2 Timing simulation using a simulator channel file (.SCF) ............12
4.2.1 Editing a SCF ....................................................13
4.3 Timing simulation using a vector file (.VEC) .........................14

5. MAX+PLUS II Timing Analyzer

5.1 Registered performance ..................................................15
5.2 Determining the critical path .............................................16
5.3 Using the Delay Matrix ..................................................17

6. Analyzing synthesis results (.RPT file) ...............................18

7. Changing compiler settings
7.1 Viewing logic synthesis equations .....................................19
7.2 Optimizing logic synthesis for speed ...................................19

8. Guidelines ......................................................................20
9. Resources ......................................................................22
Appendix A VHDL Description .......................................................23
Appendix B Vector file: binary_sort.vec .........................................29
Appendix C Conventions on writing VHDL documentation ......................30
Appendix D FAQ Table of Content ...................................................31

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 1. Introduction
Your approach to creating an electronic design in MAX+PLUS II can have a major impact on both the
quality of your design and your productivity in creating the design. At the beginning of the design creation
process, you should focus on the key design creation issues that affect overall quality, keeping in mind the
tasks necessary to successfully complete your design. You should consider the following issues and tasks:

• Carefully planning your design.

• Building design hierarchy in VHDL.
• Checking design syntax and connectivity.
• Testing and simulating each module.
• Simulating with different test benches.

1.1 Running MAX+PLUS II

To start Maxplus2 (version 9.0), the following steps are necessary.

However, there is small problem with the system variable settings, which you have to workaround until the
problem is fixed. Each time you logon, you will need to override the variables TEMP and TMP by
following these steps. You only have to perform these steps once per logon session.

• From the Start Menu, select Settings -> Control Panel.

• Double-click on the System icon. Select the Environment tab.
• In the User Variable window, select variable "temp" and in the Value field at the bottom,
replace "d:\temp" with "f:\temp". Click the Set button.
• Repeat the above step for the user variable "tmp".
• Click the OK button to exit. Close the Control Panel.
• To run Maxplus2, select "Start Menu -> Programs -> MAX+PLUS II -> Maxplus2 9.0".

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1.2 Overview of MAX+PLUS II
MAX+PLUS II software consists of several application programs and the MAX+PLUS II Manager. The
following describes some of the application programs that will be used in this course.

• Hierarchy Display - Displays the current hierarchy of files as a hierarchy tree with branches
that represent sub-designs. You can tell at a glance which files are currently open and you can
also directly open or close one or more files in a hierarchy tree.

• Text Editor - The Text Editor lets you create and edit text based logic design files such as
VHDL.

• Compiler - Processes logic projects targeted for Altera device families (e.g. FLEX 10K). It
performs most tasks automatically. However, you can customize all or part of the compilation
process.

• Waveform Editor - Serves as a tool for entering test vectors and viewing simulation results.

• Simulator - Enables you to test the logical operation and internal timing of your logic circuit.
Functional simulation, timing simulation, and linked multi-device simulation are available.

• Timing Analyzer - Analyzes the performance of your logic circuit after it has been
synthesized and optimized by the Compiler.

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 2. Creating a design in VHDL
In this section, you will learn how to enter a VHDL design in text format into the MAX+PLUS II software
and to check whether the VHDL code you have entered is correct.

2.1 Example : A Binary Sorting Node

The example you are going to explore is the design of a binary sorting node. Figure 1 shows the
functional block diagram of such a node. It consists of two input D-flipflops, two output D-flipflops, two
multiplexors, and a state machine that controls the two multiplexors. The VHDL code that describes it
structurally is given in Appendix A. Before you continue, please spend some time reading the conventions
on writing VHDL code in Appendix C.

upper
x_in 0
x
DFF DFF x_out
mux
1 S = min (x_in, y_in)

clock state exchange

reset machine

1 S

DFF mux DFF y_out

y_in 0 y = max (x_in, y_in)
lower

Figure 1 : Functional Block Diagram of a binary sorting node

Note : clock and reset signals go to every flipflop and the state machine

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After the node is reset, all flipflops and the state machine are cleared. The data are then clocked serially into
the input flipflops with most significant bit first. For every clock cycle, a bit from each input is compared
with each other inside the state machine which will determine the states of the sorting node.

There are three states in the state machine, "X_equal_Y", "X_less_than_Y", and "X_greater_than_Y", as
shown in figure 2.

• If the incoming bits from both signals are equal, the state machine remains in the X_equal_Y state and
the multiplexor’s control signals are set such that x_in connects to x_out and y_in connects to y_out.

• If the bit from x_in is less than the bit from y_in, the state machine will be locked at the X_less_than_Y
state so that the subsequent results of bit comparison would not alter the setting of the multiplexors.

• On the other hand, if the bit from x_in is greater, the node will be locked at the X_greater_than_Y state
with x_in connected to y_out and y_in connected to x_out.

Figure 2 shows the state diagram of the state machine whose behavioral description is given in Appendix
A. We will talk more about the approaches that we can describe a design in VHDL in the next assignment.

(upper = lower) reset / exchange = '0'

upper < lower / exchange = '0' upper > lower / exchange = '1'
X_equal_Y

reset reset

X_less_than_Y X_greater_than_Y

Figure 2 : State diagram of the state machine in a binary sorting node.

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2.2 Entering VHDL code
To enter this design into MAX+PLUS II

• Choose NEW (File menu), select Text Editor file, and choose OK to open an untitled Text
Editor window.
• If necessary maximize the Text Editor window by clicking Maximize button on the top right
corner of the Text Editor title bar. Type in the VHDL description for the binary sorting node
given in Appendix A.
• Choose Save As (File menu). Enter binary_sort into the File Name box and change the
Automatic File Extension to .vhd. Click on OK. Remember that the name of the file has to be
the same as the name of the entity.
• Repeat the steps shown above until you enter all the files in Appendix A. Make sure that you
save all VHDL files in the same directory.

Figure 3: Save As dialog box

2.3 Checking your VHDL code

The next step is to quickly check the correctness of your design using the compiler.

• Make sure that you select the window Text Editor - binary_sort. Choose Project Save &
Check (File menu).
• A dialog box will appear asking whether you want to change the current project name to the file
you are going to compile. Click on YES. Observe what happens.
• Choose OK when the compiler completes its process. If there are no errors and warnings go
on to the next subsection.
• If the Message window appears, check for error and warning messages. At this point, errors are
usually violations of VHDL syntax. Correct the errors and repeat the process.

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 3. Compiling your VHDL code
3.1 Brief Description of Compiler Stages
The MAX+PLUS II Compiler is a highly automated design processor that transforms design files into
output files for device programming, simulation, and timing analysis. When you start the compiler, it
begins a series of processes that ultimately creates one or more programming files. While the compiler can
compile a project with minimal assistance, it also allows you to customize processing for a particular
project. The following are brief descriptions of some compiler stages that you should know. For more
details on the compiler stages and their options, please consult the MAX+PLUS II On-line Help or the
Altera MAX+PLUS II Getting Started Manual.

• Compiler Netlist Extractor. The compiler first extracts information that defines the
hierarchical connections between design files, then checks the overall project for errors.

• Database Builder. After the Compiler creates an organizational map of your project, it
combines all design files into a fully flattened database for fast and efficient processing.

• Logic Synthesizer. The Compiler applies a range of techniques to increase the efficiency of
your project and minimize device resource usage. The optional Design Doctor utility checks
project logic reliability both before and after logic synthesis.

• Partitioner. If a project is too large to fit into a single device, the Compiler partitions it among
multiple devices from the same device family, either automatically or according to your
specifications.

• Fitter. The Fitter generates a customizable Report File that details resource usage and
describes how the project will be implemented in one or more device(s).

• Timing SNF Extractor. The optional Timing SNF Extractor creates an SNF file which
contains the timing data for timing simulation and timing analysis.

• Functional SNF Extractor. The optional Functional SNF Extractor creates the functional
Simulator Netlist File (.snf) required for functional simulation. The functional SNF does not
contain timing information, thus it is generated quicker than the Timing SNF.

• Assembler. The Assembler generates one or more files for device programming.

Figure 4: Compiler window

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3.2 Setting Compiler Options
In this section, you will learn to change some useful options in the compiler such as Devices and Logic
Synthesis Options in order to achieve your design goal. Introduced here are only frequently-used compiler
options. For other options, you must refer to the MAX+PLUS II On-line Help or the Altera MAX+PLUS
II Getting Started Manual.

3.2.1 Selecting a Device Family

You can select any MAX+PLUS II- supported device family for your project. You can also allow the
Compiler to automatically choose the most appropriate device within a particular family.

To specify the device family

• Choose Device (Assign menu). The Device dialog box is displayed.

• Look at the Device Family supported by the MAX+PLUS II by clicking on the arrow at the end
of the Device Family box. Select FLEX10K if it has not been selected.
• Check on the device in the Devices box. Then turn on the option Show Only Fastest Speed
Grades, and observe.
• Choose AUTO in the list of Devices and click OK.

Figure 5: Devices window

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3.2.2 Selecting a Global Project Logic Synthesis Style

You can select a logic synthesis style for the project that guides the Compiler’s Logic Synthesizer module
during compilation. The two main styles are "minimization of silicon resource" and "minimization of
delay". The default logic synthesis style for a new project is “Normal”. The logic option settings in this
style optimize your project logic for minimum silicon resource usage.

To select a logic synthesis style for the project.

• Choose Global Project Logic Synthesis (Assign menu). The Global Project Logic
Synthesis dialog box is displayed.
• Move the Optimize scroll bar to the middle (5) and click OK.

Figure 6: Global Project Logic Synthesis window

3.2.3 Turning on the Smart Recompile Command

When the "smart" recompile feature is turned on, the Compiler saves extra database information for the
current project for use in subsequent compilations. During “smart” compilation, the Compiler can
determine which modules are not needed to recompile the project, and will skip them during recompilation,
thereby reducing compilation time.

To turn on the smart recompile feature:

• Choose Compiler (MAX+PLUS II menu). The Compiler window is displayed.

• Choose Smart Recompile (Processing menu).

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3.2.4 Enabling Compilation for VHDL-93

VHDL is a standard (VHDL-1076) developed by IEEE (Institute of Electrical and Electronics Engineers).
It was standardized in 1987 and hence the designation std 1076-1987 or VHDL-87. The standard was
revised in 1993 to produce std 1076-1993 or VHDL-93.

By default, MAX+PLUS II will use VHDL-87. To enable compilation for VHDL-93:

• Choose Compiler (MAX+PLUS II menu). The Compiler window is displayed.
• Choose VHDL Netlist Reader Settings (Interfaces menu).
• Select the VHDL 1993 button and click OK.

Note that you must repeat these steps for each VHDL file you compile.

Figure 7: VHDL Netlist Reader Settings dialog box

3.3 Running the Compiler

To compile the project:

• Choose the Start button in the Compiler window. As the Compiler processes the project, any
information, error, or warning messages appear in a Message Processor window that opens
automatically.

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 4. MAX+PLUS II Simulator
The MAX+PLUS II Simulator provides flexibility and control for modeling single or multi-device projects.
The Simulator uses a binary simulation netlist file that is generated during compilation to perform
functional, timing, or combined linked multi-device simulation for a project.

You can either define input stimuli with a straightforward vector input language or you can draw waveforms
directly with the MAX+PLUS II Waveform Editor. Simulation results can be viewed in the Waveform
Editor and printed as waveform files.

Figure 8: Simulator window

4.1 Functional Simulation versus Timing Simulation

The MAX+PLUS II Simulator supports functional simulation to test the logical operation of a project
before it is synthesized, thereby allowing the designer to quickly identify and correct logical errors. Note
that in functional simulation mode, output logic levels change at the same time as the input vectors i.e., no
propagation delays are used. You can turn on functional simulation by choosing Compiler (MAX+PLUS
II menu) and selecting Functional SNF Extractor (Processing menu).

In a timing simulation, the MAX+PLUS II Simulator tests the project after it has been fully synthesized
and optimized. Timing simulation is performed at 0.1ns resolution. You can turn on timing simulation by
choosing Compiler (MAX+PLUS II menu) and selecting Timing SNF Extractor (Processing menu).

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4.2 Timing Simulation using a Simulator Channel File (.SCF)
The simulator channel file contains some or all of the nodes in the compiled project. This SCF file is then
used to provide inputs and to view the results of the simulation.

To create an SCF file for the binary sorting node:

• Make sure that the design of the binary sorting node has been compiled with the Timing SNF
Extractor option turned ON (see section 4.1).
• Choose New (File menu), select Waveform Editor file, select the .scf extension from the list
box and click OK to invoke the Waveform Editor with a new, untitled file.
• Choose End Time (File menu) and type 2us for 2 microseconds. The end time determines
when the simulator will stop applying input vectors. Choose Grid Size (Options menu), type
50ns for 50 nanoseconds and click OK.
• Choose Enter Nodes from SNF (Node menu) to display the dialog box. Turn off the Group
option under Type (The Inputs and Outputs options should remain turned on). Click List to
display the available input (I) and output (O) nodes.

Figure 9: Enter Nodes from SNF window

• Press the mouse button on the topmost node in the Available Nodes & Groups box and drag
the mouse to highlight all the inputs and outputs. Choose the right direction button (=>) to
copy the selected nodes. Alternatively, you may double-click on a node to select it.
• Click OK. The selected nodes appear in the Waveform Editor window. All input waveforms
have default logic 0. All output waveforms have default undefined (X) states.

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 • To rearrange a node, press the mouse button on the handle to the left of the node name and
move the pointer. A horizontal line displays the current position. Order the nodes in this
sequence x_in, y_in, reset, clock, x_out, y_out.
• Choose Save As (File menu). The name binary_sort.scf appears automatically in the File
Name box. Click OK to save the file.

4.2.1 Editing a Simulator Channel File

You must edit the input waveforms to provide the input vectors for simulation. As you simulate the project,
the simulator overwrites the undefined output waveforms.

To edit the input waveform for clock:

• Move the pointer and press the mouse button on the Value field for the clock input node. This
highlights the entire waveform for this node. Click on the Overwrite Clock button from the tool
palette on the left side of the window or choose Overwrite Clock (Edit menu). To create a
clock waveform at the current grid size (50ns), click OK to accept the default values. Note that
the clock period is actually 100ns.

You can increase/decrease the scale of the waveforms by choosing Zoom In/Zoom Out (View menu) or
clicking on the magnifying glass buttons from the tool palette.

To edit the input waveform for reset:

• Reset is an active high signal. Use the pointer to highlight the interval from 0ns to 100ns (2
grid units). Click the Overwrite High (1) button from the tool palette. Repeat this step to assert
a logic high for the interval 800ns to 900ns. To assert logic low, click the Overwrite Low (0)
button. These commands can also be found in the Edit menu.

To edit the input waveform for x_in:

• Input the value 1101 after the first reset pulse with the most significant bit first. Repeat this step
to input the value 1101001 after the second reset pulse.

To edit the input waveform for y_in:

• Input the value 0111 after the first reset pulse with the most significant bit first. Repeat this step
to input the value 1101111 after the second reset pulse.

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Some of the final waveforms are shown below:

Figure 10: Sample input waveforms

• Save the changes by choosing Save (File menu) or simply click on the disk button in the
horizontal toolbar.

• Choose Simulator (MAX+PLUS II menu).

• Click on Start to start the timing simulation.

4.3 Timing Simulation using a Vector File (.VEC)

In this part of the tutorial you will perform a timing simulation of the binary sorting node using a vector
file. Note that this is an alternative procedure to the one outlined above that uses a Simulator Channel File.

• Make sure that the design of the binary sorting node has been compiled with the Timing SNF
Extractor option turned ON (see section 4.1).
• Choose New (File Menu), select Text Editor File and choose OK to open an untitled Text
Editor window.
• Choose Save As (File Menu). Type binary_sort.vec in the File Name box. Choose OK.
• Type in the vector file as shown in Appendix B of this tutorial.
• Choose Save (File Menu).
• Choose Simulator (MAX+PLUS II menu).
• Click on Simulation input.
• Select binary_sort.vec as the input file and choose OK. The simulator will generate an SCF
file. Choose OK to continue.
• Click on Start to start the timing simulation.
• Choose OK to continue. If there are any errors or warnings you must go back and check that
you entered the vector file correctly.
• Click on Open SCF to view the results of the timing simulation.
• Choose Fit in Window (View menu) to fit the entire simulation in the Waveform Editor.

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 5. MAX+PLUS II Timing Analyzer
The MAX+PLUS II Timing Analyzer permits you to analyze the performance of a design after it is
synthesized by the Compiler. You can use the Timing Analyzer to calculate a matrix of point-to-point
device delays, determine setup and hold time requirements at device pins, and calculate maximum clock
frequency.

5.1 Registered Performance

The Timing Analyzer’s Registered Performance Display shows the worst-case registered performance, i.e.,
the maximum clock frequency for every clock signal in the circuit. The Registered Performance Display
measures the maximum delay from the Q output of all flip-flops to the data and clock enable of all other
flip-flops, including:

• Clock-to-output delay of the source flip-flop.

• Combinatorial and interconnect delays between the source and destination flip-flops.
• Internal setup time of the destination flip-flop.

Figure 11: Registered performance window

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5.2 Determining the Critical Path

• Choose Timing Analyzer (MAX+PLUS II menu).

• Choose Registered Performance (Analysis menu).
• Click on Start to run the timing analyzer.
• Record the maximum operating frequency of the binary sorting node and determine where the
longest delay path (critical path) occurs in the circuit.

Note: You can use the options in the Time Restrictions dialog box (Options menu) to list either all paths
that fail to meet a specified clock frequency or a specified number of paths. After the Timing Analyzer
finds the longest delay paths, you can view the information on the paths by choosing List Paths. You can
choose Locate to locate and highlight each signal path in your VHDL file.

Q1: What is the maximum operating frequency of the binary sorting node?

Q2: Where is the longest delay path (critical path) in the circuit? State briefly where this path lies in the
block diagram. Report all of them, if there are more than one path.

Figure 12: Time restrictions window

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5.3 Using the Delay Matrix
The Delay Matrix display shows the minimum/maximum propagation delays between source nodes and
destination nodes in the current project. A single delay time means all delay paths are of the same length.
To exclude the minimum or maximum delays from the display, and to restrict the lengths of the delay paths
used for the analysis, follow the notes in section 5.2 about setting the options in the Time Restrictions
(Option menu).

• Choose Timing Analyzer (MAX+PLUS II menu).

• Choose Delay Matrix (Analysis menu).
• Click on Start to run the timing analyzer.
• Record the maximum propagation delay in the circuit and locate where it occurs. If there are
more than one path, record all of them.

Q3: What is the maximum propagation delay in the binary sorting node? What maximum operating
frequency does this delay imply? Look for the meaning of this type of delay in the On-line Help.

Q4: Where is this maximum delay located? State briefly where this path lies in the block diagram.
Report all paths if there are more than one path.

Q5: Are the maximum operating frequencies obtained from Q1 and Q3 the same? Which frequency will
you use to clock the circuit and why?

Figure 13: Delay matrix display

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 6. Analyzing Synthesis Results (.RPT file)
The report file is a text file which contains useful information on how a design is implemented in a target
programmable logic device. To view the .RPT file, click on the RPT icon corresponding to the entity in the
hierarchy tree of the current project. Alternatively, you may double-click on the report file icon in the
compiler window.

Information on the project as a whole (e.g. name of the target device, no. of user I/O pins, percentage of the
resources used in the device) and project compilation messages are listed first.

Next, the device specific information follows. A pin-out diagram of the target device shows the mapping of
user I/O, VCC, GND and special purpose signals to the physical pins on the chip. The resource usage
section provides a concise description of how the device uses available resources. The fan-in and fan-out
statistics of all input, output, buried (internal), clock and clear signals are listed.

At the end of the .RPT file is a summary of the compilation and logic synthesis settings used for the
current design.

Q6: What is the percentage of resources (e.g., Logic Cells, I/O pins) that are used for the binary sorting
node? Include only appropriate sections of the report file.

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 7. Changing Compiler Settings
7.1 Viewing logic synthesis equations
Optional sections can be included in the report file. A more detailed report file can help you locate errors in
a project that does not compile successfully.

• Invoke the Compiler and choose Report File Settings (Processing menu). Turn on the
Equations option to include the synthesized logic equations in the report file.
• Recompile the project and view the report file.

The Equations section provides the results of extensive logic synthesis. Since synthesis minimizes the logic
required to implement a design, redundant or unnecessary logic in the original design may not appear in the
report file.

Hint: Since the Equations section in the report file can be very lengthy, it is generally sufficient to turn on
only the User Assignments and File Hierarchy options in the Report File Settings.

7.2 Optimizing logic synthesis for speed

Hardware designers are often faced with the speed-area trade-off. Here, we briefly look at the effect of
optimizing the synthesis of the design for speed.

• Choose Global Project Logic Synthesis (Assign Menu) to display its dialog box.
• Under Optimize, move the scroll bar towards Speed until it reads 10. Click OK to confirm
changes.
• Recompile the project.

Q7: What are the effects of this optimization on the timing performance (registered performance and
delay matrix) and resource usage? Give a brief explanation on your answer.

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 8. Guidelines

Here are some guidelines that might be useful while using the MAX+PLUS II development system.

• You are strongly encouranged to use the resources on the course web page. The URL is on the
front page of this manual.

• MAX+PLUS II on-line help contains all of the MAX+PLUS II documentation that comes with
the development system. Therefore, you should consult the on-line help whenever you
encounter a problem.

• Use only lower case characters for all filenames.

• The entity name in your VHDL description must be the same as the filename.

• Do not label any signal I/O port with the same name as an entity.

• Use the Compiler's Design Doctor utility to check the reliability of your design against one or
more selected design rules.

• Introduction to the toolbar shortcuts:

1 2 3 4 5 6 7 8 9

The toolbar is located along the top of the MAX+PLUS II window. When you put the mouse
pointer over any button in the toolbar, a one-line description of the button function will appear at
the lower-left corner of the MAX+PLUS II window. Clicking on toolbar buttons allow you to
quickly access various MAX+PLUS II applications and options.

Button 1: Opens the Hierachy Display window.

Button 2: Opens the Floorplan Editor window, which allows you to view and edit pin and
logic cell assignments for the current design.

Button 3: Opens the Compiler window.

Button 4: Opens the Simulator window.

Button 5: Opens the Timing Analyzer window.

Button 6: Opens the Programmer window, which together with the appropriate hardware
allows you to program Altera devices.

Button 7: Changes the name of the current project.

Button 8: Sets the current file to be the current project.

Button 9: Opens the top-level file of the current project.

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 • You may use the Altera VHDL library to implement standard functions such as counters,
multiplexors, shift registers etc. Select the Old-Style Macrofunctions option (Help menu) to
get more details. All VHDL component declarations of the standard library can be found in:
/local/maxplus2/vhdl93/altera/maxplus2.vhd.

To reduce development time, you should use MAX+PLUS II's Library of Parameterizable
Modules (also called LPM functions). By specifying a set of parameters, known as generics,
you can customize these modules to the specification or functionality of the components in your
design (e.g. the no. of I/O ports, the width of each port). For more details, select the
Megafunctions / LPM option (Help menu).

• MAX+PLUS II only supports a subset of the VHDL language. Therefore, you must check
whether a certain feature is supported by MAX+PLUS II before you can use it. You can do this
by selecting the VHDL option (Help menu).

• MAX+PLUS II provides VHDL templates as an easy and accurate way for you to enter VHDL
syntax. Once you have inserted a template into VHDL file, you must replace all variables with
your own logic. Each variable name start with double underscore (__) and each keyword is
capitalized. To insert a VHDL construct, position your cursor at the desired location in your
VHDL file. Select VHDL Template (Templates menu) to bring up the VHDL Template dialog
box. Then choose the desired construct from the list.

• Syntax Coloring highlights comments, keywords, identifiers etc. in different colours on the
screen. Hence, it may be useful when editing and debugging your code. To enable this feature,
select the Syntax Coloring option from the Options menu.

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 9. Resources
• Altera Data Book 1996
• Altera MAX+PLUS II Getting Started
• Altera MAX+PLUS II VHDL
• Altera MAX+PLUS II On-line Help
• "A VHDL Primer", Revised Edition, by Jayaram Bharsker, 1995.
• "The Designer's Guide to VHDL", by Peter J. Ashenden, Morgan-Kaufman Publishers, 1995.
• "Digital Systems Design and Prototyping Using Field Programmable Logic", by Zoran Salcic
and Asim Smailagic, Kluwer Academic Publishers, 1997.
• "VHDL and FPLDs in Digital Systems Design, Prototyping and Customization", by Zoran
Salcic, Kluwer Academic Publishers, 1998.
• Computer Architecture Lab home page (www.ece.mcgill.ca/~ta487)
• Altera home page (www.altera.com)

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Appendix A - VHDL Description
-----------------------------------------------------------------------------
-- Filename : binary_sort.vhd
-- Title : Binary Sorting Node Entity
-- Authors : Boonchuay Supmonchai & Ted Szymanski
-- Date : May 1996
-- Revision : None
-- Description : See figure 1 on page 3 of this manual
-----------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL; -- definitions for allowable logic signals, etc.

ENTITY binary_sort IS
PORT (
x_in, y_in : IN STD_LOGIC; -- Group of inputs
x_out, y_out : OUT STD_LOGIC; -- Group of outputs
reset : IN STD_LOGIC; -- Group of controls
clock : IN STD_LOGIC
);
END binary_sort;

ARCHITECTURE structure OF binary_sort IS

-- Components shown in Figure 1 : Functional Block Diagram

-- COMPONENT statements declare the I/O ports of entities to

-- be used without instantiating any of the entities.

-- In Altera's MAX+PLUS II, the VHDL code for each component

-- must be saved in a file of the same name with postfix ".vhd"

COMPONENT state_machine
PORT (
upper, lower : IN STD_LOGIC;
exchange : OUT STD_LOGIC;
reset : IN STD_LOGIC;
clock : IN STD_LOGIC
);
END COMPONENT;

COMPONENT mux21
PORT (
a, b : IN STD_LOGIC;
c : OUT STD_LOGIC;
select1 : IN STD_LOGIC
);
END COMPONENT;

487 Computer Architecture Lab Page 23 January 12, 2001

COMPONENT dffr
PORT (
D : IN STD_LOGIC;
Q : OUT STD_LOGIC;
reset : IN STD_LOGIC;
clock : IN STD_LOGIC
);
END COMPONENT;

-- Define "binary_sort" entity's internal nets or wires

SIGNAL exchange : STD_LOGIC;

SIGNAL upper, lower : STD_LOGIC;
SIGNAL x, y : STD_LOGIC;

-- In the next section, we have a "structural" description of the circuit shown

-- in figure 1. We instantiate the seven components and interconnect these
-- components by entering the appropriate signals in the I/O list of each
-- component

BEGIN

UPPER_INPUT: dffr PORT MAP (x_in, upper, reset, clock);

LOWER_INPUT: dffr PORT MAP (y_in, lower, reset, clock);

STATE_MACHINE1: state_machine PORT MAP (upper, lower, exchange, reset, clock);

UPPER_MUX : mux21 PORT MAP (upper, lower, x, exchange);

LOWER_MUX : mux21 PORT MAP (lower, upper, y, exchange);

UPPER_OUTPUT : dffr PORT MAP (x, x_out, reset, clock);

LOWER_OUTPUT : dffr PORT MAP (y, y_out, reset, clock);

END structure;

487 Computer Architecture Lab Page 24 January 12, 2001

-----------------------------------------------------------------------------
-- Filename : state_machine.vhd
-- Title : State Machine of the Binary Sorting Node Entity
-- Authors : Boonchuay Supmonchai & Ted Szymanski
-- Date : May 1996
-- Revision : None
-- Description : See figure 2 on page 4 of this manual.
-----------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL; -- definitions for allowable logic signals, etc.

ENTITY state_machine IS
PORT (
upper, lower : IN STD_LOGIC;
exchange : OUT STD_LOGIC;
reset : IN STD_LOGIC;
clock : IN STD_LOGIC
);
END state_machine;

ARCHITECTURE behavior OF state_machine IS

TYPE STATE_TYPE IS (X_equal_Y, X_less_than_Y, X_greater_than_Y);

SIGNAL present_state, next_state : STATE_TYPE;

-- In the next section, we have a "behavioral" description of the finite state

-- machine shown in figure 2 of this manual

BEGIN

PROCESS(present_state, upper, lower)

BEGIN

CASE present_state IS

WHEN X_equal_Y =>

IF (upper > lower) THEN
next_state <= X_greater_than_Y;
ELSIF (upper < lower) THEN
next_state <= X_less_than_Y;
ELSE
next_state <= X_equal_Y;
END IF;

WHEN X_less_than_Y =>

next_state <= X_less_than_Y;

WHEN X_greater_than_Y =>

next_state <= X_greater_than_Y;

END CASE;

END PROCESS;

487 Computer Architecture Lab Page 25 January 12, 2001

 PROCESS(clock, reset)
BEGIN

IF (reset = '1') THEN

present_state <= X_equal_Y;
ELSIF (clock'EVENT) AND (clock = '1') THEN
present_state <= next_state;
END IF;

END PROCESS;

-- exchange is the control signal for multiplexor

exchange <= '1' WHEN next_state = X_greater_than_Y ELSE '0';

END behavior;

487 Computer Architecture Lab Page 26 January 12, 2001

-----------------------------------------------------------------------------
-- Filename : dffr.vhd
-- Title : D-Flipflop with asynchronous reset (clear)
-- Authors : Boonchuay Supmonchai & Ted Szymanski
-- Date : May 1996
-- Revision : None
-- Description: See section 2.1 of the manual
-----------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY dffr IS
PORT (
D : IN STD_LOGIC;
Q : OUT STD_LOGIC;
reset : IN STD_LOGIC;
clock : IN STD_LOGIC
);
END dffr;

ARCHITECTURE behavior OF dffr IS

-- In the next section, we have a "behavioral" description of a D-flipflop

BEGIN

D_FF : PROCESS (clock, D, reset)

BEGIN

IF (reset ='1') THEN

Q <= '0';
ELSIF clock'event AND (clock = '1') THEN
Q <= D;
END IF;

END PROCESS D_FF;

END behavior;

487 Computer Architecture Lab Page 27 January 12, 2001

-----------------------------------------------------------------------------
-- Filename : mux21.vhd
-- Title : One-bit-wide 2-to-1 Multiplexor
-- Authors : Boonchuay Supmonchai & Ted Szymanski
-- Date : May 1996
-- Revision : None
-- Description : See section 2.1 on page 3 of this manual
-----------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY mux21 IS
PORT (
a, b : IN STD_LOGIC;
c : OUT STD_LOGIC;
select1 : IN STD_LOGIC
);
END mux21;

ARCHITECTURE behavior OF mux21 IS

-- In this section, we have a "behavioral" description of a 2-to-1 Multiplexor

BEGIN

MULTIPLEXOR : PROCESS(a, b, select1)

BEGIN

IF (select1 = '1') then

c <= b;
ELSE
c <= a;
END IF;

END PROCESS MULTIPLEXOR;

END behavior;

487 Computer Architecture Lab Page 28 January 12, 2001

Appendix B - Vector File: binary_sort.vec
% Units default to ns. Input values are interpreted in hexadecimal format by
default. %

% Specify start and stop time of simulation. %

START 0;
STOP 2000;

% Clock ticks every 50 ns i.e., clock period = 100 ns. %

INTERVAL 50;
INPUTS clock;
PATTERN
0 1; % Relative vector values %

INPUTS reset;
PATTERN
0> 1
100> 0 % Absolute time vector values %
800> 1
900> 0
;

INPUTS x_in;
PATTERN
0> 0
100> 1
300> 0
400> 1
500> 0
900> 1
1100> 0
1200> 1
1300> 0
1500> 1
1600> 0
;

INPUTS y_in;
PATTERN
0> 0
200> 1
500> 0
900> 1
1100> 0
1200> 1
1600> 0
;

% Output traces %

OUTPUTS x_out y_out;

487 Computer Architecture Lab Page 29 January 12, 2001

Appendix C - Conventions on writing VHDL documentation
In a large project with multiple contributors it is essential to have well documented professional code. The
code should be easy to locate, understand and maintain by a person other than the original author. The code
should facilitate "re-use", i.e., it should be structured into modules which can be reused by other members
in other parts of the project. The following conventions are expected in your assignments and projects.

Convention 1: Each VHDL file will start with a consistent professional-style header.

Convention 2: The entity and corresponding architecture description must be kept in the same file.

Convention 3: The name of the file should match the entity name with a .vhd suffix to facilitate easy
location and maintenance.

Convention 4: When applicable, the name of the architecture should be the same as the entity plus the
modelling style. If the entity name is "toto" and the architectural modelling style is "structural", then the
architecture name would be "toto_struct".

Convention 5: The header for an entity with a structural description will refer the reader to a structural
diagram in the report, unless the entity is trivial. The structural diagram will illustrate every internal
component and every I/O of the entity. An entity with a behavioral description may not have a structural
diagram. In this case, the entity must be a component of some higher level entity that does have a structural
diagram containing this entity. The header will refer the reader to the appropriate higher level entity's
structural diagram.

Convention 6: For highly repetitive blocks, do not use signals to interconnect. Use port connections
directly. This will minimize the amount of VHDL code and be easier to understand and maintain.

Convention 7: Instantiations using the generate statement should be port mapped positionally, not using
named association, i.e., no arrows.

Convention 8: In an entity definition, the ports of the entity should be grouped and listed in the following
sequence: inputs, outputs and control.

487 Computer Architecture Lab Page 30 January 12, 2001

Appendix D - FAQ Table of Content
Frequently Asked Questions - GENERAL
1. About MAX+PLUS II (Lab version)
2. About Altera DSP Kit ver. 1.0
3. How do I simulate vectors?
4. How do I print to the printer in 818 from MAX+PLUS II?
5. Design Methodology
6. Useful Hints
7. Reducing Compilation Time - Global Synthesis Options
8. Reducing Compilation Time - Compiling to AHDL
9. Using Long Filenames in Maxplus2 7.21
10. How do I change the font in the Text Editor?
11. How do I change the position of the Tab Stops?
12. What is Syntax Coloring?
13. How do I get the Motif/Windows look?
14. How do I simulate multiple devices?
15. How do I use MAX+PLUS II's command line mode?
16. Is there a template for IEEE format papers?

Frequently Asked Questions - VHDL

1. How do I use MAX+PLUS II VHDL Library Components
2. How do I use MAX+PLUS II LPM Components
3. How do I use AHDL Floating Point Components
4. Where can I find VHDL language references?
5. How do I initialize signals?
6. How do I access bits within a STD_LOGIC_VECTOR?
7. How do I shift bits in a STD_LOGIC_VECTOR?
8. How do I perform arithmetic on a STD_LOGIC_VECTOR?
9. How do I use VHDL variables?
10. How do I create VHDL packages?
11. How do I create VHDL functions and procedures?
12. How do I use VHDL revision 1993?
13. How do I use hexadecimal notation in VHDL?
14. How do I use STD_LOGIC_2D?
15. How do I implement a state machine?
16. How do I check for a signal's rising or falling edge?
17. What VHDL libraries are available in MAX+PLUS II?
18. How do I find MAX+PLUS II's VHDL examples?

487 Computer Architecture Lab Page 31 January 12, 2001