DOC/LP/O1/25.07.

2005

LESSON PLAN
Sub Code & Name: CS Unit: I

LP-CS9211 LP Rev. No: 00 Date: 1.7.2009 I Page 1 of 6

9211 Computer Architecture

Semester:

Branch: CSE

UNIT 1 Fundamental of Computer Design and Pipelining Fundamentals of Computer Design Measuring and reporting performance Quantitative principles of computer design. Instruction set principles Classifying ISA Design issues. Pipelining Basic concepts Hazards Implementation Multicycle operations. Objective: The students learn various performance metrics that are used to evaluate the efficiency and speedup of the computers. Various addressing mode and the instruction set design principles are explored here. To understand the design issues in the computer architecture, the case studies like MIPS are discussed in detail. For Example, instruction execution cycle, instruction set architecture [ISA] and Speedup of Architecture is discussed. The students also learn the basic principles of pipelining and hazards that derail the pipelining process. The Data Dependence and Control Dependence that affect the pipelining are explored in detail. Session No 1 2 3 4 5 6 7 8 9 10 11 Topics to be covered Cost of integrated circuits, Measuring and Reporting performance Quantitative principles of computer design Amdahls Law and Speedup. Measuring and Modeling the components of the CPU Performance Equation. Fallacies and Pitfalls. Instruction Set Principles. Memory addressing and Memory addresses. Addressing modes for signal processing Operands and Operation for signal processing and media. Instructions control flow Encoding an Instruction set Recent Compilers MIPS architecture and Register model Basics of pipelining. And Hazards RAW, WAR, WAW Hazards Tutorial Time Allocation 50m 50m 50m 50m 50m 50m 50m 50m 50m 50m 50m Books Referred 1,2 1,2 BB 1,2 BB 1,2 BB 1,2 BB 1,2 BB 1,2 1,2 1,2 1,2 1,2 BB BB BB BB BB Teaching Method BB

DOC/LP/O1/25.07.2005

LESSON PLAN
Sub Code & Name: CS Unit: II

LP-CS9211 LP Rev. No: 00 Date: 1.9.2009 I Page 2 of 6

9211 Computer Architecture

Semester:

Branch: CSE

UNIT II INSTRUCTION LEVEL PARALLELISM WITH DYNAMIC APPROACHES Concepts Dynamic Scheduling Dynamic hardware prediction Multiple issue Hardware based speculation Limitations of ILP Case studies. Objective: The Tomasulos approach for dynamic scheduling and branch prediction techniques with BTB are discussed. Example architecture:IP6 Architecture are discussed to illustrate the above concepts. Session No 12 13 14 15 16 17 18 19 20 21 22 Topics to be covered Data dependence and Hazards Control dependence and Dynamic scheduling Dynamic scheduling using Tomasulos Algorithm. Correlating Branch Predictors Branch prediction and Branch Target Buffer. Hardware Based speculation Multiple Issue with Speculation Limitations of Instruction level Parallelism IP6 Micro architecture Tutorial CAT- 1 50m 50m 50m 50m 60m 1,2 1,2 1,2 1,2 BB BB BB BB Time Allocation 50m 50m 50m 50m 50m 50m Books Referred 1,2 1,2 1,2 1,2 1,2 1,2 Teaching Method BB BB BB BB BB BB

DOC/LP/O1/25.07.2005

LESSON PLAN
Sub Code & Name: CS Unit: III

LP-CS9211 LP Rev. No: 00 Date: 1.9.2009 I Page 3 of 6

9211 Computer Architecture

Semester:

Branch: CSE

UNIT III INSTRUCTION LEVEL PARALLELISM WITH SOFTWARE APPROACHES Compiler techniques for exposing ILP Static branch prediction VLIW Advanced compiler support Hardware support for exposing more parallelism Hardware versus software speculation mechanisms Case studies. Objective: The students are exposed to ILP at the compiler levels. The Static branch prediction and multiple instruction issue techniques enhance parallelism. The hardware based speculation and software based speculation are discussed in detail. The IA64 and Itanium Processor exhibit the Instruction Level Parallelism in them. Session No 23 24 24 25 26 27 28 29 30 31 32 Topics to be covered Compiler Techniques for exposing ILP Static Branch Prediction Techniques Very Large Instruction Word approach Advanced Compiler Support Software pipelining and Trace scheduling Super Blocks Compiler speculation with Hardware support Intel IA-64 Architecture Itanium Processor Model Comparison of IA64 and Itanium Processor Model Tutorial Time Allocation 50m 50m 50m 50m 50m 50m 50m 50m 50m 50m 50m Books Referred 1,3 1,3 1,3 1,3 1,3 1,3 1,3 1,3 1,3 1,3 1,3 Teaching Method BB BB BB BB BB BB BB BB BB BB BB

DOC/LP/O1/25.07.2005

LESSON PLAN
Sub Code & Name: CS Unit: V

LP-CS9211 LP Rev. No: 00 Date: 1.9.2009 I Page 5 of 6

9211 Computer Architecture

Semester:

Branch: CSE

UNIT V MEMORY AND I/O Cache performance Reducing cache miss penalty and miss rate Reducing hit time Main memory and performance Memory technology. Types of storage devices Buses RAID Reliability, availability and dependability I/O performance measures Designing an I/O system. Objective: The students learn the Memory Hierarchy and the average access time associated with each memory level. The performance analyses for cache memory are done in detail. The techniques that can be used to reduce the miss penalty, hit time and missrate are discussed in detail. The virtual memory concepts and address translation techniques are explored here. The Types of IO devices and the bandwidth utilization of IO devices when it is interfaced with bus interfaces like SCSI and PCI are discussed in detail. Merits of RAID are outlined here. IO performance measures and designing of IO system when requirement specification for SCSI, System Bus, HDD and CPU clock rate are given. Session No 47 48 49 50 51 52 53 54 55 56 57 Topics to be covered Cache performance Average memory access time and processor performance Miss penalty and out of order execution. Reducing cache miss penalty Reducing miss rate Loop interchange and Blocking Reducing hit time and Virtual memory Types of Storage devices-SCSI,PCI Buses interface and Bus Protocols Synchronous and Asynchronous Bus Protocols RAID and Little queuing theory analysis for IO system. Designing IO System Tutorial CAT 2 Time Allocation 50m 50m 50m 50m 50m 50m 50m 50m 50m 50m 60m Books Referred 1,4 1,4 1,4 1,4 1,4 1,4 1,4 1,4 1,4 1,4 Teaching Method BB BB BB BB BB BB BB BB BB BB

DOC/LP/O1/25.07.2005

LESSON PLAN
Sub Code & Name: CS Unit: IV

LP-CS9211 LP Rev. No: 00 Date: 1.9.2009 I Page 4 of 6

9211 Computer Architecture

Semester:

Branch: CSE

UNIT IV MULTIPROCESSORS AND MULTICORE ARCHITECTURES Symmetric and distributed shared memory architectures Performance issues Synchronization issues Models of memory consistency Software and hardware multithreading SMT and CMP architectures Design issues Case studies. Objective: Here the students learn the basic principles of the cache coherence protocols. The concepts like Temporal and spatial Locality of reference are dealt in detail. The functioning of the cache coherence protocol in the centralized and distributed environment is illustrated with examples. The synchronization of instruction execution and memory consistency model with their weakness are discussed in detail. The basic concepts of multithreading are dealt in detail.

Session No 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Topics to be covered Taxonomy of parallel architectures Models for communication and memory architecture. Bottlenecks in communication protocols Symmetric shared memory architectures Snooping protocols Performance issues in the Symmetric shared memory systems. Distributed shared memory architectureIntroduction Performance issues in DSMA Synchronization-Introduction. Locks and Barrier synchronization Models of Memory consistency Strict, weak and release consistency models Introduction to Multithreading SMT and CMP architectures Design issues Case studies. Threads creation and identification

Time Allocation 50m 50m 50m 50m 50m 50m 50m 50m 50m 50m 50m 50m 50m 50m

Books Referred 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2

Teaching Method BB BB BB BB BB BB BB BB BB BB BB BB BB BB

DOC/LP/O1/25.07.2005

Course Delivery Plan: Week Units 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

I II I II I II I II I II I II I II I II I II I II I II I II I II I II I II

REFERENCES: 1. John L. Hennessey and David A. Patterson, Computer Architecture A quantitative approach, Morgan Kaufmann / Elsevier, 4th. edition, 2007. 2. David E. Culler, Jaswinder Pal Singh, Parallel Computing Architecture : A hardware/ software approach , Morgan Kaufmann / Elsevier, 1997. 3. William Stallings, Computer Organization and Architecture Designing for Performance, Pearson Education, Seventh Edition, 2006. 4. Behrooz Parhami, Computer Architecture, Oxford University Press, 2006.

Prepared by Signature Name Designation Date V SHASHIKIRAN Faculty 1/9/2009

Approved by Dr Susan Elias HOD/CS 1/9/2009