A Digital Boost Converter to Drive White LEDs

Wei-Hsu Chang, Dan Chen*, Hung-Shou Nien and Chih-Hung Chen RichTek Technology Corp. 5F, No. 20, Taiyuan Street, Chupei City, Hsinchu, Taiwan, R. O. C. E-mail: William_Chang@richtek.com Tel: 886-3-5526789 ext 2630 Abstract-- A constant off-time boost converter with digital control was proposed and implemented with a field-programmable-gate-array (FPGA) to power white light emitting diodes (WLEDs) for hand-held applications. In the application, a lithium-ion battery with voltage ranging from 3.3 V to 4.2 V was used to light a serial connection of 4 WLEDs drawing current levels from 2 mA to 20 mA. A constant off-time digital PWM controller was chosen to increase the dimming resolution. For the compensator design, a small-signal control model for the constant off-time converter was presented. A digital PI compensator with programmable gain was used to stabilize the control loop for different LED current levels. Experimental results are presented. Same design considerations apply to other applications if a digitally-controlled boost or buck/boost converter with high conversion gain is used. I. INTRODUCTION
*

Department of Electrical Engineering National Taiwan University Taipei, Taiwan, R. O. C. E-mail: chend@cc.ee.ntu.edu.tw Tel: 886-2-33663542

WLEDs with approximately 13.5 Volts total drop was powered by a lithium-ion (Li-ion) battery with voltage in the range of 3.3 V to 4.2 V. In the circuit, dimming of the light level is accomplished by controlling the LED current. In the paper, a comparison of the three controller types, constant frequency, constant on-time and constant off-time will be given first. A constant off-time controller was proposed and implemented for this application using an FPGA. A small-signal S-domain model of a constant off-time boost converter will be given for the purpose of digital compensator design. Experimental waveforms and control loop gains of the breadboard will be shown. II. DIGITAL PULSE-WIDTH MODULATORS Fig. 1 shows the circuit diagram of a digitally-controlled boost converter powering 4 WLEDs. The feedback operation is described in the following. The output voltage of the converter, vo, is connected to the load which includes the WLED string and the sensing resistor Rs. The sensed voltage vs(t) is discretized and quantized to vs[n] by the analog-to-digital converter (ADC). The subtraction of the sampled voltage vs[n] from the reference voltage Vref results in the error signal, err[n]. The digital compensator picks up err[n] and generates a
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The subject of DC power converters with digital control schemes has been a hot research area in recent years [1-6]. The present paper focuses on issues of a digitally-controlled inductor-based boost converter for white light emitting diode (WLED) applications in hand-held devices. A serial connection of 4
978-1-4244-1874-9/08/$25.00 2008 IEEE

command/duty ratio d[n] to digital pulse-width-modulator (DPWM) block which generates a pulse, d(t), in continuous-time domain at the next switching cycle. To avoid limit cycle oscillation in a digital control circuit [7,8], the per-unit increment of the sensed voltage caused by one least significant bit (LSB) change in the DPWM duty cycle output has to be smaller than the analog equivalent of the LSB of the analog-to-digital converter. That is, the relationship between per-unit change of ADC and per-unit change of DPWM should satisfy Eq. (1). v S > v g M Hs (1)

Constant-Frequency Control The voltage conversion gain, M, of a boost converter with a constant-frequency control is given by Eq. (2).

M ( D) =

1 . 1 D

(2)

By taking the differential on both sides of Eq. (2) and setting D to be one unit, one can get Eq. (4).
M ( D ) = 1 . (1 D ) 2

(4)

Eq. (4) expresses the per-unit change of conversion gain due to per-unit change of duty cycle. It can be seen from Eqs. (1) and (4) that its more difficult to satisfy Eq. (1) at higher D value. For a boost converter with high conversion gain, D is relatively large and therefore more difficult to satisfy Eq. (1) unless vS is increased. This means the resolution of the dimming control would be reduced or a higher-number-of-bit ADC is required. Since D varies with input voltage and load current, and the fact that M ( D ) depends on D with high nonlinearity, a constant-frequency controller is not a good choice for such an application. Constant On-Time Control With a constant on-time control, Eq. (3)

vS and M are, respectively, the per-unit change analog voltage of the ADC, and the per-unit change of voltage conversion gain when the DPWM duty cycle is changed by one-unit. Hs is the output voltage sensing gain, D is the duty cycle of the switching, and vg is the input voltage. The DPWM block can be implemented with a constant-frequency, constant on-time, or constant off-time control. However, a comparison of the three control schemes will be made in the following.

substituted into Eq. (2) can be rewritten as Eq. (5). T M (Toff ) = 1 + on , (5) Toff where Ton = N on Tck (6) (7)

Toff = N off Tck .

Where Non and Noff are integers, and Tck is the

Fig.1. Block diagram of a voltage-mode digital boost converter.

DPWM clock period. Since the on-time is fixed, Eq. (5) can be expressed as

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M (Toff ) =

N on N off
2

(8)

K vd =

Vg (1 D) 2

(11)

From Eq. (8), M depends on Noff with high nonlinearity. The problem associated with dimming resolution encountered in a constant-frequency controller also applies in a constant on-time controller. Constant Off-Time Control Taking the differential of both sides of Eq.

Where Kvd denotes a DC gain, z is capacitor ESR zero and a is the inductor zero, 0 is resonance-frequency pole and Q is the quality factor. D can be calculated under certain DC operating condition. B. Load Model and Sampling Gain HS The load consists of a sensing resistor and WLED string, as shown in Fig. 3(a). A WLED model was obtained from [10]. The small-signal model of a WLED string series

(5) with a constant Toff, the per-unit change of M can be expressed as in Eq.9. 1 . M (Ton ) = N off (9)

From, Eq. (9), M is independent of control variable Ton. Once Noff is selected in a design, dimming resolution is independent of operating condition of the converter. This also often leads to smaller ADC bit requirement. For this reason, the constant off-time controller is chosen for this application. III. SMALL-SIGNAL MODEL AND COMPENSATOR DESIGN FOR A CONSTANT OFF-TIME CONTROLLER For feedback compensator design, a digital small-signal S-domain model for boost converter was developed, as shown in Fig. 2. The model of each major block in the system is described in this section. A. Control-to-Output Transfer Function Gvd(s) The control-to-output voltage transfer function of a boost converter is shown in Eq. (10) [9].

with a sensing resistor is depicted in Fig. 3(b). From Fig. 3(b), the transfer function of sampling gain HS(s) can be expressed as Eq. (12). v H S (s) = s o v a s + a0 = 1 , (12) b1s + b0 where a1 = b1 = RS RWD (io ) CWD , (13) (14) (15)

a0 = RS , b0 = RS + RWD (io ) .

Where RWD is equivalent resistance of a WLED string, CWD is equivalent capacitance of a WLED string, io is the load current through WLED string, and RS is the sensing resistance. Fig. 4 shows the frequency response of the sampling gain HS(s). Notice that there is a noticeable phase-shift in the gain due to the fact that RWD varies with io, and a resonant peak in the phase due to CWD effect, indicating that the LED is not purely resistive. For a convenient design, the sampling gain can be simplified as Eq. (16) under worse case (light load). v RS , (16) HS = s = o RS + RWD (io ,min ) v where io,min is the minimum load current.

s s )(1 ) z a Gvd ( s ) = K vd , s s 2 1+ +( ) Q 0 0 (1 +
where

(10)

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C. ADC and DPWM Transfer Function, GADC(s) and GDPWM(s) Using the S-domain approach [6] to model the digital control, the ADC transfer function is shown in Eq. (17). The transfer function of a constant off-time control can be obtained by using the results from [11] and the approach of [6]. The result is shown in Eq. (18).

where Ts is the sampling frequency which is equal to switching frequency, A is the compensator constant gain, and Td is the compensator calculation time. The open-loop gain of the converter is shown in Eq. (22).

T ( s) = Gvd ( s) G ADC ( s) GDPWM (s) Gc ( s) H s , (22)

where the total delay time in the digital control is equal to TADC+Td+DTS. More details about delay time contribution are described in [6].
Vref
d

G ADC ( s ) = K ADC e

sTADC

(17) (18)

GDPWM ( s) = Goff ( s)e sDTS .

Where
j2 ms (Ton + Toff ) sTon / 2 , Goff ( s ) = e (Ton + Toff ) s sin j2 sin Toff

e sT d

e sDTs

o v

(19)

e sTADC

v s [n]

s v

where KADC is the ADC sampling gain, ms is the up-slope of the ramp signal, Ton and Toff are the on- and off-time at steady-state, respectively.

Fig. 2. Small-signal behavior model for digital boost converter. o vo + v

e sTADC and e sDTS are respectively the ADC conversion delay time and the DPWM sampling delay time in the digital control.
C. Digital Compensator GC(s) In a WLED driver application, fast transient response is not a critical issue. Therefore, a first-order digital PI (Proportional and Integration) compensator was used as the compensator. The transfer function represented by z-transform is d ( z) A = . (20) err ( z ) 1 z 1 For the design of the compensator in continuous-time domain, Eq. (20) was transformed by Gcomp ( z ) = bilinear transform, and the result is shown in Eq. (21). s ( + 1) A 2 / Ts (21) Gc ( s ) = e sTd , Ts s

o i

s vs + v

(a)

o v

s v

(b) Fig. 3. (a) Circuit configuration and (b) small-signal model of WLEDs series with sensing resistor.

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loop-gain Bode plots, from which one can be seen that bandwidth and phase margin (PM) are 400 Hz and 60 degree. This controller has been demonstrated to work satisfactorily with the WLED load.
Table 1. Hardware parameter values. Specifications Switching Frequency (fs) Input Voltage (vg) Output Voltage (vo) Output Current (io) Parameters 117~195 kHz 3.3 V 3.3~16 V 2 ~20 mA 440 uH 64 m 390 uF 40 m Xilinx Spartan-3E 11 bits 150 MHz 4.68 MHz 12.5 MHz

Fig. 4. Frequency response of sensing gain Hs, in which load condition is 4 WLEDs and Rs=25.

Inductance (L) ESR of L (RL) Capacitance (C) ESR of C (RC) Controller (FPGA) Resolution bits of DPWM DPWM clock rate(1/Tck) Calculation Clock Frequency ADC Sample Rate (1/TADC)

IV. SIMULATION AND EXPERIMENTAL RESULTS A Xilinxs SPARTAN-3E FPGA was used to implement the proposed digital constant off-time pulse-width modulator. Table 1 shows the breadboard parameters. Resolution bits of DPWM and ADC are 11 bits and 8 bits, respectively. A PI compensation was used in the experiment to meet the stability criterion. Fig. 5 shows design concept of the constant off-time DPWM, in which the related parameters are shown in Table 2. In this digital implementation, the switching frequency varies from 117K to 195 KHz with the constrained on-time between 3.41 s and 6.82 s. Fig. 6 shows the output voltage (vo), inductor current (iL) and DPWM signal (d) waveform under regulation with WLEDs as load, in which off-time clock-cycles is fixed at 256(~1.7 us). The voltage conversion ration (M) varies linearly with on-time (Ton), as shown Fig. 7. Fig. 8 shows the Bode plots of G c ( s ) G DPWM ( s ) for both the measured and the
theoretical results. They agree well with each other. Fig. 9 shows the comparison of the measured and the theoretical model of the
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Resolution bits of ADC (AD9057) 8 bits

Table 2. Parameter values for DPWM implementation with different duty cycle. Toff (s) Seg. 1 Seg. 2 Seg. 3 Seg. 4 6.82 6.82 3.41 1.70 Ton (s) 0~3.41 (0~3.41)+3.41 (0~3.41)+3.41 (0~3.41)+3.41 Duty 0~0.33 0.33~0.5 0.5~0.66 0.66~0.8

50

Gain(dB)

-50 3 10 100

10

Frequency(Hz)

10

10

(a)

Phase(degree)

0 -100 -200 -300 -400 3 10 Theory data Measurement data 10

4

Frequency(Hz)

10

10

Fig. 8. Bode plots of G c ( s ) G DPWM ( s ) , measured vs. theoretical.

(b)
Gain(dB)
20 0 -20 -40 -60 -80 2 10 0 10
3

Fig. 5. (a) Implementation of digital constant off-time pulse-width modulator and (b) associated waveforms.

Frequency(Hz)

10

10

10

Phase(degree)

-100 -200 -300 -400 2 10 Measurement data Theory data 10

3

Frequency(Hz)

10

10

10

Fig. 9. Bode plots of the loop gain T ( s ) , measured vs. theoretical. Converter working conditions: same as Fig. 6.

Fig. 6. Waveforms

of

breadboard

under

closed-loop regulation control. Circuit working conditions: output voltage: 13.1 V (4 WLEDs) input voltage: 3.3 V, load current: 20 mA.

V. CONCLUSIONS A constant off-time digital controller was proposed and demonstrated for a boost converter of high-conversion gain ratio for WLED applications. Compared to the other two controller types, a constant off-time controller provides better light dimming resolution or requires ADC converters with less number of bits. A digital control model was proposed and verified in the paper. For a typical DC voltage source application using a digitally-controlled boost or buck/boost converter with high conversion gain, similar considerations apply.
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Fig. 7. Voltage conversion ratio (M) vs. on-time (Ton).

ACKNOWLEDGEMENT This work was supported by Taiwan Government Industrial Bureau contract #95-EC-17-A-01-I1-0051 to Richtek Technology Corp. and National Taiwan University. REFERENCES
[1] Y. Duan and H. Jin, Digital Controller Design for Switch Mode Power Converters, Proceeding of IEEE Applied Power Electronics Conference and Exposition, vol.2, pp. 480-484, 1999. [2] B. J. Patella, et al., High-Frequency Digital Controller IC for DC/DC Converters, Proceeding of IEEE Applied Power Electronics Conference and Exposition, vol.1, pp. 374-380, 2002. [3] A. M. Wu, et al., Digital PWM Control: Application in Voltage Regulator Models, Proceedings of IEEE Power Electronics Specialists Conference, vol. 1, pp. 77-83, 1999. [4] A. R. Oliva, et al., Digital Control of a Voltage-Mode Synchronous Buck Converter, IEEE Transactions on Power Electronics, vol. 21, pp. 157-163, 2005. [5] L. Peng, et al., A Novel PWM Technique in Digital Control, IEEE Transactions on Industrial Electronics, vol. 54, pp. 338-346, 2007. [6] C. H. Chen, et al., Modeling of Digitally-controlled Voltage-Mode DC-DC Converters, Proceedings of IEEE Industrial Electronics Society Conference, vol. 2, pp. 2005-2009, 2007. [7] A. Prodic, et al., Design and Implementation of a Digital PWM Controller for a High-Frequency Switching DC-DC Power Converter, Proceedings of IEEE Industrial Electronics Society Conference, vol. 2, pp. 893-898, 2001. [8] A. V. Peterchev and S. R. Sander, Quantization Resolution and Limit Cycling in Digitally Controlled PWM Converters, IEEE Transactions on Power Electronics, vol. 18, pp. 301-308, 2003. [9] R. P. Severns and G. Bloom, Modern DC-to-DC Switch Mode Power Converter Circuits, New York: Van Nostrand Reinhold, 1985. [10] Datasheet: High Brightness White LED, UPWLEDxx, Microsemi., 2003. [11] J. Sun, Small-Signal Modeling of Variable-Frequency Pulse Width Modulators, IEEE Transactions on Aerospace and Electronic System, vol. 38, pp. 1104-1108, 2002.

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