ELX304

Electronic System Design

University of Sunderland Faculty of Applied Sciences Department of Computing, Engineering & Technology

ELX304 Electronic System Design EXAMINATION

Date:

Wednesday 7th September 2011

Time:

9.30-12.30

Instructions to Candidates: Time allowed - 3 hours There are 6 questions set. You must attempt 4 questions. This is a closed book examination this means you are not permitted to use any text books or study aids in the examination. You are forbidden to use programmable calculators or dictionaries. You must answer the required number of questions only. Any additional answers will not be marked. You should put a cross through any work you do not wish to be marked. The following examination aids are provided : - Linear graph paper

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Electronic System Design

Q1

Figure Q1 shows the state flow diagram of a synchronous circuit to detect the pattern 1101 in serial clocked data (X). The end of the sequence can form the beginning of the next sequence and once the pattern is recognized then the output (Z) is immediately set high and held for one clock pulse.
1

A 0 1 E 0 0 0

B 0 1

0 0 0

C 0

D 1

Figure Q1 : Synchronous Pattern Detector a) Develop its minimized state output table. Should any merges occur remove the alphabetically higher ordered term (i.e if A and B merge replace all B terms with A) marks) b) State the design rules and indicate which ones are not satisfied by the following assignment :
Q1Q2 Q3 0 1 00 A D 01 B 11 C 10 E -

(5

(5 marks)
c) Develop a J-K flip-flop solution to the problem using the assignment provided in Q1b above. You need not sketch the final design. Using the above state flow diagram sketch how it could be modified to hold the output for two clock pulses when the

(10 marks)

d)

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Electronic System Design

sequence is detected. (5 marks) Q2 The following state flow diagram is a model of a control system for the robot shown. The circuit inputs are the proximity sensor outputs (S1S2) which are a logic high when an obstacle is detected. The outputs (Z1Z2) are the forward drive signals to the robots motors where a logic high represents drive and a logic low brake.
00 A 11 01 01,11 B 01 Z1 01 10 D 10 10 10 C 11 Robot (viewed from above) 00 00 Z2 S1 S2

11 00 10

a)

Identify any operational limitations that are present in the solution shown in figure Q1. (2 marks) b) An Asynchronous solution to the above problem is to be designed : i) Obtain its State output table, assuming outputs need only be assigned to stable states for now.

marks)
ii)

(2

marks)
c)

Use an implication table to show that its minimised state output table contains only a single state and from this identify the Boolean logic expressions for the motor drives Z1 and Z2.

(6

A new robot control scheme is proposed which has only a single proximity sensor (S) at the front of the robot and

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Electronic System Design

Q3 a)

avoids an obstacle by continuing to rotate in the same direction until the sensor signal is lost. If the control strategy is to alternate this rotational direction in the sequence left-right-left-right etc, develop a minimal race-free asynchronous solution.

(15 marks)

The basic building block of all numeric devices is the full adder. Design the logic required to implement it. marks) b) The following circuit shows the NAND implementation of an EX-OR gate : A Z B i) marks) ii) Show that Z = A B

(5

(4

marks)
iii)

Show how the sum bit of a full adder can be implemented using EX-OR gates.

(2

marks)

Develop a NAND implementation of the carry bit of a full adder.

(4

c)

Full adders can be used to implement multi-bit adders. Show the construction of a 4-bit adder

i) marks) ii)

(2

What is the main problem with such implementations

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Electronic System Design

marks)
iii)

and discuss one method of improving things?

(3

marks)

Describe how multiplication is performed and therefore identify what hardware would need to be added to convert the 4-bit adder into a multiplier of unsigned 4-bit binary numbers.

(5

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Electronic System Design

Q4 a)

For the logic function

f =a +b.c

Show how the function may be implemented using : i) NMOS with active depletion transistor pull-up marks) ii) NMOS in a programmed transistor array marks) iii) CMOS technology marks)

(3

(4

(3

b)

Develop a Shannons expansion theorem form of the logic function and sketch its implementation upon a CMOS semi-custom (Double Rail MPGA) design cell.

(10 marks)

c)

For the CMOS logic array cell shown in figure Q4 sketch : i) the transistor layout of the cell marks) ii)

(3

If the cell is programmed using metal links what would the minimum size of the contact areas be if MOSIS design rules were used (2 marks)

X1 Z1 F1

X2 Polysilicon Z2 P-channel

Z3

F2

Z4 N-channel

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Electronic System Design

Figure Q4 : CMOS Logic Array

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Electronic System Design

Q5

For the CMOS gate shown in Figure Q5 :

a) Sketch the circuit and determine the logic produced marks) b)

(6

Use the MOSIS design rules shown in Table Q5 to determine the height of the cell shown in Figure Q5 assuming that the aspect ratio of the NMOS gates is 1:1 and the PMOS gates 1:2. Clearly label the rules employed in coming to your solution on the attached solution page at the back of the examination paper. (12 marks)

c)

Why is the aspect ratio of the PMOS gates half that of the NMOS gates ? marks) d)

(2

Describe the relationship between feature size and the MOSIS design rules and explain what the limitations are to its future reduction. (5 marks)
Vdd

Gnd P-Well B A

Metal

N-Moat

Polysilicon

P-Moat

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Electronic System Design

Figure Q5 : CMOS P-Well Gate Rules 1. P-well 1. 2. 3. Active 1. 2. 3. 4. 5. 6. Poly 1. 2. 3. 4. 5. Contact 1. 2. 3. 4. 5. 6. 7. 8. 9. Width Spacing (Different potential) Spacing (Same potential)

Scale 4 10 6

2.

Width Spacing P+ active n+ active n+ active P+ active

in n-subs to p-well edge in n-subs to p-well edge in p-well to p-well edge in p-well to p-well edge

2 2 6 5 2

3.

Width Spacing Field Poly to active Poly overlap of active Active overlap of Poly

2 2 2 2

4.

Square contact, exactly Rectangular contact, exactly Space to different contact Poly overplay of contact Space to channel Metal overlap of contact Active overlap of contact N+ select overlap of contact Subs/well shorting contact, exactly

2 * 2 2*6 2 2 2 2*6

5.

Metal 1.

Width

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Electronic System Design

2.

Spacing

Table Q5 : CMOS - MOSIS Design Rules (Single Metal P-Well process) Q6 a) The nature of NMOS/CMOS construction lends itself readily to the construction of parallel plate capacitors. i) Why is this a problem? marks) ii) Why are capacitors often used in analogue circuit construction rather than resistors?

(2

marks)
b)

(2

Single mask capacitors are constructed using ink technology in the form shown below :
LD H W

flux x WX W

i)

Use the formula for a parallel plate capacitor : C=

o r A d

shown above to derive (ignoring fringing affects) an expression for its sheet capacitance, CS .

You are given that C = CS

ii)

LD WX

(4 marks)

marks)

Using the MOSIS design rules of Table Q5 for polysilicon show that under minimum dimensions W = WX .

(3

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Electronic System Design

iii)

Why is this method of capacitor construction more accurate than standard multi-mask methods?

(1 mark)

Q6 continued overleaf

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Electronic System Design

Q6 Continued c) The above theory shows that the capacitance of single mask devices is proportional to the mean path length, LD. One efficient layout of such devices is the inter-digitated capacitor shown below :
Lf

Wx W

Wx

Lf

i)

Assuming that W = Wx show that the mean internal path length (of the flux) between the two film deposits is :
LD = ( N 1) L f + ( 2 N 1)W

Where N is the total number fingers, of length Lf, on both film deposits (N = 4 shown) marks) ii) iii)

(7

Why is the above relationship only an approximation? (2 marks)

Sketch the structure of an inter-digitated capacitor where N = 3 and Lf = 4W and evaluate its mean path length and overall dimensions (in terms of W). (4 marks)

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Electronic System Design

Page for Submission of Q5 Solution ( If used please remove and attach securely to exam booklet )

Vdd

Gnd P-Well

Metal

N-Moat

Polysilicon

P-Moat