Investigation on technological aspects of class E RF power ampliers for UMTS applications

Dusan Milosevic, Johan van der Tang and Arthur van Roermund Eindhoven University of Technology (TU/e) Department of Electrical Engineering, Mixed-signal Microelectronics (MsM) Group, EH 5.28 P.O. Box 513, 5600 MB Eindhoven, The Netherlands phone: +31 40 247 3393, fax: +31 40 245 5674 email: d.milosevic@tue.nl
Abstract This paper presents results of investigation on the effects of technology on the performance of the class E power amplier circuit. A typical class E circuit has been designed and simulated, for a typical UMTS Tx frequency (1.95 GHz) and output power ( 27dBm). Three different technologies have been used (silicon BJT, CMOS and GaAs HBT) and several important parameters (output efciency, power added efciency, stress put on the device) have been monitored and put in table form for comparison. Care has been taken to adapt the design in such a way to provide a maximum performance with each technology, for a fair comparison. The results are then analyzed and different tradeoffs are discussed. Possibilities for the linearization of the amplier are considered. Keywords Power amplier, class E operation, efciency, linearization, technology

I. I NTRODUCTION Expansive development of wireless communication systems during the last decade has particularly put the design of RF power ampliers (PAs) in focus. Handsets are battery-operated devices and the talktime will directly depend on the efciency of the power amplier in the transmitter. Power consumption of other blocks in the transceiver (DSP/baseband circuitry, oscillators, mixers, lters, LNA etc.) is often negligible to that of the PA. Therefore, the power consumption of the entire transceiver is essentially characterized by the operation of the power amplier. Efciency and linearity are opposing requirements in the design of PA and many efforts are constantly being done by researchers to improve the efciency of PA circuits while still satisfying the linearity requirements for the given system. First and second generation of wireless communication systems, Nordic Mobile Telephone (NMT) and Global System for Mobile communications (GSM) respectively, use modulation formats which result in constant envelope RF signal, thus theoretically allowing the utilization of non-linear power ampliers. The

third generation of wireless communication systems, also known as Universal Mobile Telecommunications System (UMTS) and IMT-2000, is an ambitiously devised system, which will provide a wide range of multimedia services (moving picture transfer etc.), and high data-rates must be supported for both uplink and downlink. Therefore, a modulation technique with high spectral efciency has been chosen, since spectrum is an expensive resource nowadays. UMTS utilizes a Wideband Code Division Multiple Access (W-CDMA) air interface. The resulting modulated RF signal has a non-constant envelope, thus requiring an essentially linear amplication in the transmitter path. On the top of that, a high power control range (of 80 dB in uplink) presents an even bigger challenge for the PA designer. In this paper it is investigated whether highly efcient (but extremely non-linear) class E PA has potential for utilization in UMTS handsets. II. C LASS E POWER
AMPLIFIER

Class E power ampliers were introduced by Sokal and Sokal in 1975 [1]. It is a switching type PA. The basic circuit diagram is depicted in gure 1. The circuitry is rather simple and consists of an active device (it can be BJT,
V dc L1

RFC Load network C2 L2 Load

C1

Rload

Fig. 1. Basic class E circuit

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HBT, JFET, MOSFET, MESFET), an RF choke and surrounding passive elements which form the load network. The practical implementation of the amplier also includes matching networks at the input and output. The circuit from gure 1 represents the original, simplest conguration. Class E can be implemented in a differential conguration as well, or employ a more complex load network involving lters, harmonic traps etc. Unlike conventional classes of operation (A, AB, B, C) where the transistor is operated as a current source controlled by the input signal, in class E (and other switching type PAs) the transistor is operated as a switch having two discrete states, ON and OFF. During the ON state (switch closed), the transistor is heavily overdriven and should provide an as low resistance as possible, while sustaining the current running through it. Conversely, during the OFF state (switch opened) it is in cut-off region, and should provide a very high impedance and be able to stand a voltage rise across its terminals. Clearly, this is an extremely non-linear regime. There are several different approaches in literature to analyze the operation of the circuit, ranging from differential equation solving to frequency domain analysis. The most common and the simplest one will only be mentioned here, in order to briey explain the principle of operation. Some important design equations for circuit elements are rewritten, without derivation. First, it is necessary to take several assumptions which makes the analysis possible. These assumptions are as follows : 1. Transistor is modeled as an ideal switch, i.e. short circuit in the ON state and open circuit in the OFF state, with instant switching action. 2. The switch can sustain the current running through it in the ON state and also must be able to stand the non-zero voltage that appears during the OFF state. 3. The RF choke (DC-feeder) has a very large inductance and accordingly allows only DC current to ow through it. 4. The Q-factor of the of the series resonator L2 C2 is high enough, so it can be considered that purely sinusoidal current is running through the load Rload . The equivalent circuit of gure 1 is depicted in gure 2. The shunt capacitor C p includes the output capacitance of the active device (which can be signicant) and capacitance C1 from gure 1. The series L2 C2 circuit is presented as a serial connection of the resonator Ls Cs tuned at operating frequency and an additional mistuning element L. The switch alternately opens and closes at operating frequency, and the duty cycle can be chosen arbitrarily, but 50% is the usual choice. As it was shown in [2], the choice of the duty cycle is a trade-off between the peak voltage across the transistor and the peak current. The series resonant circuit in the load branch, L2 C2 , is forcing a

V dc

RFC resonant @ Idc isw(t) v sw(t) Cp Irf sin t Rload Ls Cs

L

Fig. 2. Equivalent circuit for the class E PA

sinusoidal waveform of the load current. During the OFF state, the entire current (which is a sum of the DC current and instantaneous value of the load current) is owing through the shunt capacitor C p , charging/discharging it, and the switch voltage Vsw has a characteristic asymmetric waveform, as shown in gure 3. During the ON state,

v sw()
V pk v sw=0 d v sw =0 dt 0 0 OFF state

ON state

Fig. 3. Waveforms for an ideal class E circuit

the voltage across the switch is zero (in ideal case) and the current ows now entirely through the switch. High efciency of operation arises from the fact that no power is dissipated in the switch: voltage vsw and current isw never simultaneously have non-zero values. In addition to that, the so-called class E conditions for soft switching must be satised at the instance of turn-on , the switch voltage vsw and its slope must both be equal to zero, see gure 3. This guarantees that the shunt capacitor will not be discharged through the switch. This is the nominal operating point of class E circuit, and the required load network elements to achieve this operation are: L

1 152Rload

(1)

Cp

0 1837 Rload

(2)

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Values of Ls and Cs are not uniquely determined; they depend on the chosen loaded Q-factor of the series LC circuit. This choice is a design parameter, and it is a trade-off among several criteria [3]. The lowest allowed theoretical value of QL is 1.789, and practical values can be around 10. Therefore, Ls and Cs will be determined as

Ls

QL

1 152 Rload

(3) (4)

Cs

2L

Finally, the load resistance is calculated from the desired output power and supply voltage as Rload

0 577

2 Vdc Pout

(5)

In a practical implementation, inductances Ls and L will be lumped into L2 , C2 will be equal to Cs , and C1 should be determined from C p and the output capacitance of the used transistor. In some cases, this parasitic capacitance can entirely provide the required value for C p , or even be larger and act as a limiting factor in the design. The value of the dc-feeder inductance (RF choke) is not critical, but should be sufciently high that it can be considered as a block for RF signal. The above equations are well known expressions established by Sokal. Recently, the new, improved equations have been published by Sokal, that take into account the inuence of the loaded Q-factor, nite onresistance of the transistor and parasitic resistances of passive elements on the output power[3]. III. C LASS E PA WITH
DIFFERENT TECHNOLOGIES

GaAs HBT ( fT 50GHz) and CMOS18 technology ( fT 60GHz). Power ampliers have been designed for operation at 1.95 GHz, which corresponds to the central frequency of the UMTS uplink band (1920-1980 MHz), and with the target output power of approximately 500 mW (27 dBm). For each device a new circuit has been designed, but based on the original simple topology given in gure 1. This was done in order to provide a fair comparison for the devices. For the same reason, equivalent driving conditions have been applied at the input of the transistor. In all three cases, the transistor input terminal (base/gate) has been driven by a sinewave voltage with the appropriate DC offset. A similar approach has been used like in [4]. From theoretical point of view, the ideal driving signal for class E PA is a squarewave or trapezoidal voltage [3]. This is one of major disadvantages of class E PAs, since at frequencies in GHz range, it is difcult to efciently generate such pulses [5][6]. For this reason, a sinusoidal driving signal has been used, as an approximation and as a realistic option. It is possible to utilize a class F amplier as a driver stage [7][8][9], but analysis of the driving stage is outside the scope of this paper. Elements in the load network have been adjusted so as to achieve waveforms as close as possible to the nominal class E operation, i.e. soft switching, see g. 3. Results of simulations are presented in table I, and the relevant simulation waveforms for the circuit with the HBT are given in gure 4. Efciency of a power amplier is dened as

Pout Pdc

(6)

As it has already been mentioned, it is possible to make use of different types of devices in the design of the class E PA. For many years, GaAs MESFET devices were practically the only candidate for high performance RF power ampliers. The main goal of this paper is to show that a comparable performance is achievable with different technologies of the active device. The issue of technology is important, since the costs of devices differ signicantly. Handsets are products intended for the mass market, and even a small difference in the manufacturing costs has a large impact. CMOS is an important technology nowadays, in both digital and analog part of the transceiver, and it would be very benecial to implement a power amplier in the same technology, and thus open a possibility for a single chip transceiver, or a chip set but in the same process. We have used three different devices in attempt to 23GHz), do a technology benchmarking: Si BJT ( fT

where Pout is the output RF power and Pdc is the supply power. This parameter is also referred to as output or collector/drain efciency. A more realistic measure of the ampliers performance is the power added efciency (PAE), which takes into account the input power. PAE is dened as Pout Pin (7) PAE Pdc

where Pin is the input power for the power amplier. PAE can signicantly differ from when the power gain is lower than 10 dB, for example, which can often be the case with power ampliers. Since the power gain of PA is dened as Pout Gp (8) Pin

PAE also can be expressed as PAE

1 Gp

(9)

Transistor sizing is an important issue and the rst step

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TABLE I S IMULATION
RESULTS FOR

C LASS E PA

Parameter Frequency (GHz) Supply voltage (V) Output power (mW) Output eff. (%) PAE (%) Power gain (dB) Peak Vc d (V) Peak Ic d (mA) Breakdown (V)

Technology BJT HBT CMOS18 1.95 1.95 1.95 3 3 1.2 498 482 410 79 89.6 79.6 75 86 13.5 14.3 8.6 10.56 3.85 480 556 1288 19 12 4

and thus minimize losses during the ON-state. First, it can be noticed from table I that a comparable performance has been achieved with all three devices. Theoretically, efciency for class E power ampliers is 100 %, but in practice there are several effects that lower this value. Transistors can not perfectly perform a switching action, because of nite turn-on and turn-off transitions. Especially the nite collector/drain current fall time can be critical [10]. Therefore, there partly will be an overlapping of non-zero voltage and current that will introduce losses. In addition, the transistor has a nite on-resistance, which causes dissipation during the ON state of the RF cycle. In [11], it was shown that efciency degrades with on-resistance as

Ic

1 r 1 4 R ON

(10)

load

Vc

Fig. 4. Collector current and voltage for HBT circuit

in a PA design. Device must be large enough to provide a reliable operation and satisfying performance. In these designs, the emphasis was on achieving high efciency and correct waveforms. Reasonably large devices have been used, but no special considerations have been done on the reliability of operation. The device in the BJT based PA has been given the dimensions W=2 m and L=1700 m, and a MULT factor of 2. MEXTRAM model has been used for simulations. The GaAS HBT has been used with an AREA parameter of 2000 and the Gummel-Poon model has been used in simulations. The third technology is 0 18 m CMOS process with dimensions L=0 18 m and W=6000 m. For CMOS PA, MOS level 9 model has been used in simulations. All circuits have been simulated in Philips inhouse circuit simulator Pstar. Dimensions of the BJT and the HBT have been chosen so that the peak current of the device is below the value which corresponds to the maximum ft on the ft vs. Ic plot. A large MOS transistor has been used in order to provide low on-resistance

where rON is the ON-resistance of the transistor. During the ON state, a bipolar device (BJT or HBT) is in saturation, and a MOS device is in linear (triode) region. Collector-to-emitter saturation voltage, VCEsat , depends on the actual type of the device under consideration, but also on the frequency of operation, and can reach as high as 1 or 2 volts in RF applications [3]. In circuits employing HBT and BJT it was around 0 2V, and somewhat lower in the CMOS PA. MOS model level 9 shows that RdsON for the given transistor changes almost linearly from 0 105 to 0 16 when Vds changes from 0 to 0 2V and the gate is constantly driven with Vgs 1 8V. In the CMOS design, a very low Rload has been used, of only 0 88. This is necessary because of the low supply voltage, which is imposed by the breakdown limitation of the device (4V for the gateoxide breakdown for the used technology). Taking into account Rload 0 88, it can be seen that a good agreement of the simulated efciency with the theoretical prediction (10) has been achieved. In table I, PAE and power gain for the CMOS circuit were omitted. This is due to the imperfection of the active device model and the fact that it was not possible to accurately determine the input power for this design. MOS level 9 model was used, which does not implement the intrinsic resistance of the MOS device, which is seen by the source driving the transistor. Namely, at high frequencies, the input impedance of a MOS transistor is no longer purely capacitive, but has a real part as well, which is dissipating power[12]. In [13] the relation between the input power, series gate resistance and other transistor parameters was derived, but it was not taken into account that apart from the series gate resistance, the correct MOS model has to include the additional resistance of the channel. Therefore, for accuracy reasons, PAE and power gain are not given in table I for the MOS PA.

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Other phenomena that have a signicant inuence on efciency are transistor parasitic capacitances. Since large devices are normally used in PAs, these capacitances must be taken into account. The transistor output capacitance is particularly signicant in large MOS devices. In some cases, depending on the technology of the device, transistor size and desired output power, it can be entirely used as the shunt capacitance C p in gure 2. The drain-to-bulk junction capacitance in a MOS transistor is non-linear, and the effective PA design procedure in the presence of this non-linear effect has been thoroughly investigated in several papers [14][15][16]. For the transistor in CMOS design, this capacitance for zero bias Vds 0 was found to be 5 07pF. This value is far less then the required one for shunt capacitance (17 pF, see eq.(2)). Therefore, the nonlinearity of the transistor output capacitance has a minor effect in this design and standard design equations have been used.

IV. L INEARIZATION In case of class E power ampliers it is difcult to talk about any linearity, since these circuits do not really perform an amplication: the input signal is seen just as an information for triggering the active device , i.e. switch, and the amplitude of the output voltage is entirely determined by the supply voltage and load network elements. In one of his early papers Raab points out that these circuits are rather power converters than ampliers [17]. Class E PAs are suitable only for constant envelope systems and any information contained in the amplitude of the input signal will be lost at the output. However, there is potential to linearize the operation of the class E PA and to use it in applications with variable envelope. This linearization scheme is called Envelope Elimination and Restoration (EER) and the block diagram is given in gure 5. This
V dc Envelope detector Amplitude modulator RF input RF output

PA Phase detector (limiter)

Fig. 5. EER schematic.

principle of operation is simple: all voltages in the class E circuit are (in a theoretically ideal case) proportional to the supply voltage. Therefore, by changing the supply voltage it is possible to control the amplitude of the output signal. Input signal, which has a variable envelope, is passed through the phase detector (limiter) and brought to the input of the class E stage. The upper branch contains an amplitude detector, which extracts the envelope of the input signal, and an amplitude amplier, or more precisely supply voltage modulator, which provides the required power to the class E circuit. From theoretical point of view, this is a perfect concept and it preserves a high efciency of the class E PA. Since all voltages are linearly proportional to the supply voltage, the ratio of losses and output power remains constant and so does the efciency, given that all elements of the circuit remain unchanged. This is particularly important for application in systems where the peakto-average ratio (crest factor) is high. In UMTS, the peakto-average ratio can be above 10 dB. In practice, class E PA will not demonstrate a perfectly linear Vout Vdc ratio, since the transistor is not an ideal switch and has a set of parameters which will change when operating conditions change. In addition to that, efciencies of other blocks in the system have to be taken into account, and especially that of the amplitude amplier. The overall performance will depend not only on the class E but on other blocks as well, but it is important to provide the highest possible efciency of the class E before linearization. The practical realization of EER will be conditioned by several requirements. Performance of the amplitude amplier in the envelope path is of crucial importance. It must provide a linear transfer characteristic and have a sufcient bandwidth. The envelope extraction from the input RF signal will result in spectral expansion. The bandwidth of the envelope path has to be at least 3-4 times the bandwidth of the RF modulated signal in order to satisfy the stringent linearity requirements of the UMTS standard [19]. In addition to large bandwidth of the envelope path, an accurate phase and amplitude alignment must be provided. Because of the different nature of signal processing in the phase and envelope branch, a certain delay mismatch will exist. This delay mismatch must be minimized in order to satisfy the ACPR requirements for UMTS. The class E PA circuit will also have to be modied. For application in UMTS, the supply voltage will have a bandwidth of at least 20 MHz and an RF choke can not be used in the circuit. The EER concept has been checked on the class E circuit employing an ideal switch and ideal blocks in the envelope and phase path and the results satisfy ACPR requirements for UMTS.

is an old technique, which dates from the 1950s (before Class E existed), and was proposed by Kahn [18]. The

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V. C ONCLUSIONS This paper has presented results of investigations on the performance of class E RF power ampliers employing active devices of different technologies. The results of simulations show that comparable performance can be achieved with all devices, but GaAs heterojunction bipolar transistor is the most promising one. CMOS has an advantage of opening the possibility for high integration of the transceiver, but also a signicant shortcoming in terms of low breakdown voltage and necessity to use much lower supply voltage for the desired output power. These results are comparable to several recently published designs [4][5][11][20], but should be accepted with caution since ideal (lossless) passive components have been used in simulations. UMTS handsets will be power-demanding devices and an efcient power amplication is a challenge, in order to provide acceptable operation time with reasonable size and weight of the battery and entire handset. Linear class A power ampliers can satisfy stringent UMTS linearity requirements, but achieve the theoretical maximum of 50% only at peak envelope power, and the overall efciency performance will be signicantly lower. A superior efciency of class E in comparison to conventional linear class A/AB power ampliers indicate that further investigation in the implementation of the EER or other linearization technique is of high importance.

ACKNOWLEDGMENTS The work presented in this paper is funded by the Dutch technology foundation STW. The authors would like to thank STW for their nancial support and Peter Baltus from Philips SLE, Eindhoven for many helpful discussions. R EFERENCES
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[3] N. O. Sokal, Class-E switching-mode high-efciency tuned RF/microwave power amplier: improved design equations, IEEE MTT-S Int. Microwave Symp. Digest, 2000, vol. 2 , pp. 779-782. [4] G. K. Wong and S. I. Long, High efciency bipolar power amplifers, Final Report 1997-98 for MICRO Project 97-104, see www.ucop.edu/research/micro/97 98/97 104.pdf [5] K. Mertens and M. Steyaert, A 700-MHz 1-W fully differential CMOS class-E power amplier, IEEE Journal of Solid-State Circuits, vol. 2 , pp. 137-141, February 2002. [6] K. Mertens and M. Steyaert, Low voltage PA design in standard CMOS, AACD, 2001. [7] T. Sowlati, C. Salama, J. Sitch, G. Rabjohn and D. Smith, Low voltage, high efciency Ga As class E power ampliers for wireless transmitters, IEEE J. Solid-State Circuits, vol. 30, pp. 1074-1080, October 1995. [8] S. C. Cripps, RF Power Ampliers for Wireless Communications, Artech House, 1999. [9] B. Razavi, RF Microelectronics, Prentice Hall, 1998. [10] M. Kazimierczuk, Effects of the collector current fall time on the class E tuned power amplier, IEEE J. Solid-State Circuits, vol. SC-18, pp. 181-193, April 1983. [11] C. Yoo and Q. Huang, A common-gate switched 0.9-W classE power amplier with 41 % PAE in 0.25- m CMOS, IEEE J. Solid-State Circuits, vol 36, pp. 823-830, May 2001. [12] D. Leenaerts, J. van der Tang and C. Vaucher, Circuit design for RF transceivers, Kluwer Academic Publishers, 2001. [13] D. K. Choi and S. I. Long, A physically based analytic model of FET Class-E power ampliersdesigning for maximum PAE, IEEE Transactions on Microwave Theory and Techniques, vol. 47, pp. 1712-1720, September 1999. [14] M. J. Chudobiak, The use of parasitic nonlinear capacitors in class E ampliers, IEEE Transactions on Circuits and Systems, vol. 34, pp. 941-944, December 1994. [15] P. Allinikula, K. Choi and S. I. Long, Design of class E power amplier with nonlinear parasitic output capacitance, IEEE Transactions on Circuits and Systems, vol. 46, pp. 114-119, February 1999. [16] C. Chan and C. Toumazou, Design of a class E power amplier with non-linear transistor output capacitance and nite DC-feed inductance, IEEE International Symposium on Circuits and Systems, vol. 1, pp. 129-132, 2001. [17] F. H. Raab, Idealized operation of the class E tuned power amplier, IEEE Transactions on Circuits and Systems, vol. CAS-24, pp. 725-735, December 1977. [18] L. R. Kahn, Single Sideband Transmission by Envelope Elimination and Restoration, Proc. IRE, vol. 40, pp. 803-806, July 1952 [19] L. Sundstr om, Linear transmitter architectures, AACD 2001. [20] G. K. Wong and S. I. Long, An 800 MHz HBT class-E amplier with 74 % PAE at 3.0 volts for GMSK, in Proc. 21st Annual GaAs IC Symposium, pp. 299-302, 1999.

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