1CY 7C34 4B

fax id: 6101

CY7C344 CY7C344B

32-Macrocell MAX EPLD

Features
High-performance, high-density replacement for TTL, 74HC, and custom logic 32 macrocells, 64 expander product terms in one LAB 8 dedicated inputs, 16 I/O pins 0.8-micron double-metal CMOS EPROM technology (CY7C344) Advanced 0.65-micron CMOS EPROM technology to increase performance (CY7C344B) 28-pin 300-mil DIP, cerDIP or 28-pin HLCC, PLCC package sents the densest EPLD of this size. Eight dedicated inputs and 16 bidirectional I/O pins communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an input, two expanders are used to create an input path. Even if all of the I/O pins are driven by macrocell registers, there are still 16 buried registers available. All inputs, macrocells, and I/O pins are interconnected within the LAB. The speed and density of the CY7C344/CY7C344B makes it a natural for all types of applications. With just this one device, the designer can implement complex state machines, registered logic, and combinatorial glue logic, without using multiple chips. This architectural flexibility allows the CY7C344/CY7C344B to replace multichip TTL solutions, whether they are synchronous, asynchronous, combinatorial, or all three.

Functional Description
Available in a 28-pin 300-mil DIP or windowed J-leaded ceramic chip carrier (HLCC), the CY7C344/CY7C344B repre-

Logic Block Diagram [1]

15(22) 15(23) 27(6) 28(7) INPUT INPUT INPUT INPUT INPUT INPUT INPUT 1(8) 13(20) 14(21) INPUT/CLK 2(9)

Pin Configurations
HLCC Top View

4 3 2 1 28 27 26 I/O INPUT INPUT INPUT INPUT/CLK I/O I/O 5 6 7 8 9 10 11 25 24 23 22 21 20 19 I/O I/O INPUT INPUT INPUT INPUT I/O

MACROCELL 2 MACROCELL 4 MACROCELL 6 MACROCELL 8 MACROCELL 10 MACROCELL 12 MACROCELL 14 MACROCELL 16 MACROCELL 18 MACROCELL 20 MACROCELL 22 MACROCELL 24 MACROCELL 26 MACROCELL 28 MACROCELL 30 MACROCELL 32 B U S G L O B A L

MACROCELL 1 MACROCELL 3 MACROCELL 5 MACROCELL 7 MACROCELL 9 MACROCELL 11 MACROCELL 13 MACROCELL 15 MACROCELL 17 MACROCELL 19 MACROCELL 21 MACROCELL 23 MACROCELL 25 MACROCELL 27 MACROCELL 29 MACROCELL 31 C O N T R O L I O

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

3(10) 4(11) 5(12) 6(13) 9(16) 10(17) 11(18) 12(19) 17(24) 18(25) 19(26) 20(27) 23(2) 24(3) 25(4) 26(5)

12 13 14 1516 1718

C3442

CerDIP Top View

INPUT INPUT/CLK I/O I/O I/O I/O VCC GND I/O I/O I/O I/O INPUT INPUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 INPUT INPUT I/O I/O I/O I/O VCC GND I/O I/O I/O I/O INPUT INPUT C3443

64 EXPANDER PRODUCT TERM ARRAY

32

C3441

Selection Guide
Maximum Access Time (ns) Maximum Commercial Operating Military Current (mA) Industrial Maximum Standby Current (mA) Commercial Military Industrial 7C344B10 10 200 7C344B12 12 200 220 220 150 170 170 7C34415 7C344B15 15 200 220 150 170 7C34420 7C344B20 20 200 220 220 150 170 170 7C34425 7C344B25 25 200 220 220 150 170 170

150

Shaded area contains preliminary information. Note: 1. Numbers in () refer to J-leaded packages.

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134 408-943-2600 January 1990 Revised October 1995

CY7C344 CY7C344B
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. 65C to +150C Ambient Temperature with Power Applied................................................... 0C to +70C Maximum Junction Temperature (Under Bias)............. 150C Supply Voltage to Ground Potential ............... 2.0V to +7.0V Maximum Power Dissipation................................... 1500 mW DC VCC or GND Current ............................................ 500 mA Static Discharge Voltage (per MIL-STD-883, Method 3015)..............................>2001V DC Output Current, per Pin ......................25 mA to +25 mA DC Input Voltage[2] .........................................3.0V to +7.0V DC Program Voltage .................................................. +13.0V

Operating Range
Range Commercial Industrial Military Ambient Temperature 0C to +70C 40C to +85C 55C to +125C (Case) VCC 5V 5% 5V 10% 5V 10%

Electrical Characteristics Over the Operating Range[3]

Parameter VOH VOL VIH VIL IIX IOZ IOS ICC1 ICC2 tR tF Description Output HIGH Voltage Output LOW Voltage Input HIGH Level Input LOW Level Input Current Output Leakage Current Output Short Circuit Current Power Supply Current (Standby) Power Supply Current Recommended Input Rise Time Recommended Input Fall Time GND VIN VCC VO = VCC or GND VCC = Max., VOUT = 0.5V[4, 5] VI = VCC or GND (No Load) VI = VCC or GND (No Load) f = 1.0 MHz[4,6] Commercial Military/Industrial Commercial Military/Industrial Test Conditions VCC = Min., IOH = 4.0 mA VCC = Min., IOL = 8 mA 2.2 0.3 10 40 30 Min. 2.4 0.45 VCC+0.3 0.8 +10 +40 90 150 170 200 220 100 100 Max. Unit V V V V A A mA mA mA mA mA ns ns

Capacitance
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions VIN = 2V, f = 1.0 MHz VOUT = 2.0V, f = 1.0 MHz Max. 10 10 Unit pF pF

AC Test Loads and Waveforms[7]

5V OUTPUT 50 pF INCLUDING JIGAND SCOPE Equivalent to: R2 250 R1 464 5V OUTPUT 5 pF R2 250 R1 464 3.0V GND 6ns ALL INPUT PULSES 90% 10% tf 90% 10% 6ns

tR (a) (b)
C3444

tF
C3445

THVENIN EQUIVALENT (commercial/military) 163 OUTPUT 1.75V C3446

Notes: 2. Minimum DC input is 0.3V. During transitions, the inputs may undershoot to 2.0V for periods less than 20 ns. 3. Typical values are for TA = 25C and VCC = 5V. 4. Guaranteed by design but not 100% tested. 5. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 6. Measured with device programmed as a 16-bit counter. 7. Part (a) in AC Test Load and Waveforms is used for all parameters except tER and tXZ, which is used for part (b) in AC Test Load and Waveforms. All external timing parameters are measured referenced to external pins of the device.

CY7C344 CY7C344B
Timing Delays
Timing delays within the CY7C344/CY7C344B may be easily determined using Warp2, Warp2Sim, or Warp3 software or by the model shown in Figure 1. The CY7C344/CY7C344B has fixed internal delays, allowing the user to determine the worst case timing delays for any design. For complete timing information, the Warp3 software provides a timing simulator. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tS1. Determine which of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tS1) is the lowest frequency. The lowest of these frequencies is the maximum data-path frequency for the synchronous configuration. When calculating external asynchronous frequencies, use tAS1 if all inputs are on dedicated input pins. If any data is applied to an I/O pin, tAS2 must be used as the required set-up time. If (tAS2 + tAH) is greater than tACO1, 1/(tAS2 + tAH) becomes the limiting frequency in the data-path mode unless 1/(tAWH + tAWL) is less than 1/(tAS2 + tAH). When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tAS1. Determine which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the lowest frequency. The lowest of these frequencies is the maximum data-path frequency for the asynchronous configuration. The parameter tOH indicates the system compatibility of this device when driving other synchronous logic with positive input hold times, which is controlled by the same synchronous clock. If tOH is greater than the minimum required input hold time of the subsequent synchronous logic, then the devices are guaranteed to function properly with a common synchronous clock under worst-case environmental and supply voltage conditions. The parameter tAOH indicates the system compatibility of this device when driving subsequent registered logic with a positive hold time and using the same clock as the CY7C344/CY7C344B.In general, if tAOH is greater than the minimum required input hold time of the subsequent logic (synchronous or asynchronous), then the devices are guaranteed to function properly under worst-case environmental and supply voltage conditions, provided the clock signal source is the same. This also applies if expander logic is used in the clock signal path of the driving device, but not for the driven device. This is due to the expander logic in the second devices clock signal path adding an additional delay (tEXP), causing the output data from the preceding device to change prior to the arrival of the clock signal at the following devices register.

Design Recommendations
Operation of the devices described herein with conditions above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this datasheet is not implied. Exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. The CY7C344/CY7C344B contains circuitry to protect device pins from high-static voltages or electric fields; however, normal precautions should be taken to avoid applying any voltage higher than maximum rated voltages. For proper operation, input and output pins must be constrained to the range GND (VIN or VOUT) VCC. Unused inputs must always be tied to an appropriate logic level (either VCC or GND). Each set of VCC and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2 F must be connected between VCC and GND. For the most effective decoupling, each VCC pin should be separately decoupled.

Timing Considerations
Unless otherwise stated, propagation delays do not include expanders. When using expanders, add the maximum expander delay tEXP to the overall delay. When calculating synchronous frequencies, use tS1 if all inputs are on the input pins. tS2 should be used if data is applied at an I/O pin. If tS2 is greater than tCO1, 1/tS2 becomes the limiting frequency in the data-path mode unless 1/(tWH + tWL) is less than 1/tS2.

EXPANDER DELAY t EXP LOGIC ARRAY CONTROLDELAY tCLR tLAC tPRE INPUT DELAY tIN LOGIC ARRAY tRSU DELAY tRH tLAD SYSTEM CLOCK DELAYtICS I/O I/O DELAY tIO CLOCK DELAY tIC

REGISTER OUTPUT DELAY OUTPUT tRD tCOMB tLATCH tOD tXZ tZX

INPUT

I/O

FEEDBACK DELAY tFD

C3447

Figure 1. CY7C344/CY7C344B Timing Model

CY7C344 CY7C344B
External Synchronous Switching Characteristics[7] Over Operating Range
7C344B10 Parameter tPD1 tPD2 tPD3 tPD4 tEA tER tCO1 tCO2 tS tH tWH tWL tRW tRR tRO tPW tPR tPO tCF tP fMAX1 Description Dedicated Input to Combinatorial Output Delay[8] Coml /Ind Mil I/O Input to Combinatorial Output Delay[9] Dedicated Input to Combinatorial Output Delay with Expander Delay[10] I/O Input to Combinatorial Output Delay with Expander Delay[4, 11] Input to Output Enable Delay[4] Input to Output Disable Delay[4] Synchronous Clock Input to Output Delay Synchronous Clock to Local Feedback to Combinatorial Output[4, 12] Dedicated Input or Feedback Set-Up Time to Synchronous Clock Input Coml/Ind Mil Coml /Ind Mil Coml/Ind Mil Coml/Ind Mil Coml /Ind Mil Coml /Ind Mil Coml /Ind Mil Coml/Ind Mil 0 4 4 10 10 10 10 10 10 3 8 90.9 9 9 71.4 71.4 12 12 12 12 12 12 3 3 13 13 50.0 50.0 MHz Mil Synchronous Clock Input HIGH Time[4] Synchronous Clock Input LOW Time[4] Asynchronous Clear Width[4] Asynchronous Clear Recovery Time[4] Asynchronous Clear to Registered Output Delay[4] Asynchronous Preset Width[4] Asynchronous Preset Recovery Time[4] Asynchronous Preset to Registered Output Delay[4] Coml/Ind Mil Coml /Ind Mil Coml /Ind Mil Coml /Ind Mil Coml /Ind Mil Coml /Ind Mil Coml /Ind Mil Coml /Ind Mil Mil External Synchronous Clock Period (1/fMAX3)[4] External Maximum Frequency(1/(tCO1 + tS))[4, 14] Coml/Ind Mil Coml/Ind Mil
Shaded area contains preliminary information.

7C344B12 Min. Max. 12 12 12 12 18 18 18 18 12 12 12 12 6 6 12 12 8 8 0 0 4.5 4.5 4.5 4.5 12 12 12 12 12 12

7C34415 7C344B15 Min. Max. 15 15 15 15 30 30 30 30 20 20 20 20 10 10 20 20 10 10 0 0 6 6 6 6 20 20 20 20 15 15 20 20 20 20 15 15 4 4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit ns

Min.

Max. 10 10 16 16 10 10 5 10

Input Hold Time from Synchronous Clock Input[7] Coml /Ind

Synchronous Clock to Local Feedback Input[4, 13] Coml /Ind

CY7C344 CY7C344B
External Synchronous Switching Characteristics[7] Over Operating Range (continued)
7C344B10 Parameter fMAX2 fMAX3 fMAX4 tOH Description Maximum Frequency with Internal Only Feedback (1/(tCF + tS))[4, 15] Data Path Maximum Frequency, least of 1/(tWL + tWH), 1/(tS + tH), or (1/tCO1)[4, 16] Maximum Register Toggle Frequency 1/(tWL + tWH)[4, 17] Output Data Stable Time from Synchronous Clock Input[4, 18] Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml/ Ind Mil 3 125.0 125.0 Min. 111.1 Max. 7C344B12 Min. 90.9 90.9 111.1 111.1 111.1 111.1 3 3 Max. 7C34415 7C344B15 Min. 71.4 71.4 83.3 83.3 83.3 83.3 3 3 ns MHz MHz Max. Unit MHz

Shaded area contains preliminary information. Notes: 8. This parameter is the delay from an input signal applied to a dedicated input pin to a combinatorial output on any output pin. This delay assumes no expander terms are used to form the logic function. 9. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to form the logic function. 10. This parameter is the delay associated with an input signal applied to a dedicated input pin to combinatorial output on any output pin. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling production material. 11. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output pin. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling production material. 12. This specification is a measure of the delay from synchronous register clock input to internal feedback of the register output signal to a combinatorial output for which the registered output signal is used as an input. This parameter assumes no expanders are used in the logic of the combinatorial output and the register is synchronously clocked. This parameter is tested periodically by sampling production material. 13. This specification is a measure of the delay associated with the internal register feedback path. This delay plus the register set-up time, tS, is the minimum internal period for an internal state machine configuration. This parameter is tested periodically by sampling production material. 14. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external only feedback can operate. 15. This specification indicates the guaranteed maximum frequency at which a state machine with internal-only feedback can operate. If register output states must also control external points, this frequency can still be observed as long as it is less than 1/tCO1. This specification assumes no expander logic is used. This parameter is tested periodically by sampling production material. 16. This frequency indicates the maximum frequency at which the device may operate in data-path mode (dedicated input pin to output pin). This assumes that no expander logic is used. 17. This specification indicates the guaranteed maximum frequency in synchronous mode, at which an individual output or buried register can be cycled by a clock signal applied to either a dedicated input pin or an I/O pin. 18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.

CY7C344 CY7C344B
External Synchronous Switching Characteristics[7] Over Operating Range (continued)
7C34420 7C344B20 Parameter tPD1 tPD2 tPD3 tPD4 tEA tER tCO1 tCO2 tS tH tWH tWL tRW tRR tRO tPW tPR tPO tCF tP Description Dedicated Input to Combinatorial Output Delay[8] I/O Input to Combinatorial Output Delay[9] Coml /Ind Mil Coml/Ind Mil Dedicated Input to Combinatorial Output Delay with Ex- Coml /Ind pander Delay[10] Mil I/O Input to Combinatorial Output Delay with Expander Delay[4, 11] Input to Output Enable Delay[4] Input to Output Disable Delay[4] Synchronous Clock Input to Output Delay Synchronous Clock to Local Feedback to Combinatorial Output[4, 12] Coml/Ind Mil Coml/Ind Mil Coml /Ind Mil Coml /Ind Mil Coml /Ind Mil 12 12 0 0 7 7 7 7 20 20 20 20 20 20 20 20 20 20 20 20 4 4 14 14 16 16 25 25 25 25 25 25 7 7 ns ns ns ns Min. Max. 20 20 20 20 30 30 30 30 20 20 20 20 12 12 22 22 15 15 0 0 8 8 8 8 25 25 25 25 25 25 ns ns ns ns ns ns ns 7C34425 7C344B25 Min. Max. 25 25 25 25 40 40 40 40 25 25 25 25 15 15 29 29 ns ns ns ns ns ns ns ns Unit ns

Dedicated Input or Feedback Set-Up Time to Synchro- Coml/Ind nous Clock Input Mil Input Hold Time from Synchronous Clock Input[7] Synchronous Clock Input HIGH Time[4] Synchronous Clock Input LOW Time[4] Asynchronous Clear Width[4] Asynchronous Clear Recovery Time[4] Asynchronous Clear to Registered Output Delay[4] Asynchronous Preset Width[4] Asynchronous Preset Recovery Time[4] Asynchronous Preset to Registered Output Delay[4] Synchronous Clock to Local Feedback Input[4, 13] External Synchronous Clock Period (1/fMAX3)[4] Coml /Ind Mil Coml/Ind Mil Coml /Ind Mil Coml /Ind Mil Coml /Ind Mil Coml /Ind Mil Coml /Ind Mil Coml /Ind Mil Coml /Ind Mil Coml /Ind Mil Coml/Ind Mil

CY7C344 CY7C344B
External Synchronous Switching Characteristics[7] Over Operating Range (continued)
7C34420 7C344B20 Parameter fMAX1 fMAX2 fMAX3 fMAX4 tOH Description External Maximum Frequency(1/(tCO1 + tS))[4, 14] Maximum Frequency with Internal Only Feedback (1/(tCF + tS))[4, 15] Data Path Maximum Frequency, least of 1/(tWL + tWH), 1/(tS + tH), or (1/tCO1)[4, 16] Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Mil Output Data Stable Time from Synchronous Clock Input[4, 18] Coml/ Ind Mil Min. 41.6 41.6 62.5 62.5 71.4 71.4 71.4 71.4 3 3 Max. 7C34425 7C344B25 Min. 33.3 33.3 45.4 45.4 62.5 62.5 62.5 62.5 3 3 ns MHz MHz MHz Max. Unit MHz

Maximum Register Toggle Frequency 1/(tWL + tWH)[4, 17] Coml/Ind

External Asynchronous Switching Characteristics Over Operating Range[7]

7C344B10 Parameter tACO1 tACO2 tAS tAH tAWH tAWL tACF tAP fMAXA1 fMAXA2 fMAXA3 fMAXA4 tAOH Description Asynchronous Clock Input to Output Delay Asynchronous Clock Input to Local Feedback to Combinatorial Output[19] Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input Input Hold Time from Asynchronous Clock Input Asynchronous Clock Input HIGH Time[4, 20] Asynchronous Clock Input LOW Time[4] Asynchronous Clock to Local Feedback Input[4,
21]

7C34415 7C344B12 7C344B15 Max. 12 12 18 18 4 4 4 4 5 5 6 6 7 7 7 7 6 6 7 7 9 9 12.5 12.5 62.5 62.5 76.9 76.9 83.3 83.3 90.9 90.9 12 13 13 45.4 45.4 40 40 66.6 66.6 76.9 76.9 15 15 ns MHz MHz MHz MHz 18 18 ns ns ns ns ns Min. Max. 15 15 30 30 ns ns Unit ns

Min. Coml/ Ind Mil Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml /Ind Mil Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml /Ind Mil Coml/Ind Mil 12 111.1 100.0 90.9 12 71.4 5 4 3 4

Max. Min. 10 15

External Asynchronous Clock Period (1/fMAX4)[4] External Maximum Frequency in Asynchronous Mode 1/(tACO1 + tAS)[4, 22] Maximum Internal Asynchronous Frequency 1/(tACF + tAS) or 1/(tAWH + tAWL)[4, 23] Data Path Maximum Frequency in Asynchronous Mode[4, 24] Maximum Asynchronous Register Toggle Frequency 1/(tAWH + tAWL)[4, 25] Output Data Stable Time from Asynchronous Clock Input[4, 26]

Shaded area contains preliminary information.

CY7C344 CY7C344B
External Asynchronous Switching Characteristics Over Operating Range[7] (continued)
7C34420 7C344B20 Parameter tACO1 tACO2 tAS tAH tAWH tAWL tACF tAP fMAXA1 fMAXA2 fMAXA3 fMAXA4 tAOH Description Asynchronous Clock Input to Output Delay Coml/ Ind Mil Asynchronous Clock Input to Local Feedback to Com- Coml/Ind binatorial Output[19] Mil Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input Input Hold Time from Asynchronous Clock Input Asynchronous Clock Input HIGH Time[4, 20] Asynchronous Clock Input LOW Time[4] Asynchronous Clock to Local Feedback Input[4, 21] External Asynchronous Clock Period (1/fMAX4)[4] External Maximum Frequency in Asynchronous Mode 1/(tACO1 + tAS)[4, 22] Maximum Internal Asynchronous Frequency 1/(tACF + tAS) or 1/(tAWH + tAWL)[4, 23] Data Path Maximum Frequency in Asynchronous Mode[4, 23] Maximum Asynchronous Register Toggle Frequency 1/(tAWH + tAWL)[4, 25] Output Data Stable Time from Asynchronous Clock Input[4, 26] Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml /Ind Mil Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml /Ind Mil Coml/Ind Mil 16 16 34.4 34.4 37 37 50 50 62.5 62.5 15 15 9 9 9 9 7 7 9 9 18 18 20 20 27 27 30.3 30.3 40 40 50 50 15 15 ns MHz MHz MHz MHz Min. Max. 20 20 30 30 12 12 12 12 9 9 11 11 21 21 ns ns ns ns ns 7C34425 7C344B25 Min. Max. 25 25 37 37 ns ns Unit ns

Notes: 19. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the registered output signal to a combinatorial output for which the registered output signal is used as an input. Assumes no expanders are used in logic of combinatorial output or the asynchronous clock input. This parameter is tested periodically by sampling production material. 20. This parameter is measured with a positive-edge-triggered clock at the register. For negative edge triggering, the tAWH and tAWL parameters must be swapped. If a given input is used to clock multiple registers with both positive and negative polarity, tAWH should be used for both tAWH and tAWL. 21. This specification is a measure of the delay associated with the internal register feedback path for an asynchronously clocked register. This delay plus the asynchronous register set-up time, tAS, is the minimum internal period for an asynchronously clocked state machine configuration. This delay assumes no expander logic in the asynchronous clock path. This parameter is tested periodically by sampling production material. 22. This parameter indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can operate. It is assumed that no expander logic is employed in the clock signal path or data path. 23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate. If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tACO1. This specification assumes no expander logic is utilized. This parameter is tested periodically by sampling production material. 24. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode. This frequency is least of 1/(tAWH + tAWL), 1/(tAS + tAH), or 1/tACO1. It also indicates the maximum frequency at which the device may operate in the asynchronously clocked data-path mode. Assumes no expander logic is used. 25. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode by a clock signal applied to an external dedicated input or an I/O pin. 26. This parameter indicates the minimum time that the previous register output data is maintained on the output pin after an asynchronous register clock input to an external dedicated input or I/O pin.

CY7C344 CY7C344B
Typical Internal Switching Characteristics Over Operating Range[7]
7C344B10 Min. Max. 2 2 6 5 5 3 5 5 2 4 0.5 0.5 0.5 3 3 5 0.5 1 2 2 2 2 7C344B12 Min. Max. 2.5 2.5 2.5 2.5 6 6 6 6 5 5 3 3 5 5 5 5 2 2 5 5 0.5 0.5 0.5 0.5 0.5 0.5 4 4 4 4 6 6 0.5 0.5 1 1 3 3 3 3 3 3 3 3 7C34415 7C344B15 Min. Max. 4 4 4 4 8 8 7 7 5 5 4 4 7 7 7 7 5 5 7 7 1 1 1 1 1 1 6 6 6 6 7 7 1 1 1 1 5 5 5 5 5 5 5 5

Parameter Description tIN Dedicated Input Pad and Buffer Delay tIO tEXP tLAD tLAC tOD tZX tXZ tRSU tRH tLATCH tRD tCOMB tCH tCL tIC tICS tFD tPRE tCLR tPCW tPCR

Coml/Ind Mil I/O Input Pad and Buffer Delay Coml/Ind Mil Expander Array Delay Coml/Ind Mil Logic Array Data Delay Coml/Ind Mil Logic Array Control Delay Coml/Ind Mil Output Buffer and Pad Delay Coml/Ind Mil [27] Output Buffer Enable Delay Coml /Ind Mil Output Buffer Disable Delay Coml/Ind Mil Register Set-Up Time Relative to Clock Signal Coml/Ind at Register Mil Register Hold Time Relative to Clock Signal at Coml/Ind Register Mil Flow-Through Latch Delay Coml/Ind Mil Register Delay Coml/Ind Mil Transparent Mode Delay[28] Coml/Ind Mil Clock HIGH Time Coml/Ind Mil Clock LOW Time Coml/Ind Mil Asynchronous Clock Logic Delay Coml/Ind Mil Synchronous Clock Delay Coml/Ind Mil Feedback Delay Coml/Ind Mil Asynchronous Register Preset Time Coml/Ind Mil Asynchronous Register Clear Time Coml/Ind Mil Asynchronous Preset and Clear Pulse Width Coml/Ind Mil Asynchronous Preset and Clear Recovery Time Coml/Ind Mil

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Shaded area contains preliminary information. Notes: 27. Sample tested only for an output change of 500 mV. 28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial operation.

CY7C344 CY7C344B
Typical Internal Switching Characteristics Over Operating Range[7] (continued)
7C34420 7C344B20 Parameter tIN tIO tEXP tLAD tLAC tOD tZX tXZ tRSU tRH tLATCH tRD tCOMB tCH tCL tIC tICS tFD tPRE tCLR tPCW tPCR Description Dedicated Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Expander Array Delay Logic Array Data Delay Logic Array Control Delay Output Buffer and Pad Delay Output Buffer Enable Delay[27] Output Buffer Disable Delay Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml /Ind Mil Coml/Ind Mil Register Set-Up Time Relative to Clock Signal at Reg- Coml/Ind ister Mil Register Hold Time Relative to Clock Signal at Register Coml/Ind Mil Flow-Through Latch Delay Register Delay Transparent Mode Delay[28] Clock HIGH Time Clock LOW Time Asynchronous Clock Logic Delay Synchronous Clock Delay Feedback Delay Asynchronous Register Preset Time Asynchronous Register Clear Time Asynchronous Preset and Clear Pulse Width Asynchronous Preset and Clear Recovery Time Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil Coml/Ind Mil 5 5 5 5 7 7 7 7 8 8 2 2 1 1 6 6 6 6 7 7 7 7 ns 5 5 9 9 1 1 1 1 1 1 8 8 8 8 10 10 3 3 1 1 9 9 9 9 ns ns ns ns ns ns ns Min. Max. 5 5 5 5 10 10 9 9 7 7 5 5 8 8 8 8 8 8 12 12 3 3 1 1 3 3 ns ns ns ns ns 7C34425 7C344B25 Min. Max. 7 7 7 7 15 15 10 10 7 7 5 5 11 11 11 11 ns ns ns ns ns ns ns ns Unit ns

10

CY7C344 CY7C344B
Switching Waveforms
External Combinatorial
DEDICATED INPUT/ I/O INPUT tPD1/t PD2 COMBINATORIAL OUTPUT tER COMBINATORIAL OR REGISTERED OUTPUT tEA HIGH-IMPEDANCE THREE-STATE VALID OUTPUT
C3448

HIGH-IMPEDANCE THREE-STATE

External Synchronous
DEDICATED INPUTS OR REGISTERED FEEDBACK tS SYNCHRONOUS CLOCK tCO1 ASYNCHRONOUS CLEAR/PRESET tOH tRO/t PO REGISTERED OUTPUTS tCO2 COMBINATORIAL OUTPUT FROM REGISTERED FEEDBACK [12]
C3449

tH

tWH

tWL

tRW/t PW

tRR/t PR

External Asynchronous
DEDICATED INPUTS OR REGISTERED FEEDBACK tAS ASYNCHRONOUS CLOCK INPUT tAH tAWH tAWL

tACO1 tAOH

tRW/t PW

tRR/t PR

ASYNCHRONOUS CLEAR/PRESET

tRO/t PO ASYNCHRONOUS REGISTERED OUTPUTS tACO2 COMBINATORIAL OUTPUT FROM ASYNCH. REGISTERED FEEDBACK [19]
C34410

11

CY7C344 CY7C344B
Switching Waveforms (Continued)
Internal Combinatorial
tIN INPUT PIN tIO I/O PIN tEXP EXPANDER ARRAY DELAY tLAC, tLAD LOGIC ARRAY INPUT tPIA

LOGIC ARRAY OUTPUT

C34411

Internal Asynchronous
tIO tR CLOCK PIN tIN CLOCK INTO LOGIC ARRAY tIC CLOCK FROM LOGIC ARRAY tRSU DATA FROM LOGIC ARRAY tRD,tLATCH REGISTER OUTPUT TO LOCAL LAB LOGIC ARRAY tPIA REGISTER OUTPUT TO ANOTHER LAB
C34412

tAWH

tAWL

tF

tRH

tFD

tCLR,tPRE

tFD

Internal Synchronous (Input Path)

tCH SYSTEM CLOCK PIN tIN SYSTEM CLOCK AT REGISTER tRSU DATA FROM LOGIC ARRAY
C34413

tCL

tICS

tRH

12

CY7C344 CY7C344B
Switching Waveforms (Continued)
Internal Synchronous (Output Path)
CLOCK FROM LOGIC ARRAY

tRD

tOD

DATA FROM LOGIC ARRAY tXZ OUTPUT PIN HIGH Z

C34414

tZX

Ordering Information
Speed (ns) 10 Ordering Code CY7C344B10HC CY7C344B10JC CY7C344B10PC CY7C344B10WC 12 CY7C344B12HC/HI CY7C344B12JC/JI CY7C344B12PC/PI CY7C344B12WC/WI CY7C344B12HMB CY7C344B12WMB 15 CY7C34415HC/HI CY7C34415JC/JI CY7C34415PC/PI CY7C34415WC/WI CY7C344B15HC/HI CY7C344B15JC/JI CY7C344B15PC/PI CY7C344B15WC/WI CY7C344B15HMB CY7C344B15WMB 20 CY7C34420HC/HI CY7C34420JC/JI CY7C34420PC/PI CY7C34420WC/WI CY7C344B20HC/HI CY7C344B20JC/JI CY7C344B20PC/PI CY7C344B20WC/WI CY7C34420HMB CY7C34420WMB CY7C344B20HMB CY7C344B20WMB
Shaded area contains preliminary information.

Package Name H64 J64 P21 W22 H64 J64 P21 W22 H64 W22 H64 J64 P21 W22 H64 J64 P21 W22 H64 W22 H64 J64 P21 W22 H64 J64 P21 W22 H64 W22 H64 W22

Package Type 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead Windowed CerDIP

Operating Range

28-Lead Windowed Leaded Chip Carrier Commercial

28-Lead Windowed Leaded Chip Carrier Commercial/Industrial 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead Windowed CerDIP 28-Lead Windowed Leaded Chip Carrier Military 28-Lead Windowed CerDIP 28-Lead Windowed Leaded Chip Carrier Commercial/Industrial 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead Windowed CerDIP 28-Lead Windowed Leaded Chip Carrier 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead Windowed CerDIP 28-Lead Windowed Leaded Chip Carrier Military 28-Lead Windowed CerDIP 28-Lead Windowed Leaded Chip Carrier Commercial/Industrial 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead Windowed CerDIP 28-Lead Windowed Leaded Chip Carrier 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead Windowed CerDIP 28-Lead Windowed Leaded Chip Carrier Military 28-Lead Windowed CerDIP 28-Lead Windowed Leaded Chip Carrier 28-Lead Windowed CerDIP

13

CY7C344 CY7C344B
Ordering Information (continued)
Speed (ns) 25 Ordering Code CY7C34425HC/HI CY7C34425JC/JI CY7C34425PC/PI CY7C34425WC/WI CY7C344B25HC/HI CY7C344B25JC/JI CY7C344B25PC/PI CY7C344B25WC/WI CY7C34425HMB CY7C34425WMB CY7C344B25HMB CY7C344B25WMB
Shaded area contains preliminary information.

Package Name H64 J64 P21 W22 H64 J64 P21 W22 H64 W22 H64 W22

Package Type 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead Windowed CerDIP 28-Lead Windowed Leaded Chip Carrier 28-Lead Plastic Leaded Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead Windowed CerDIP

Operating Range

28-Lead Windowed Leaded Chip Carrier Commercial/Industrial

28-Lead Windowed Leaded Chip Carrier Military 28-Lead Windowed CerDIP 28-Lead Windowed Leaded Chip Carrier 28-Lead Windowed CerDIP

MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics

Parameter VOH VOL VIH VIL IIX IOZ ICC1 Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3

Switching Characteristics
Parameter tPD1 tPD2 tPD3 tCO1 tS tH tACO1 tACO1 tAS tAH Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11

Document #: 3800127G MAX is a registered trademark of Altera Corporation. Warp2 and Warp3 are registered trademarks of Cypress Semiconductor Corporation. Warp2Sim is a trademark of Cypress Semiconductor Corporation.

14

CY7C344 CY7C344B
Package Diagrams
28-Pin Windowed Leaded Chip Carrier H64

15

CY7C344 CY7C344B
Package Diagrams (Continued)
28-Lead Plastic Leaded Chip Carrier J64

28-Lead (300-Mil) Molded DIP P21

16

CY7C344 CY7C344B
Package Diagrams (Continued)
28-Lead (300-Mil) Windowed CerDIP W22
MILSTD1835 D 15Config.A

Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.