A Mixed-Signal ASIC Power-Factor-Correction (PFC) Controller for High Frequency Switching Rectiers

Regan Zane and Dragan Maksimovi c

Colorado Power Electronics Center (CoPEC) Department of Electrical and Computer Engineering University of Colorado, Boulder, CO 80309-0425 zane@colorado.edu, maksimov@colorado.edu
Abstract A mixed-signal IC controller is described for singlephase PFC applications. The single-chip controller block diagram is described, and the fundamental analog and digital operating blocks are developed in detail. Implementation options for each block are given, with experimental results from a 1.2 CMOS test chip included. The controller blocks are derived for boost and buck/boost type converters, but control of other power stages could be derived in the same manner. The nal controller is proposed as a single-chip PFC solution, with no external design or components necessary for high-performance, stable operation over a wide range of operating conditions. I Introduction Many new control techniques for AC-to-DC power converters have been developed in response to tightened regulation of the input current harmonic content [1]-[4]. These controllers generally add complexity and cost to power systems with the performance benet of powerfactor-correction (PFC) and low current harmonic distortion. While such methods have been successful at meeting the demands of many systems over the past ten years, especially using analog ICs that combine multiple control components on a single chip (such as [13]), the recent proliferation of electronic systems throughout the home and ofce places new constraints on front-end AC-to-DC converters. Specifically, applications such as light-weight, mobile equipment, smart appliances, and uorescent lighting demand controllers that result in smaller, lighter, cheaper and higher-performance power systems. In leading up to the solution described in this paper, we will rst examine each of these power system requirements and their implications on the controller: 1) Small footprint & light weight: In order to reduce the size and weight of power-stage components, the converter must be operated at high switching frequencies, likely from hundreds of kHz to M Hz . Also, the controller shouldnt require additional power-stage components for proper operation. To reduce the size of the controller, multi-function chips should be used and total component count should be minimized.
This material is based upon work supported by the National Science Foundation under Grant No. ECS-9703449 and by the University of Colorado 1998 Summer Session Research Grant.

2) Low-cost: System costs can be split into two categories: component/production costs and design costs. To minimize component/production costs, controller power-stage interfacing should be simple with few components needed. To reduce design costs, very little design should be necessary to implement the controller using the most common power stages for particular applications. 3) High-performance: Performance requirements for front-end AC-to-DC converters are driven primarily by regulations that specify limits on input current harmonics [5]. Also, it is often desirable that the system operate over universal-input voltage range and a wide range of load conditions. In general, the controller should force the power-stage to achieve low current harmonic distortion and near-unity PFC, while maintaining as wide-bandwidth control of the output voltage as possible within input harmonic constraints. Regulations such as IEC 1000-3-2 can often be met using simple controller/power stage congurations without precise input current shaping. On the other hand, the regulations proposed for avionics applications have much tighter limits on the line-current harmonic contents. These limits can be met only using high-performance low-harmonic rectiers [16]. Combining the above requirements, an ideal solution would be a low-cost, single-chip controller capable of switching frequencies from hundreds of kHz to M Hz that requires no external design and very few external components for stable operation over a wide range of operating conditions for most common power stages. The analog ICs available today offer many of these characteristics, but are not capable of the adaptive functions necessary for stable, closed-loop operation over wide operating conditions without additional system design. Due to the versatility and adaptability of digital signal processors (DSPs), many DSP controllers have been proposed and implemented for lowfrequency, high-power applications [9]-[12], especially in the area of motor drives [14]. However, due to the high-frequency and low-cost requirements of the PFC controller, DSP solutions appear infeasible for the foreseeable future, even with the rapid growth in digital technologies. This paper presents a mixed-signal IC controller that combines the benets of analog and digital techniques, with the potential of meeting

ig iline vline + vg _

power converter is Co

DminTs
+ Vo _ Vref

driver

iq(t) clock

ic(t)

t t t t

c(t)

switch drive r(t)

+

Analog Integrator iq(t) ic(t)

A/D Conv Digital Feedback Filter vm[k]

r(t) switch drive c(t)

R S

Clock Distribution Switch Freq. Select

vc[n]

D/A Conv

Digital NLC Generator

dTs

Ts

Mixed-Signal IC Controller

Figure 2: Step-up/down controller waveforms

be best performed using analog or digital circuit techniques. Starting with the power switch current integration block, analog implementation offers the benets of simple interfacing with the power-stage and innite time resolution in the output iq (t) for continuous duty-ratio. On the other hand, digital implementation results in precise control of the integration factor and automatic switching frequency scalability, but very complex high-speed A/D conversion of high-frequency switch current, possible sensitivity to switching noise and stability problems with discrete-time output and resulting duty-ratio. Thus, analog techniques were chosen, with the need for adaptive circuitry to vary the integration factor with switching frequency. The NLC waveform generator block must regenerate an amplitude modulated waveshape, dependant only on the power-stage type, within each switching cycle. This has been performed off-chip using discrete passive components in the analog domain [7]. To maintain precise waveshape generation over a wide range of switching frequencies on an IC, a digital NLC generator was used with an output D/A converter for continuous comparison and innite duty-cycle resolution. Interfacing with the outer-voltage feedback loop can be achieved using either digital preset modulation in the generator or analog modulation in the D/A converter, depending on the feedback lter type used. Finally, in order to maintain stable closed-loop operation while optimizing the transient response characteristics, the outer-voltage feedback lter must adaptively adjust its compensation for changes in load. Due to the very low frequencies involved (twice line-frequency), analog techniques would require off-chip components and would not facilitate adaptive behavior. A digital feedback lter clocked at a low frequency offers a good solution. For example, an adaptive, digital feedback lter implemented using standard microcontrollers has already been discussed in [10]. The full controller as outlined in Fig. 1 was simulated with ex-

Figure 1: Mixed-Signal IC Controller Block Diagram

all of the ideal PFC control characteristics detailed in the preceding argument. The general design and operation of the controller is described in Section II. Implementation options for each primary block are then developed in Section III, with experimental results from a 1.2 CMOS test chip included where applicable. II IC Controller Description The ideal PFC control objectives are to maintain the low-frequency portion of the input current ig proportional to the input (full-waverectied ac line) voltage vg , and to keep the output dc voltage Vo at a specied reference level, ig = vg , Re Vo = Vref . (1)

A general block diagram of the proposed controller is shown in Fig. 1, where the control input to the power stage is the switch gate drive signal, c(t). The power stage operates with a xed switching frequency fs and variable duty ratio D, and can be analyzed using standard techniques [5]. The controller is based on the non-linear carrier (NLC) control method to achieve the performance requirements of (1) while maintaining simplicity and IC implementation potential [6]. At the beginning of a switching period, a xed-frequency clock pulse sets the switch drive high. A signal proportional to the integral of the power stage switch current, iq (t), is then compared to a judiciously selected non-linear waveform, ic (t), resetting the switch drive when iq (t) = ic (t), and thus controlling the power switch duty cycle. General operating waveforms for a step-up/down controller are shown in Fig. 2. In developing the mixed-signal IC, each functional block of the controller in Fig. 1 was examined separately to determine if its specied function coupled with its interactions with other blocks would

2.0A

0A

-2.0A 280ms

i(line)

290ms Time

300ms
Figure 4: Experimental integration block waveforms for (1) integrator reset, (4) integration buffer output, with fs = 100kHz , D = 0.2, Iin = 50mA. integration constant was not exactly known, but only needed to be maintained within a range of values dependant on the NLC generator output. Future designs will employ adaptive control of the integration constant or current scaling factor to allow for operation over a wide range of switching frequencies. The nal stage performed voltage-tocurrent conversion for interfacing with the current output of the NLC generator. This was implemented using a voltage-buffer and on-chip 18K resistor combination to maintain the current through the resistor proportional to the integration output voltage. Each of these stages were tested separately from the rst test chip and found to operate as designed. Results from the integration stage are shown in Fig. 4. B. NLC Waveform Generator This section develops simple difference equations for ASIC hardware implementation of the NLC waveform generator of Fig. 1 for two power-stage types. Additional generators could be developed in a similar manner and included on the same chip with simple selection logic allowing a single chip to be used for all common power stages. The ideal waveforms for step-up (boost) and step-up/down (buck-boost, Flyback, Sepic, Cuk) switching converters are given by [6]: step up : vc (t) step up/down : vc (t) vc (t + Ts ) = = = t t 1 Ts Ts Ts t Vm 1 t Ts vc (t) , Vm

Figure 3: Simulated AC line current waveform iline

tracted experimental waveforms from Section III using an averagedswitch model [8] of a step up/down power stage, with the resulting ac-line input current iline shown in Fig. 3, achieving a total harmonic distortion (THD) of less than 5%. III IC Controller Implementation Two full-custom ASICs have been designed in 1.2 CMOS for testing of the mixed-signal controller depicted in Fig. 1. The chips were fabricated using MOSIS services [18]. The rst chip isolated each primary block for individual testing and evaluation, while the second chip combined all blocks for full closed-loop operation with the power-stage. Experimental results from the rst test chip are included in this section where applicable, whereas the second chip is still in fabrication and closed-loop experimental results are not yet available. The nal chip can be operated with a single 5V power supply and a single high-frequency clock input. Sub-Sections A, B, and C develop implementation options for the three primary blocks of Fig. 1, namely the analog integration, NLC generator, and digital feedback lter blocks. The second test chip also included a current-comparator, switch-drive logic, and clock generation logic for control of switch-drive reset, integrator reset, and NLC generator clocking and reset. A. Analog Integrator The analog integrator was designed using three stages. First, the input power-switch current was scaled down by a factor of 5000 using closely matched current-mirrors. The design assumed a peak powerstage current of up to 5A, with a 1 : 100 current transformer for 50mA peak chip input current, scaled down to 10A peak for the integration stage. The second stage used an on-chip capacitor and reset switch for current integration, designed for operation at a switching frequency of fs = 100kHz . Due to the on-chip capacitor, the

(2)

where vc (t) is the ideal NLC waveform (ic (t) in Fig. 1), Vm is the slowly varying feedback signal, and 1/Ts is the power stage switching frequency. Starting with step-up (boost) type converters [5] and sampling (2) with a period Tc , the resulting ideal NLC waveform is given by: vc (nTc ) = Vm nTc Ts 1 nTc Ts , (3)

vc[2] vc[1] vc[0] 3-bit Shift Register Reset

Reset vm[k] 2-1 MUX 1/z vc[n]

vc[n] 1/z 3 -3 1/z 1/z

+ +

K
Figure 6: Step-up/down NLC Generator Filter Implementation
to focus only on the non-linear portion of the signal results in the sampled waveform:
(nTc ) = e a vc
b

Figure 5: Step-up NLC Generator Filter Implementation

where n is the sample number. With the goal of a simple recursive difference equation for lter implementation, the Z -Transform of (3) is found to be: vc (z ) b = = Vm b Tc , Ts z 1 (1 b) z 2 (1 + b) 1 3z 1 + 3z 2 z 3 (4)

(7)

using the same notation as in the step-up generator. Again using the Z -Transform, the recursive form for hardware implementation is found to be:
vc [n]

= =

Kvc [n 1]

e a .

(8)

where 1/b is an integer representing the number of samples per powerstage switching period. The Inverse Z -Transform is then used to nd the desired recursive difference equation: vc [0] vc [1] vc [2] vc [n] = = = = 0 V m ( b b2 ) 2Vm (b 2b ) 3vc [n 1] 3vc [n 2] + vc [n 3] , 3 n 1 . b
2

(5)

Equation (5) can then be implemented directly in hardware, as shown in Fig. 5, by pre-loading the rst three points during reset, then operating the lter for the remaining portion of the switching period. For step-up/down (buck-boost, Flyback, Sepic, Cuk) type converters [5], a discrete-time implementation is not as easily derived from the ideal NLC waveshape (1) due to an innite response at the start of each switching cycle. However, a good approximation can be derived using the same exponential generator analyzed in [7], for which the sampled approximate NLC waveform becomes:

This lter is shown in Fig. 6, where the reset signal loads the voltagefeedback signal vm [k] into the delay element input for Dmin Ts , with normal lter operation for the remainder of the switching period. Note that the voltage-feedback lter operates at a much lower frequency than the NLC generator, as signied by separate subscripts for the two signals, vm [k] and vc [n]. Notice that for both NLC waveform generators, the frequency factor b is given by the ratio of the controller sampling and power-stage switching frequencies, fc and fs respectively. Thus, if the two frequencies are scaled together internally, the waveform generator operates independent of power stage switching frequency, as required by the application. An analog NLC waveform output ic (t) is achieved through a current-steering D/A converter for high-speed, high-accuracy operation with minimal passive components [17]. Details of the circuit design were described in [19]. For the rst test chip, a bit resolution of 6 bits and a sampling clock frequency of fc = 40 fs were chosen for good resolution at high duty ratios and low total harmonic distortion (THD) of the AC line current iline . The resulting K from (8) is: K = 0.890625dec = 0.111001bin . (9)

vc (nTc )

Vm ,

0 nTc Dmin Ts

nTc Dmin Ts aTs , Dmin Ts < nTc Ts , Vm e

(6) where a = 0.22 is a constant found to minimize the total harmonic distortion (THD) of the input current over a universal input voltage range, and Dmin is the minimum duty ratio expected for the operating load range. Normalizing and shifting the waveform by Dmin Ts

The maximum bias current (peak vm [k]) for the least-signicantbit (LSB) was 1A, resulting in a peak (reset) current for ic (t) of 63A. Low-pass ltering of the output was performed by sizing of the output current mirrors. Experimental results are shown in Figs. 7-8 for two switching frequencies, fs = 25kHz , and fs = 250kHz , which demonstrate valid operation independent of switching frequency. Higher frequency operation could not be accurately recorded due to bandwidth and noise limitations of the testing structure, whereas in the nal implementation of Fig. 1 all NLC waveform generator signals will be internal to the chip with predicted switching frequency fs operation up to M Hz .

Figure 7: Experimental waveforms for (1) Dmin , (3) digital clock,

and (4) D/A converter output ic (t) [26A/div ], with fs = 25kHz , fc = 1M Hz . C. Digital Feedback Filter A block diagram of the voltage-regulating feedback loop for the IC controller is shown in Fig. 9, where F (s) is the low-frequency powerstage control-to-output transfer function, G is a constant scale factor, and Av (z ) is the digital feedback lter transfer function. The power stage transfer function is given by [7]: F (s ) = 1 gm R v o = s , v m 3 1+ w p (10)

Figure 8: Experimental waveforms for (1) Dmin , (3) digital clock,

and (4) D/A converter output ic (t) [26A/div ], with fs = 250kHz , fc = 10M Hz .

F(s) G D/A A/D

vo(s)

Av(z)

where the converter pole frequency wp and transconductance gm are dened as: 3 wp = , (11) RC 2 Vg, rms , (12) gm = Rs Vo2 and Rs is the equivalent power-switch current sense resistance. Many well-known methods are available for design of the digital lter Av (z ) in Fig. 9. Since the loop has already been analyzed, implemented, and tested in the analog domain, a logical approach would be to use a discrete equivalent lter from the known Av (s). Thus, the compensation approach used here is modeled after that in [7], where Av (s) was chosen as: A v (s ) = wo s 1+ s wz 1 , G (13)

vref(z)
Figure 9: Voltage regulating feedback loop
[15]. The resulting discrete-time transfer function is given by: A v (z ) = vm (z ) = A1 ve (z ) 1 + b 1 z 1 1 z 1 , (15)

where A1 and b1 are given by: A1 = wz tan = tan tan

wz Tf 2 wz Tf 2

wo
wz Tf 2

1 G +1

1 , +1 (16)

where wz is the compensator zero frequency, and integral compensation assures zero steady-state error in the output voltage. To achieve a desired loop-gain cross-over frequency, the compensator zero is used to cancel the converter pole, wz = wp , with a resulting cross-over frequency given by: gm R (14) fcross = fo . 3 The desired digital feedback lter was determined via the bilinear transformation (BLT) with pre-warping around the zero frequency, wz

b1

and Tf is the digital lter clock period. From the Inverse Z-transform, the desired discrete-time difference equation is given by: vm [k] = A1 ve [k] + A1 b1 ve [k 1] + vm [k 1] , (17)

where a possible block diagram suitable for hardware implementation is shown in Fig. 10. In order to maintain optimum feedback

ve[k]

+
1/z

A1 A1b1

vm[k]

Figure 10: Digital Feedback Filter Implementation

for variable load and universal input conditions, the lter coefcients, A1 and A1 b1 , of Fig. 10 must adaptively adjust to maintain suitable phase margin for closed-loop stability and a cross-over frequency sufciently below the line-frequency output voltage ripple for low distortion. Additionally, care must be taken in choosing and generating the digital lter clock frequency, ff , due to the line-frequency ripple, 2fl , and switching frequency ripple, fs , on the sampled output voltage. One option is to extract the line-frequency ripple and sample the output with a clock synchronized to twice the line-frequency. An on-chip anti-aliasing lter can then be used to lter out the switching frequency noise. V Conclusions A mixed-signal IC controller for single-phase PFC switching converters has been presented. The single-chip, high-performance controller combines analog and digital building blocks to achive operation at high switching frequencies and no external components or design required for high-performance, stable operation. Internal blocks were described with implementation examples given for boost and buck/boost type power stages, and experimental results from a 1.2 CMOS test chip were included. The proposed controller can be used to implement high-performance, low-harmonic rectier systems. It is suitable for operation over universal input voltage range, wide switching frequency range, and variable load conditions. Mixed-signal (analog and digital) ASICs, such as the PFC controller described in this paper, are proposed as an approach that would enable advanced, high-performance control functions in future power electronic systems.

[7] R. Zane, D. Maksimovi c, Non-linear-Carrier Control for HighPower-Factor Rectiers Based on Up-Down Switching Converters, IEEE Transactions on Power Electronics, Vol. 13, NO. 2, March 1998, pp. 213-221. [8] N. Jayaram, D. Maksimovi c, Power Factor Correctors Based Converters with Nonlinearon Coupled-Inductor Sepic and Cuk Carrier Control, IEEE APEC 98, pp. 468-476. [9] M. Chang, J. Lin, Y. Tzou, DSP-based Fully Digital Control of a AC/DC Converter with a Nonlinear Digital Current Mode Control, IEEE PESC 96, pp. 1702-1708. [10] A. Mitwalli, S. Leeb, G. Verghese, V. Thottuvelil, An Adaptive Digital Controller for a Unity Power Factor Converter, IEEE Transactions on Power Electronics, Vol. 11, NO. 2, 1996, pp. 374. [11] M. Tognolini, A. Rufer, A DSP based Control for a Symmetrical Three-Phase Two-Switch PFC-Power Supply for Variable Output Voltage, IEEE PESC 96, pp. 1588-1594. [12] H. Pinheiro, G. Jo os, K. Khorasani, Neural Network-Based Controller for Voltage PWM Rectier, IEEE PESC 96, pp. 1582-1587. [13] Unitrode Product Guide, High Power Factor Preregulator, UC3854A/B, Unitrode Integrated Circuits, Merrimack, NH, http://www.unitrode.com, 1998. [14] Analog Devices Product Guide, Single-Chip DSP Motor Drive Controller with PFC, ADMC331, http://www.analog.com, 1999. [15] G. Franklin, J. Powell, M. Workman, Digital Control of Dynamic Systems, Massachusetts: Addison-Wesley, 1992. [16] R. Bachik, A. Brockschmidt, C. Epperson, K. Yuen, Practical Aspects of Line-Line and Line-Ground Single Phase PFC, IEEE APEC 99, pp. 342-348. [17] S. Soclof, Design and Applications of Analog Integrated Circuits, New Jersey: Prentice-Hall, 1991. [18] http://www.mosis.com [19] R. Zane, D. Maksimovic c, Frequency scalable non-linear waveform generator for mixed-signal power-factor-correction IC controller, IEEE Custom Integrated Circuits Conference, San Diego, May 16-19, 1999.

References
[1] R. Mammano, R. Neidorff, Improving Input Power Factor A New Active Controller Simplies the Task, Power Conversion, Oct. 1989 Proceedings, pp. 100-109. [2] R. Redl, B. Erisman, Reducing Distortion in Peak-CurrentControlled Boost Power Factor Correctors, IEEE APEC 94, pp. 576-583. [3] C. Zhou, R. Ridley, F. C. Lee, Design and Analysis of a Hysteretic Boost Power Factor Correction Circuit, IEEE PESC 90, pp. 800-807. [4] Z. Lai, K. Smedley, Y. Ma, Time Quantity One-Cycle Control for Power Factor Controllers, IEEE APEC 96, pp. 821-827. [5] R. Erickson, Fundamentals of Power Electronics, New York: Chapman & Hall, 1997. [6] R. Zane, D. Maksimovi c, Modeling of high power factor rectiers based on switching converters with nonlinear-carrier control, IEEE PESC 96, pp. 1105-1111.