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JMP
Jump Unconditional
MEMORY BASED
RD WR HALT
R1MEM[ADDRESS] MEM[ADDRESS]R1
5-1-1: Instruction word design The instruction set given in Table 5-1 give 16 instructions at assembly language. The next step is to define instruction word, the purpose of Instruction word is to define mechanism to store the assembly based program inside memory. The assembly mnemonics are given in table 5-1 with op code, the instruction word defines how are certain program in Assembly is represented in Machine Language. RType- Register Type Instruction The register type instruction has two Register fields of 2-Bits. The register File will contain Four Registers. The instruction of RType Include all Arithmetic Instruction, AND, OR and CMP instructions. The R-Type instrution is 1-byte. OPCode(4Bits) Des Reg(2Bits) Src Reg(2Bits)
SRType- Single Register Type Instruction Single Register Type instruction include instructions with single register field. The remaining two bits are either given for Immediate Value as in MOV instructions or to Give Shift Amount. OPCode(4Bits) Branch Type Instruction All branching instruction are two byte instruction with second byte containing 8-Bit Address to address 256x8 Memory. The Src and Des Register Fields are donot care. OPCode(4Bits) Address (8 Bits) Memory Type Instruction The Memory Type Format is two byte instruction same as Branch, except for SRC/DES are not donot care. In Read Instruction Destination register is given and write instruction has Source register enabled. OPCode(4Bits) Address (8 Bits) SRCReg(WR Instruction) DesReg(RDInstruction) XXXXXXXXXX XXXXXXXXXX Des Reg(2Bits) Shift Amount /Immediate Value (2Bits)
Figure 5-1: Instruction Word for the instruction set given in Table 5-1
5-1-2: Conversion of Assembly Program into Machine Level Language
ISA also involve Address modes, however to keep the things simple we have not discussed address modes in this design. To Illustrate the Translation of Assembly code into machine level code Example 5-1 gives an assembly level code of program which sum all even numbers till 20. The memory of the design is Von Neuman with logical partitioning of Memory; however buses are separate for address and data. First 200 locations contain Code memory and next 56 locations contain data memory. Design Example 5-1: Translation of Assembly Level Code into Machine Level Code
The program will calcualte sum of even numbers till 20. Code is given in both C and aseembly level languages and possible machine level is given below. int sum; for (int i=0;i<=20;i+=2) { sum+=i; } 1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8 9 10 0110 0110 1101 200 0110 0000 0001 1010 5 1111 xx xx 11 00 10 xx 01 01 11 xx
MOV R0,2 MOV R1,2 RD R2,200 MOV R3,1 LOOP: ADD R0,R1 SUB R2,R3 BRNZ LOOP HALT
00 01 10 10 10 xx
Assembler maintains a table called Label Table, which is mostly used in Loops. The line-5 of assembly has label LOOP the address of this label is 5. The Line 9 of Machine Level code contains address 5.
PC
Register File
CONTROL UNIT
Memory ALU
256x8
DREG
Add_Mem(8)
Data_IM(2)
Sel_MData Sel_MAdd
MUX_DATA
MUX_ADD
IR
AREG
Figure 5-2: Micro Architecture of 8-Bit RISC Processor(Width of bus is 1 otherwise indicated)
register. Once the instruction is fetch the control Unit will execute the instruction depending on type of instruction fetch. The Op Code of the instruction in focus is used to determine what action should be taken to perform a relevant execution, this stage is called decode. The instruction is been fetch and it is known what instruction is brought (decode), finally the instruction is execute. The results of the execution are written back to the memory or register file, this step is called write back. The program is present in the memory, data path fetch, decode, execute and write back the program location by location. This operation is controlled by the Control Unit of the design.
Clock Cycle
5-3-1: Fetch Operation Figure 5-3 indicates fetching of Instruction from the memory. The program counter is initially zero it points the first location of the memory, on each fetch it is incremented to the next location by the program counter.
PC
Register File
CONTROL UNIT
Memory ALU
Dout_Mem
256x8
LD_DReg
DREG
Add_Mem
Data_IM
Sel_MData Sel_MAdd
MUX_DATA
MUX_ADD
IR
AREG
PC
Register File
CONTROL UNIT
Din_RFile
Memory ALU
256x8
DREG
Add_Mem
Data_IM
Sel_MData Sel_MAdd
MUX_DATA
MUX_ADD
IR
AREG
PC
Register File
CONTROL UNIT
Memory ALU
256x8
DREG
Add_Mem
Data_IM
Sel_MData Sel_MAdd
MUX_DATA
MUX_ADD
IR
AREG
5-3-4: Execute in Branch based instruction The Branch operation is shown in Figure 5-6, the Program Counter leaves it regular incremental process and jumps to address either on certain condition or unconditionally. The instruction word in Figure 5-1 indicates that the address where the branch is taken is kept in the second byte of the instruction. The second byte is read from the memory and store the result in program counter. The Dout_Mem is loaded into PC by asserting LD_PC and making SEL_MADD as 0.
PC
Register File
CONTROL UNIT
Memory ALU
256x8
DREG
Add_Mem
Data_IM
Sel_MData Sel_MAdd
MUX_DATA
MUX_ADD
IR
AREG
5-3-5: Read and Write Operations The read and write instructions share common first Clock Cycle as shown in Figure 5-7. The read/write instructions contain second byte with address. This is indirect address where the read/write is to be done. The data in second byte of read/write is only an address referring to location where either data is written in memory or to be read from memory.
PC
Register File
CONTROL UNIT
Memory
ALU
256x8
DREG
Add_Mem
Data_IM
Sel_MData Sel_MAdd
MUX_DATA
MUX_ADD
IR
AREG
The DOut_Mem contains the second byte of instruction which is feed back to AReg(Address register). For example the second byte of instruction contains 200 and this instruction is present at location 5 of program memory, then 200 will be feed back into AReg. As discussed in the Figure 5-7 that Address register will now contain the address at second byte of read instruction For example 200 while PC will still hold the address of active program memory i.e. 5. First address in PC is incremented to point to the next address i.e. 6.
PC
Register File
CONTROL UNIT
Memory ALU
256x8
DREG
Add_Mem
Data_IM
Sel_MData Sel_MAdd
MUX_DATA
MUX_ADD
IR
AREG
Figure 5-8 explains the second clock cycle of read operation while Figure 5-9 explains second clock cycle for Write operation. The AReg points to the indirect address, DOut_Mem has data from memory which is passed to register file through MUX_DATA.
PC
Register File
CONTROL UNIT
Memory ALU
256x8
DREG
Add_Mem
Data_IM
Sel_MData Sel_MAdd
MUX_DATA
MUX_ADD
IR
AREG
significance. Last but not least the move instruction passes the data to be moved on Data_IM line from the control unit. It is passed from MUX_DATA to the register File.
Register File
DOut2_RFile2(8)
module RFile(input RW_RFile,input [1:0] Add1_RFile,input [1:0] Add2_RFile,input [7:0] Din_RFile, output reg [7:0] DOut1_RFile,output reg [7:0] DOut2_RFile, input Clk,input Enb_RFile); reg [7:0]RF[3:0]; always@(posedge Clk) if(Enb_RFile==1) if(RW_RFile==0)//Read begin DOut1_RFile<=RF[Add1_RFile]; DOut2_RFile<=RF[Add2_RFile]; end else //Write begin RF[Add1_RFile]<=Din_RFile; DOut1_RFile<=8'd0; DOut2_RFile<=8'd0; end else begin DOut1_RFile<=8'd0; DOut2_RFile<=8'd0; end endmodule
5-4-2: Program File Figure 5-11 Show Design of Program Counter, its a special register with increment, data loading and Reset Facility in it. Program counter keep the current address of the program to be fetch, it is increment once in all 1-Byte instructions and incremented twice in two byte instructions. Program Counter point the memory location by location, however the normal flow of program counter may change in case of branch instructions.
PC
DOut_PC(8)
module PC(input INC_PC,input RST_PC,input LD_PC, input[7:0] Din_PC, output [7:0]DOut_PC,input Clk); reg [7:0]RPC; assign DOut_PC=RPC; always@(posedge Clk) if(RST_PC) RPC<=8'b0; else if(INC_PC==1) RPC<=RPC+1; else if(LD_PC==1) RPC<=Din_PC; Endmodule
LD_DReg Din_Reg(8)
Reg_8Bit
DOut_Reg(8)
module Reg_8Bit(input [7:0] Din_Reg,input Clk, output [7:0] DOut_Reg,input LD_DReg); reg [7:0]R; assign DOut_Reg=R; always@(posedge Clk) if(LD_DReg) R<=Din_Reg; else R<=R; endmodule
OpCode_ALU(3)
ALU
DOut_ALU(8)
ShAMT_ALU(2)
module ALU(input [2:0] OpCode_ALU,output reg[2:0] Flag_ALU,input [1:0] ShAMT_ALU,input [7:0] Din1_ALU,input [7:0] Din2_ALU,output reg [7:0] DOut_ALU); //ALU Operations always@(OpCode_ALU or ShAMT_ALU or Din1_ALU or Din2_ALU)
case(OpCode_ALU) 3'b000:DOut_ALU<=Din1_ALU+Din2_ALU;//add 3'b001:DOut_ALU<=Din1_ALU-Din2_ALU;//sub 3'b010:DOut_ALU<=Din1_ALU*Din2_ALU;//mul 3'b011:DOut_ALU<=Din1_ALU&Din2_ALU;//and 3'b100:DOut_ALU<=Din1_ALU|Din2_ALU;//or 3'b101:DOut_ALU<=~Din1_ALU;//cmp 3'b110:DOut_ALU<=Din1_ALU>>ShAMT_ALU;//slr 3'b111:DOut_ALU<=Din1_ALU<<ShAMT_ALU;//sll endcase ///For Flags always@(Din1_ALU or Din2_ALU or DOut_ALU) begin if(Din1_ALU>Din2_ALU) Flag_ALU[2:1]<=2'b00; else if(Din1_ALU==Din2_ALU) Flag_ALU[2:1]<=2'b01; else if(Din1_ALU<Din2_ALU) Flag_ALU[2:1]<=2'b10; else Flag_ALU[2:1]<=2'b11; if(DOut_ALU==0) Flag_ALU[0]<=1'b1; else Flag_ALU[0]<=1'b0; end endmodule
modules. Memory is not part of Data path so it shown as separate module. It is important to consider the sequential and combinational elements. The drives are always wire and does not have storage capabilities unless have register in them.
PC
Register File
BUS_ADD
DATA PATH
Enb_RFile Din_RFile
WRFOut11
WRFOut12
BUS_DATA
Din_Mem
Memory
256x8
Add_Mem
OpCode_ALU
WPCOut
CONTROL UNIT
Flag_ALU ShAMT_ALU
ALU
WALUOut
LD_DReg
DREG
WDROut
DOut_Mem
Data_IM
BUS_ADD
Sel_MData Sel_MAdd
MUX_DATA
BUS_DATA
MUX_ADD
LD_IR Inst
IR AREG
LD_AReg
RW_Mem Enb_Mem
Figure 5-14: Modifications in Data Path (All wires are shown in Italic)
The code of data path given in figure 5-15, connection wires are shown as separate wires after port definition is made.
module DP_RISC8Bit(input INC_PC,input LD_PC,input RST_PC,input RW_RFile, Add2_RFile,input RW_Mem,input [2:0] OpCode_ALU, input [7:0] Add1_RFile,input [7:0]
LD_DReg,input [7:0] Data_IM, input [1:0] Sel_MData, input Sel_MAdd,input LD_IR, output [7:0] Inst,input Clk, input LD_AReg, output [7:0] Din_Mem, output [7:0] Add_Mem,input [7:0] DOut_Mem, input Enb_RFile); wire [7:0]BUS_DATA,BUS_ADD; wire [7:0]WRFOut1,WRFOut2,WPCOut,WALUOut,WDROut; assign Din_Mem=WRFOut1; RFile R1(.RW_RFile(RW_RFile),.Add1_RFile(Add1_RFile),.Add2_RFile(Add2_RFile),.Din_RFile(BUS_DATA),
.Din2_ALU(WRFOut2),.DOut_ALU(WALUOut)); MUX_ADD MA1(.Din1_MADD(DOut_Mem),.Din2_MADD(WPCOut),.Sel_MADD(Sel_MAdd),.DOut_MADD(BUS_ADD)); Reg_8Bit DReg(.Din_Reg(WALUOut),.Clk(Clk),.DOut_Reg(WDROut),.LD_DReg(LD_DReg)); Reg_8Bit AReg(.Din_Reg(BUS_ADD),.Clk(Clk),.DOut_Reg(Add_Mem),.LD_DReg(LD_AReg)); MUX_DATA MD1(.DIn1_MData(WDROut),.DIn2_MData(Data_IM),.DIn3_MData(DOut_Mem),.DIn4_MData(8'dz), .DOut_MData(BUS_DATA),.Sel_MData(Sel_MData)); Reg_8Bit IR(.Din_Reg(BUS_DATA),.Clk(Clk),.DOut_Reg(Inst),.LD_DReg(LD_IR)); endmodule
All intermediate wires are shown in italic in figure 5-14. The address bus and data bus uses BUS_ADD or BUS_DATA respectively. The interconnection WRFOut1 and WRFOut2 between Register File and ALU. The outputs of Register Program Counter, ALU and Data Register is used by WPCOut,WALUOut and WDROut respectively. There are three instances of Reg_8bit are used in the code Instruction register, data register and address register. However for program counter uses separate module, because it requires special function like increment of program counter.
Table 5-4 show possible states for the ASMD, Figure 5-15 show the modification in data path as required by ASMD.
PC
Register File
CONTROL UNIT
Din_Mem
Memory ALU
Dout_Mem
256x8
LD_DReg
DREG
Add_Mem
Data_IM
Sel_MData Sel_MAdd
MUX_DATA
MUX_ADD
IR
AREG
Figure 5-16: Modifications in Data Path before writing ASMD of the control unit
Figure 5-16 shows the ASMD of the Processor with all states shown in table 5-4. Every instruction will be fetch and decode, after decode the type of instruction defines which will be the next state. For R-Type instruction Execute_Reg and Execute_WB. For Shift type instruction which is SR Type, Flow of R-Type instructions are followed. While for Move Type instruction S_Exec_SR is acquired. All Two bytes instructions S_Fetch2Byte is used. Branch instruction will use S_Branch. The read and write instruction follow common execute cycle. After execute Read and write will use different write back stats.
S_RST
RST_PC->1 LD_PC->0 LD_AReg->0 LD_IR->0 LD_DReg->0 Enb_RFile->0 Enb_Mem->0 INC_PC->0
S_Fetch
Sel_MAdd->1 LD_IR->1 Enb_Mem->1 LD_PC->0
Enb_RFile->0
S_Decode
LD_AReg->1 Sel_MData->2 RST_PC->0
RW_Mem->0
INC_PC->0
S_Exec_Reg R-Type
Enb_RFile->1 RW_RFile->1 Add1_RFile->DesReg Add2_RFile->SrcReg OpCode_ALU->OCode LD_DReg->1 INC_PC->0 ShAMT_ALU->SA
S_WB_Reg
LD_Dreg->0 Sel_MData->0 RW_RFile->0 Enb_RFile->1 Add1_RFile->DesReg
S_Fetch2Byte
Sel_MAdd->1 INC_PC->0 LD_AReg->1
B Type
S_Branch
INC_PC->0 LD_PC->1 Sel_MAdd->0 LD_AReg->0
S_Exec_RW M Type
Sel_MAdd->1 INC_PC->1 LD_AReg->0
S_WB_RD RD HALT
LD_AReg->0
Enb_RFile->1 Sel_MData->2 RW_RFile->0
Add1_RFile->DesReg
INC_PC->0
S_WB_WR WR S_HALT
LD_AReg->0
RW_RFile->1 Enb_RFile->1 RW_Mem->1
5-5-1: Coding Control Unit All States and Instructions are defined as constant in the start and Figure 5-17 shows the Implementation of ASMD shown in figure 5-16. The implementation is orthodox ASMD style from chapter-3.
always@(posedge Clk or posedge RST) if(RST==1) State<=S_RST; else case(State) S_RST:State<=S_FETCH; S_FETCH:State<=S_DECODE; S_DECODE: case(OCode) ADD,SUB,MUL,AND,OR,CMP: State<=S_EXEC_REG;//R-Type Instruction SLR,SLL:State<=S_EXEC_REG;//Shift Type Instruction for SR Type MOV:State<=S_EXEC_SR;//SR Type Mov instruction BRZ,BRNZ,BRLT,JMP: State<=S_BRANCH;//Branch Instruction RD,WR: State<=S_EXEC_RW;///Memory based instruction HALT:State<=S_HALT;//Halt endcase S_EXEC_REG:S_WB_REG; S_EXEC_SR,S_BRANCH,S_WB_REG,S_WB_RD,S_WB_WR:State<=S_FETCH; S_EXEC_RW:if(OCode==RD) State<=S_WB_RD; else if(OCode==WR) State<=S_WB_WR; else State<=S_HALT;//Halt default: State<=S_HALT;//Halt endcase
Figure 5-19 show the signal assignment of State transition reflected in Figure 5-18.
always@(State) case(State) S_RST: begin RST_PC<=1; LD_PC<=0; LD_AReg<=0; LD_IR<=0; LD_DReg<=0; Enb_RFile<=0; Enb_Mem<=0; INC_PC<=0; end S_FETCH: begin Sel_MAdd<=1; LD_AReg<=1; LD_IR<=1; Sel_MData<=2'd2; Enb_Mem<=1; RST_PC<=0; LD_PC<=0; RW_Mem<=0; Enb_RFile<=0; INC_PC<=0; end S_DECODE: begin DesReg<=Inst[5:4]; SrcReg<=Inst[7:6]; SA<=Inst[7:6]; IVal<=Inst[7:6]; OCode<=Inst[3:0]; INC_PC<=1; LD_AReg<=0; LD_IR<=0; Enb_Mem<=0; Enb_RFile<=0; end S_EXEC_REG: begin Enb_RFile<=1; RW_RFile<=1; Add1_RFile<=DesReg; Add2_RFile<=SrcReg; OpCode_ALU<=OCode; LD_DReg<=1; INC_PC<=0; ShAMT_ALU<=SA; end S_WB_REG: begin LD_DReg<=0; Sel_MData<=0; RW_RFile<=0; Enb_RFile<=1; Add1_RFile<=DesReg; end S_EXEC_SR: begin Data_IM<=IVal; Sel_MData<=2'd1; Enb_RFile<=1; RW_RFile<=0; Add1_RFile<=DesReg; INC_PC<=0; end S_BRANCH: begin INC_PC<=0; Sel_MAdd<=0; LD_PC<=1; LD_AR<=1b0; end S_EXEC_RW: begin Sel_MAdd<=1; LD_AReg<=1; INC_PC<=0; end
S_WB_RD: begin LD_AReg<=0; Sel_MData<=2'd2; Enb_RFile<=1; RW_RFile<=0; Add1_RFile<=DesReg; INC_PC<=1; end S_WB_WR: begin LD_AReg<=0; Enb_RFile<=1; RW_RFile<=1; RW_Mem<=1; Add1_RFile<=DesReg; Enb_Mem<=1; INC_PC<=1; end endcase
Exercise Problems
5-1: If the instruction set given in Table 5-1 does not have multiply instruction we would require it using assembly routine. Write Assembly routine to implement multiplication instruction using 15 Instructions given in Table 5-1. 5-2: The processor in Figure 5-16 contain data path having two flags. Modify the flag mechanism and add flagging mechanism with following flags.
C
Carry
AC
Auxiliary Carry
OV
Over Flow
Z
Zero
CP1
Compare-1
CP2
Compare-2
Write Verilog code, behavioral level block for ALU module to implement the flagging Logic. Over Flow is discussed in 6-1-5. 5-3: The process discussed in section 5-3 contains mov instruction to move immediately value into Din_Mem register File. Modify the architecture given in Figure P 5-3 to add a logic to move value from register to register.
RFile
ALU
Data_IM Mem_Out
MUX_DSEL
5-4: The instruction register is passed directly to the control unit and it issues OpCode and Shift amount to ALU, Source and destination address to Register File and determines the type of instruction. Come up with the architecture where only 4-Bit instruction type is passed to the control unit. The source, destination addresses and OpCode are directly passes in the datapath instead of routing through the control unit. Draw the architecture of such configuration. 5-5: Assume that the memory is divided into 3 Partitions Code memory, Data Memory and The Stack. Add two new instructions push and pop. The value to be pushed in the stack or popped form the stack is taken or stored in the register file respectively.
0-199
Code Memory
200-238
Data Memory
239-255
Stack
Push R0
Pop R0 //Pop Value from the top of the stack into Register R0 Recommend possible changes in data path and control Unit Draw relevant portion of data path only, recommend changes in ASMD of control Unit after Fetch and decode. All other stages are not required.
5-6: Generally the registers in the processor are visible in the assembler. UART transmitter is used to transmitt all values to the computer. Control Unit send all the registers to the computer once halt is encountered in the program. Modify the ASMD to enable UART Transmission once HALT is encountered.
UART_TX
Processor
Assembler
Register File
CONTROL UNIT
ALU
Data_Ready
RST_UART T_Byte
UART_TX
5-7a: Consider Instruction set of 21 instructions given in the table P5-7. There are 16 registers and each register is 16-bit wide. Design Instruction word for 16-Bit architecture. ADD ADDi SUB MUL AND OR XOR ADD R0,R1 ADDi R0,2 SUB R0,R1 MUL R0,R1 AND R0,R1 OR R0,R1 XOR R0,R1 CMP SLL SLR MOV MOVR BRZ BRNZ CMP R0 SLL R0,1 SLR R0,1 MOV R0,3 MOVR R0,R1 BRZ LABEL BRNZ LABEL BRLT BREQ BRG JMP RD WR HALT BRLT LABEL BREQ LABEL BRG LABEL JMP LABEL RD R0,200 WR R0,200 HALT
5-7b : The instruction set given in Pb 5-7a contains two instructions SLL and SLR for shifting operation. Give the mechanism to merge the instructions into single shift instruction which can give shifting in both directions . 5-8a: Section 5-6 defines the retiming of the processor where synchronization of data path and control unit was done by premetive signal assignment. Another way of delaying the state transition of control unit is to insert dummy states to generate no operation, This gives relaxation time for data path to transact. Write the behavioural block for state transition of control unit or draw ASMD to reflect the change through delay states. 5-8b: This problem is extension of pb 5-8a. Another way of synchroniztion of data path and control unit is to make the clock of control unit slow so that it transact accordingly. If control unit of processor is made to move on slow clock what possible complication datapath can present. 5-9: If code and data memory were different, what difference will data path present. What other registers will be required? Give possible modification in ASMD of control Unit? 5-10: Consider mechanism of processor to handle routines/macros in assembly. Generally branches are created towards sub routines. This requires special instruction to create a jump with return. More registers are required to pass argument and to return the value from the register File. The 16x8 register file is so divided that the last four registers can be used to pass four argument. The value is returned into first argument register. If procedure call is not in progress these four register can be used as general purpose registers. A new instruction JR(jump with return address) is added to return after jump. Propose modification in control unit to accommodate this sort of jump. 12 x 8
R0 R1 R2 R3 5-11: The register file given Section 5-3 contains process where consective reads and writes are not
possible. Modify the architecture in a way that data register is not requred. Change the register file which can allow consective reads and write. Add1_RFile
RFile
Add2_RFile
ALU
DReg
MUX_DSEL
5-12:Figure 5-x presents modified Von Neuman architecture where the memory space is shared between code and data. The von Neuman generally have data and address shared. Draw a data path with shared data and address buses. 5-13: If the architecture is 32 bit and memory has each word equal to 1 byte. This means a oe instruction will be stored on 4-Locations in the memory. The branch in this case relative to memory program storage is deceptive. Think a way of achieving this possible type of branch. How to scale a address so that a single branch represent 4-Locations Jump? 5-14a: In 32-Bit architecture PC will represent 232 memory. Similar can be said about AR, Suppose a memory is of 216 location, hwo to ensure that memory cannot exceed 216 address possible location. Think a way that lower left 16 bit only contain zero. 5-14b: The control unit can also be used to prevent PC of exceeding 216 locations. Device a mechanism that control unit can prevent program counter for exceeding 216 Locations. Modify Data Path in a way that it does not allow the address calculation more than the more then code memory.
5-15: The PC counter has control signal INC_PC which increment the program counter by 1. Suppose PC does not have the signal to increment from Control Unit. Redraw the data path to accommodate increment PC using ALU. What possible modification can be done to facilitate the ALU to increment the PC. 5-16: The branching mechanism of process given in Chapter-5 is absolute branching where PC is exactly replaced with the address of branching. Another way of branching is PC relative addressing. For example if PC Is currently at 20 and jump at 4 or 35 is required. Instead of replacing PC with 4 or 36, 16 is added or subtracted from PC respectively. The branching process done by realtive of earlier PC address is called PC relative address. Modify datapath and control unit to make PC relative addressing. 5-24: The multiplication of two 8-bit number can be a product ofa 16-bit. However the data register attached with the ALU is only 8-bit. The architecture given in section 5-4 does not caters for this constriants. The only wat to get out of this problem is to let the programmer know that the result cannot exceed 8-bit. Suggest possible architecture for handling 16-Bit product results.