HIGH SPEED ADCS DEDICATED FOR WIDEBAND WIRELESS RECEIVERS

M. Sawan, A. Djemouai, K. El-Sankary, H. Dang, A. Naderi, Y.Savaria, and F.Gagnon Polystim Neurotechnology Laboratory, Department of Electrical Engineering, Ecole Polytechnique of Montreal, Montreal (QC), Canada ABSTRACT In this paper we present and discuss the design of different architectures of high-speed analog-to-digital converters (ADCs) dedicated for wideband wireless receivers such as software-defined radio systems. Our interest concerns three different architectures: a pipelined 10-bit, 50 MS/s, a Flash 6-bit, 1-GS/s, and a band-pass Sigma-Delta 6-bit, 2-GS/s. A first version of the pipelined ADC and the Flash ADC was fabricated. As part of the Sigma-Delta ADC, a resonator operating at 2-GHz was fabricated. In addition to the design of these ADCs, a PCB card that supports these ADCs within a wireless receiver prototype was designed and tested. The ADCs technology of fabrication is the CMOS 0.18um for the pipelined and the flash, and the CMOS 0.13um for the band-pass Sigma-Delta. I. INTRODUCTION The accessibility of high performance sub-micron integrated circuits (IC) and the high rate of the proliferation of mobile communication applications have created enormous needs for the development of new generations of wireless receivers. Examples of such receivers are the wireless personal area networks -WPAN(2.4 GHz) and wireless local-area network -WLNA- (5 GHz). Presently, all around the world, large efforts are oriented for the development of efficient reconfigurable, multi-band and multi-standard wireless receivers known as software-defined radio (SDR). Practically, the most feasible solutions for these receivers are either direct conversion or intermediate frequency (IF) transceivers. Here, advantages of digital hardware and software programming resources are highly exploited in order to perform digitally almost all the receiver functionality. By doing so, the constraints of the receivers analog parts are highly relaxed since in this case, the digitization of the received signal is performed just after the receiver antenna. This means that in SDR systems, the analog-todigital converter (ADC) is placed as close as possible to the antenna and all the processing and the required demodulation operations are performed digitally. However, in such cases, the performances of the receiver are principally determined by those of the ADC. In fact, for SDR receivers, the ADC should comply with stringent characteristics such as high-speed operation, large input bandwidth, high resolution, and high spurious-free dynamic range (SFDR). In order to deal with these constraints, concepts of sub-sampling and over-sampling are usually exploited in SDR applications [1, 2]. Other constraints such as power consumption and area have to be also considered. Among the existing ADC architectures, the pipelined, the Flash, and the Sigma-Delta architectures are the most favorable for the design of ADC that meet the SDR specifications. In this paper, we present and discuss our teams ongoing project that aims the design of three types of ADCs dedicated for wireless SDR receivers. The ADC architectures which are considered here are: Pipelined, Flash and band-pass Sigma-Delta converters. In section II, we present a 10-bit, 50 MHz pipelined architecture. In section III, we present a 6-bit, 1 GS/s ADC. In section IV, we present the proposed architecture for a 6 bit, 2 GS/s band-pass Sigma-delta ADC. Finally we discuss in section V the design of a PCB dedicated to include the designed pipelined ADC in wireless receiver prototype. II. PIPELINED ADC One of the suitable ADC architecture for the present and next wireless receiver generations is the pipelined ADC [3] owing to its wide input bandwidth and high-resolution capability. In this context, a 10-bit, 50 MHz, pipelined ADC has been implemented and fabricated. As shown in Fig. 1, this ADC includes nine cascaded stages. Each stage is composed of one multiplying digital to analog converter (MDAC) and one fully-differential 1.5 bits ADC.
Di Vin V1 Vi Stage i Vi+1 Vp DP Stage P

S/H

Vi

SHA Vdaci

G
ADC DAC Di

Vi+1

MDAC

Fig. 1. Block diagram of a pipelined ADC.

The MDAC is built around switched capacitor techniques and the 1.5 bits ADC uses dynamic comparators and preamplifiers. The ADC includes also an input fullydifferential sample-and-hold (S/H) that enables sampling for high frequency signals without distortions. Moreover, digital calibration was used to minimize the effect of the offset voltage and the finite gain of the operational amplifier of each stage.

0-7803-8935-2/05/$20.00 2005 IEEE.

III. FLASH ADC A preliminary version of a 6-bit flash ADC using MCML circuits was implemented with the TSMC 0.18-um CMOS technology[4]. The block diagram of this flash ADC is depicted in Fig. 2. The resistive ladder provides reference voltages to 83 preamplifiers, where 20 dummies are used to fulfill the averaging requirement [5]. The preamplifiers, along with the 63 comparators, convert the signal coming from the S/H into thermometer codes (TC). At the encoder stage, TC codes are translated to binary codes (BC). The encoder uses series of AND gates and a quasi-gray encoding ROM to correct first and second order bubbles occurring in TC codes [6]. The differential nature of the S/H, preamplifiers and comparators greatly removes second-order distortions, which improves the ADC SFDR. In order to deal with the design high-speed limitations, we used MOS currentmode logic (MCML), instead of CMOS logic, for designing the ADC critical blocks. In fact, MCML techniques have shown effective increasing of the conversion rate and reducing the power consumption of the ADC.

defeated by the well-known disadvantages of mixers and filters in the receiver architectures [8]. In order to accommodate the BSD modulation over higher IF band, a conventional structure of BSD that exploits subsampling at the quantizer (Fig. 3), was developed in [9]. This architecture provides the possibility of data conversion at high frequencies. However, many problems due to high-Q bandpass filters and its automatic tuning make it undesirable for radio frequencies. In addition, two correlated frequencies are necessary and any phase-error between them reduces SNR at the output signal. As far as the bandpass filter, it should not change the input signal, and just quantization noise is shaped by that, the up-conversion of the output signal in the feedback path seems to be unreasonable. The feed forward bandpass filter can be replaced by a lower IF one in the feedback path without mixer.
Bandpass filter Input +_ Quantizer Output fS
IF2

H(s)
Center freq.= C

ASin(Ct)

Mixer

fM

Fig. 3. Bandpass Sigma-Delta modulator using subsampling. The proposed structure, which is a type of Delta Modulator (DM), is shown in Fig. 4. Using this structure, it is possible for the center frequency of the modulator to be in the multiGiga hertz range. The only inconvenient to mention here is the integrator linearity. Furthermore, a low frequency bandpass filter with realistic small Q-factors can be used in the modulator feedback. Also, we have to note that the complexity of the proposed structure is very small compared to the conventional BSD. The feedback bandpass filter should however be continuous-time to avoid any aliasing.
Quantizer

Fig.2. Block diagram of a 6-bit flash ADC.

Input

Output

+_

+_

ASin(Ct)

fS Bandpass filter

IF2

IV. BAND-PASS SIGMA-DELTA ADC Bandpass Sigma-Delta modulators (BSD) are ideally suited for use in wireless receivers, where high dynamic range is required over the bandwidth of the signal to be down-converted. Interferes are also corrupted by quantization noise and would be removed after digital filers. However it requires high over-sampling-ratio that limits severely its applications to low-IF in CMOS technology [7]. Consequently, the advantages of BSD are

Bandpass filter

H(s)
Center freq.= IF2

H(s)
Center freq.= IF2

Fig. 4. Proposed structure of the BSD

V. TEST OF ACHIEVED ADCs A PCB that allows using the designed ADCs within a wireless receiver prototype was fabricated and tested (fig. 5).

The first version of this card aims to support two 10-bit, 50-MHz ADCs, the fabricated pipelined ADC and a commercial pipelined one (AD9215). Only one of the two ADCs can be used at a time. The commercial ADC is selected such that its performances are equivalent or close to those of the fabricated one. At this time, the PCB is validated only with commercial ADC, because the testing and debugging process of the fabricated ADC are not completed yet.
IF input - LPF: Differential Low-pass filter - DA: Differential amplifier - SDA: Single to differential amplifier - DSA: Differential to Single amplifier SDA - VGA: Voltage Controlled Gain amplifier

m. Three chips of these ADCs are being fabricated and few previous versions are under test. The post-layout simulation of the pipelined ADC were evaluated using an input fullscale sine-waveform with a frequency equal to 2.5 MHz and a sampling frequency equal to 50 MHz. Fig. 6 shows the power spectrum of digital output of the ADC. The signal-tonoise-and-distortion ratio (SNDR) is equal to 61 dB that leads to an effective number of bits (ENOB) of 10 bits. The SFDR is 73 dB. The differential non-linearity (DNL) and integral nonlinearity (INL) were found to be 0.55 LSB and 0.5 LSB respectively. Table 1 summarizes all the obtained results.
0 -20

fsamp Output digital interface

-40 ] B d [ D S P -60 -80 -100 -120 0 0.5 1 1.5 Frequency [Hz] 2 2.5 x 10
7

LPF DA VGA

Fabricated ADC

Commercial ADC fsamp

DSA Analog output

Fig. 5. Simplified block diagram of the test PCB

Fig. 6. Spectrum of the output of the 10-bit pipelined ADC. Table 1: Simulated performance of the pipelined ADC.

The card comprises mainly a conditioning input stage, a filter, a variable gain amplifier (VGA), two output amplifiers, and two ADCs. Moreover, it includes a voltage level translator and many different circuits which generate all the ADCs required bias currents and reference voltages. The conditioning input stage is based on a fully differential operation amplifier (opamp) and its task is to convert the IF input signal from single to differential. The second stage is differential second order Butterworth low-pass filter built around a differential opmap. The cut-off frequency this filter is fixed to the half of the sampling frequency (fsamp = 50 MHz). The VGA (AD8370) is used to adjust the amplitude of the IF input signal such that to meet the ADCs input dynamic range (DR) requirement. The VGA gain can be digitally controlled in the range of -11 dB to +35 dB. Following the VGA, a differential amplifier is used to drive the inputs of the ADCs. Another differential-to-single amplifier is also used to sense the analog output of the VGA for other use. VI. RESULTS The architectures of pipelined, flash, and band-pass sigma-delta ADCs were designed, modeled and carefully simulated. The pipelined and the flash ADCs were built in TSMC 0.18m 1P6M mixed signal CMOS process with MiM capacitors. The band pass filter build in CMOS 0.13

Technology ENOB Conversion rate Active area SNDR SFDR INL DNL Input range Supply voltage Power dissipation

0.18um CMOS 10-bit 50 MS/sec 1.4 mm2 61 dB 73 dB 0.55 LSB 0.5 LSB 1.2Vpp 1.8 V 32 mW

For the case of the Flash architecture, a 6 bit, 1 GS/s ADC was also designed and fabricated. Post-layout simulations using parasitic extraction have shown that the ADC operates at 1.25 GHz with an effective resolution bandwidth (ERBW) locating between 585 MHz and 600 MHz. The power consumption of this full-flash ADC, including the clock buffer, is approximately equal to 260 mW. Table 2 summarizes the post-layout simulation results.

Table 2. Simulated results of the flash ADC.

140 120 100 Power [dB] 80 60 40 20 0 Input frequency = 5 MHZ, Sampling frequency = 50 MHz

Resolution Sampling Rate SNDR/SFDR Power Input Range Common ERBW Resolution Sampling Rate SNDR/SFDR Power

6-bit 1.25 GHz 37.79 dB/45.84 260 mW 460 mVp-p 1.5 V 385 600 MHz 6-bit 1.25 GHz 37.79 dB/45.84 260 mW

0.5

1 1.5 Frequency [Hz]

2.5 X 107

For the case of the sigma-delta architecture, a first version of a 4th order integrated filter (resonator) was also designed and sent for fabrication. Simulation results of the proposed modulator are shown in Fig. 7. Signal to noise ratio at the output of the modulator is 51 dB for a 2 GHz input signal with 5 MHz bandwidth. The second IF is placed at 20 MHz when the signal is sampled at 990 MS/s.

Fig. 8. DFT corresponding to experimental digital output of the test PCB card.

ACKNOWLEDGMENTS Acknowledgements are due to NSERC, Prompt Qubec and CMC for the financial and facilities supports, and to Design Workshop Technologies, LTRIM Technologies, and Ultra Electronics Tactical Communications Systems for their technical inputs to achieve this project.
REFERENCES
[1] X. Li, and M. Ismail, Multi-Standard CMOS Wireless Receivers: Analysis and Design, Kluwer Academic Publishers, 2002. [2] J.A. Wepman, "Analog-to-Digital Converters and Their Applications in Radio Receivers," IEEE Communications Magazine, Vol. 33, no. 5, pp. 39-45, May 1995. [3] K. El-Sankary and M. Sawan, Low power, low voltage, 10bit50MSPS pipeline ADC dedicated for front-end ultrasonic receivers, IEEE ICM, pp. 833-836, 2002. [4] H. Dang, M. Sawan and Y. Savaria, A novel approach for

Fig. 7. Power spectrum of the BSD output signal.

implementing ultr-high speed flash ADC using MCML circuits, IEEE International Symposium on Circuits and Systems
(ISCAS) 2005. [5] P. Hui, A.A. Abidi, Spatial Filtering in Flash A/D converters, IEEE Transactions on Circuits and Systems, Vol. 50, no. 8, pp. 424436, Aug. 2003. [6] Y. Akazawa et al.,"A 400MSPS 8b flash AD conversion LSI," IEEE Solid-State Circuits Conference, pp. 98-99, Feb. 1987. [7] E. H. Dagher, P. A. Stubberud, W. K. Masenten, M. Conta, T. V. Dinh, A 2-GHz analog-to-digital delta-sigma modulator for CDMA receivers with 79-dB signal-to-noise ratio in 1.23-MHz bandwidth, IEEE Journal of Solid-State Circuits, Vol. 39, No. 11, Nov. 2004. [8] B. Razavi, Design considerations for direct conversion receivers, IEEE Transaction on Circuits and Systems -II, Vol. 44, No. 6, June 1997. [9] Gourgue, F.; Bellanger, M.; Azrouf, S.; Bruneau, V.; A bandpass subsampled delta-sigma modulator for narrowband cellular mobile communications, IEEE International Symposium on Circuits and Systems (ISCAS), Vol. 5, pp. 353-356, 1994.

Finally, the design and evaluation of the dedicated PCB to test the pipelined ADCs in a Wireless receiver have being completed. In Figure 8, we report the DFT which was carried on a collection of experimental digital outputs of the PCB card.
VII. CONCLUSIONS

We reported our undertaken researches concerning the design of three different ADC architectures dedicated for wideband receivers such as software-defined radios. We also discussed briefly the architecture of a PCB card, which was designed for the sake of demonstrating the use of the pipelined ADC within a wireless receiver prototype.