Verilog HDL Basics

Presenter: Dr. Abhijit Asati Abhijit asati@bits-pilani Abhijit_asati@bits pilani.ac.in ac in

What is an HDL?
An HDL is NOT a software programming language Software Programming Language

Language which can be translated into machine instructions

and d then h executed d on a computer Eg. C, Perl, Python Hardware Description Language Language g g with syntactic y and semantic support pp for modeling g the temporal behavior and spatial structure of hardware VHDL: (Very High Speed Integrated Circuit (VHSIC) H d Hardware D Description i ti Language L Verilog: Verifying Logic HDL

Abstraction levels in Digital IC Design:

Application of HDLs :

Why HDLs?

For designs with just a few gates, it was possible to verify these circuits on paper or with breadboards

As designs grew, designers began using gate-level models described in a HDL for verification.

In larger and more complex designs, for early highlevel design exploration, these gate-level models are at too low-level for the initial specification

VERILOG HDL Verilog HDL was the intellectual property of gateway design automation. GDA was privately i t l h held ld by b Dr. D Prabhu P bh Goel G l -1983 1983 Cadences ownership of verilog HDL made it more essential for EDA companies. IEEE Standards: IEEE 1364 1995 IEEE 1364 2001 IEEE 1364 2005

Ab t ti Levels Abstraction L l in i Verilog V il

Gate Level Modeling Data Flow Modeling g Behavioral Modeling g Switch Level Modeling

Usually, codes are written using a mix of gate-level, dataflow, and b h i l models behavioral d l mix i n match! t h!

Why levels?
Gate level Modeling offers control over hardware gates like : AND , OR OR, XOR XOR, NAND NAND, NOR NOR, NOT and their interconnections. Dataflow modeling gp provides: shielding from this excessive attention to details shows how data flows between blocks. Behavioral modeling: Similar to programming in C Little concern as to actual hardware implementation

IDENTIFIERS: Identifiers are made of: alphanumeric character, the underscore or the dollar sign ($) other characters like ~,!, #, %, *, (, ) etc.. are not allowed Identifiers are case sensitive. Identifiers start with an alphabetic character or an underscore only. They y cant start with number or a $ sign. g Keywords cant be used as identifiers. KEYWORDS: Keywords are in lowercase. reg value; input clk; // where reg is keywords and value is an identifiers

Data Types: Nets

Can be thought as hardware wires driven by logic Value set for wire: { 0,1,X,Z } Various types of nets
wire wand d wor

(wired-AND) (wired AND) (wired-OR)

e.g: e g:
wire a; wire b,c; wire d=1b0; wire [7:0] bus; wire [31:0] bus A, , bus B, , bus C; wand b; wor x;

Nets
In following g example: p Y is evaluated, , automatically, every time A or B changes
A B A Y B Y

wire Y; // declaration assign Y = A & B; wand Y; // declaration assign Y = A; assign Y = B;

Registers
R Registers i retain i value l until il another h value l is i placed l d on them. h reg data type can be declared as: vectors (multiple bit widths) If bit width is not specified, the default is scalar ( 1-bit ). reg eg assignments ss g e s are e always w ys do done e inside s de a always w ys o or initial b block oc reg A = C = A = C = A, 1; A; 0; 0; C; // C gets the logical value 1 // C is still 1 // C is now 0

Register values are updated explicitly!!

INTEGER: -(231-1) to +(231-1) e.g. g integer counter; initial counter=-1; REAL: REAL e.g. real delta; initial begin delta = 4e10; delta = 2.13; end

TIME : A special time register data type is used in verilog to store simulation time. eg e.g. time save_sim_time; save sim time; initial save_sim_time = $time; // //Save the h current simulation i l i time i ARRAYS: Allowed for reg, integer & time e.g. g integer count [0:7];// count[0] to count[7] reg bool [31:0]; //bool[31] to bool[0] time chk_point chk point [1:100]; // chk_point[1] to chk_point[100] PARAMETERS: PARAMETERS Constants C can be b defined d fi d in i a module d l by b the h keyword parameter. g e.g. parameter port_id=5; parameter cache_line_width = 256;

Hierarchical Design g
Top Level Module Sub-Module 1 Sub-Module 2

Basic Module 1

Basic Module 2

Basic Module 3

e.g.

Full Adder

Half Adder

Half Adder

Gate Primitives

and nand or nor xor xnor not buf b f

Properties of these gates are: Execute E t in i parallel ll l Order independent Continuously active

Gate Level
A B C S

HALF ADDER module halfadder(s,c,a,b); input a,b; output s,c; xor g1(s,a,b); and g2(c,a,b); endmodule

A B

Half Adder

Hierarchical design: Full Adder

in1 in2 A B

Half Adder 1 ha1

S C

I1 I2

A B

Half Adder ha2

S C I3

sum

cout

cin

module fulladder(s,cout,a,b,cin); fulladder(s cout a b cin); input a,b,cin; output s,cout; wire c1,s1, c2; halfadder ha1(s1,c1,a,b); halfadder ha2(s,c2,s1,cin); or o1(cout,c2,c1); endmodule d d l
a b A B

Half Adder 1 ha1

s1 c1

A B

Half Adder ha2

s c2 01

sum cout

cin i

Other Full Adder

module FA (Sum,Cout); ( , ); output Sum,Cout; reg A,B,Cin; wire x1,x2,x3,x4,x5,x6; nor (x1,A,B); nand d (x2,A,B); ( 2 ) not (x3,x2); nor (x4,x1,x3); not (x5 (x5,Cin); Cin); xor (Sum,x4,Cin); or (x6,x1,x5); nand(Cout,x2,x6);

initial begin $monitor("A = %b B = %b Cin = %b Sum = %b Carry = %b",A,B,Cin,Sum,Cout); , , , , , ); A=0; B=0; Cin=0; #3 A= 0; B=0;Cin=1; #3 A= 0; B=1;Cin=0; #3 A= 0; B=1;Cin=1; #3 A= 1; B=0;Cin=0; #3 A= 1; B=0;Cin=1; # #3 A= 1; B=1;Cin=0; #3 A= 1; B=1;Cin=1; #3 $finish; end endmodule

Working directory: E:\ARA_Synapticad\ Executable file: C:\SynaptiCAD\bin\vlogcmd.exe Highest level modules: FA Compile Complete . R Running... i C1> . A = 0 B = 0 Cin = 0 Sum = 0 Carry = 0 A = 0 B = 0 Cin = 1 Sum = 1 Carry = 0 A = 0 B = 1 Cin = 0 Sum = 1 Carry = 0 A = 0 B = 1 Cin = 1 Sum = 0 Carry = 1 A = 1 B = 0 Cin = 0 Sum = 1 Carry = 0 A = 1 B = 0 Cin = 1 Sum = 0 Carry = 1 A = 1 B = 1 Cin = 0 Sum = 0 Carry = 1 A = 1 B = 1 Cin = 1 Sum = 1 Carry y=1 Exiting VeriLogger Command Line at simulation time 24000 0 Errors, 0 Warnings Compile time = 0.00300, Load time = 0.00000, Execution time = 0.06300 Normal exit Process exited with code 0.

Circuit1_with delay:

Module D (out , a, b, c); output out; input a,b,c; wire d; and #(5) a1 (d,a,b) ; // d @ T = 5 or #(4) O1 (out ,d,c); // out @ T = 4 endmodule d d l

Circuit #1 with delay

// Description of circuit module circuit_bln (A,B,C,x,y); input A,B,C; output x,y; wire e; and #(30) g1(e,A,B); or #(20) g3 (x, e, y); not #(10) g2 (y (y,C); C); endmodule

// stimulus for simple circuit module stimcrct; reg A,B,C; wire x,y; circuit_bln cwd( A, B, C, x, y); initial b i begin A = 1'b0; B = 1'b0; C = 1'b0; #100 A = 1'b1; 1 b1; B = 1'b1; 1 b1; C=1'b1 C=1 b1 ; #100 $finish; end endmodule

Note: observe Glitch in output X

Circuit #2 with delay

module gate_delay gate delay (Y,A); (Y A); output Y; input A; not #(10) n1 (Y,A); endmodule d l test_bench; t t b h module reg A; gate_delay gd (Y, A); initial begin A = 1'b0; #10 A = 1 1'b1; b1; #3 A = 1'b0; #3 A = 1'b1; #3 A = 1'b0; #15 A = 1'b1; #15 A = 1'b0; #20 $finish; end endmodule

Data Flow Modeling

Continuous Assignements Syntax:
assign #delay <id> = <expr>;

Where h to write i them: h

inside a module outside t id procedures d (i iti l and (initial d always l block) bl k)

Properties of these statements are:

Execute in parallel Order independent Continuously active

module fa1(s,cout,a,b,cin); input a,b,cin; output s,cout; assign s=a^b^cin; assign cout cout= a&b | b&cin | cin&a ; endmodule
module FA_dataflow (a,b,cin,sum,cout); input a,b,cin; output sum,cout; wire T1,T2,T3,T4; assign T1=a^b; assign sum=T1^cin; assign T2=a&b; assign T3=b&cin; assign T4=cin&a; assign cout=T2|T3|T4; endmodule

Behavioral Modeling
Can be b expressed di in two types of f procedures/blocks: d /bl k initial they execute only once always they execute for ever (until simulation finishes) Modules can contain any number of procedures Procedures can p Execute in parallel Order independent It can miss events if procedure evaluation is not complete l for f previous i event and d it i gets another h event.

Procedural Statements
Procedural statements i.e., statements inside a procedure Execute sequentially q y Order dependent Continuously not active e.g. 2-to-1 mux implementation: b i begin if (sel == 0) Execution Y = B; Flow else Y = A; ; end

Procedural assignments

Initial Initial Blocks

Start execution at sim time zero and finish when their last statement executes
module nothing; initial $display(Im first); initial begin #50; $display(Really?); end d endmodule

Will be displayed at sim time 0

Will be displayed at sim time 50

Always Always Blocks

Start execution at sim time zero and continue until sim finishes

Events
@
always @(signal1 or signal2 or ..) begin .. execution ti triggers ti every end time any signal changes

always @(posedge clk) begin .. end

execution triggers every time clk changes from 0 to 1 execution i triggers i every time clk changes from 1 to 0

always @(negedge clk) begin .. end

Examples
B Behavioral h i l implementation i l i of f half h lf adder dd module half_adder(S, C, A, B); output S S, C; input A, B; reg S,C; wire A, B; always @(A or B) begin S = A ^ B; C = A & B; end endmodule

Behavioral implementation p of full adder module fab(s,cout,a,b,cin); i input a,b,cin; b i output s,cout; reg s,cout; s cout; always @(a or b or cin) #1 {s,cout}=a+b+cin; { , } ; endmodule

 Behavioral edge-triggered DFF implementation module dff(Q dff(Q, D D, Clk); output Q; input p D, , Clk; ; reg Q; wire D, Clk; always @(posedge Clk) Q = D; endmodule

e.g. Level L l triggered ti d DFF ?

Behavioral Timing
Blocking assignments: Sequential Block

d initial begin g #5 c = 1; #5 b = 0; #5 d = c; end c b 0 5 10 15

Time Each assignment g is blocked by its previous one

Blocking assignments: Parallel Block

initial fork #5 c = 1; #5 b = 0; #5 d = c; join

//gets updated value

d c b

Assignments are parallel blocked here

10

15

Time

Order of execution is controlled by delay. Order Od i is important i t t only l if no delay d l clause l is i used d or execution ti is i at t same time.

Non-blocking assignments:

Let, posedge of CLK at T=0 Let next posedge of CLK at T=9 Let,

always @ (posedge CLK) begin c <= #5 1; b <= #5 0; d < <= #5 c; end

Assignments are not blocked here

initial begin/fork #5 c <= 1; #5 b <= 0; #5 d <= c; end/join

But they are are, here!

Thank You! ?????