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Lecture 2 Branch, Call and Delay Loops, AVR I/O port programming
Review on Lecture-1
Three parts of a computer : CPU, Memory and I/O Instruction execution Types of memory ROM : PROM, EPROM, EEPROM, Flash ROMm Mask ROM RAM : SRAM, NVRAM, DRAM Microcontroller versus Microprocessor Application of microcontrollers Embedded Systems & their design challenges AVR microcontroller AVR family overview
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Decrement Counter
Is Counter Zero?
PC
+1
15
OPCODE(pt1)
10 9
3 2
OPCODE(pt2)
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BRNE AGAIN has the machine code of F7E9. Its binary equivalent is 1111011111101001 The mnemonics is from 15-9 & 2-0, i.e., 111101001 and the operand is the binary underlined, i.e., 1111101. It gives -3. Since previous PC=5, so new PC=+5+1-3=3 and the address of label AGAIN is 3
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Unconditional Jump
The unconditional jump is a jump in which control is transferred unconditionally to the target location In AVR there are three unconditional branches
JMP (jump) RJMP (relative jump) IJMP (Indirect jump)
1 0 0 1 0 1 0 k21
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Calling a subroutine from another subroutine which is called from the main program
Write a program to count up from 0x00 to 0xFF and send the count to PORTB. Use one subroutine for sending the data to PORTB and another one for time delay
MAIN LDI COUNT, 0 BACK: CALL DISPLAY RJMP BACK .ORG 0x300 DELAY: LDI R20, 0XFF AGAIN: NOP NOP DEC R20 BRNE AGAIN RET
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DISPLAY SUB DISPLAY: INC COUNT OUT PORTB, COUNT CALL DELAY RET
DELAY SUB
Calling a subroutine from another subroutine which is called from the main program (contd.)
The address of the instruction CALL DISPLAY is 0x0007 and that after CALL DELAY is 0x000C So, the SP will move as shown in the following figure
Before CALL DISPLAY After CALL DISPLAY After CALL DELAY
SP
0C 00 07 00 07 00
SP SP
07 00
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Pipelining
In early microprocessor such as 8085, the CPU could either fetch or execute at a given time In other words, the CPU had to fetch an instruction from memory, then execute it and then fetch the next instruction, execute it and so on The idea of pipelining in its simplest form is to allow the CPU to fetch and execute at the same time (an instruction fetches while the previous instruction executes) The diagram in the next slide demonstrate the situation
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Pipelining (continued)
Non pipeline fetch 1
T1
exec 1
T2
fetch 2
T3
exec 2
T4
fetch 3
T5
exec 3
T6
fetch 1
Pipeline
exec 5
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Branch penalty
The simultaneous operation of execute and fetch is maintained by a process called queuing In some circumstances, CPU must flush out the queue For example, when a branch instruction is executed the CPU starts to fetch from a new memory location and the code in the queue that was fetched previously is discarded In this case, the execution unit must wait until fetch unit fetches the new instruction This is called a branch penalty It happens in case of JMP, CALL, RET and all conditional branch instruction
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Therefore, we have a time delay of [1+((1+1+1+2)X255)+4] x 0.1 uS = 128 uS Notice that BRNE takes two instruction cycles if it jumps back and takes only one machine cycle when falling through the loop. That means the above number should be 127.9 uS.
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 32 29 28 27 26 25 24 23 22 21
PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3) PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF AGND AVCC PC7 (TOSC0) PC6 (TOSC1) PC5 (TDI) PC4 (TD0) PC3 (TMS) PC2 (TCK) PC1 (SDA) PC0 (SCL) PD7 (OC2)
ATmega
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Px7
Px6
Px5
Px4
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Px3
Px2
Px1
Px0
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In the above program 0s is send to DDRC, so Port C becomes an input port and 1s to DDRB, so Port B becomes output port
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VCC PORTx.n 1=Close 0=Open pin n of Port x Outside Inside of of AVR AVR LDI R16, 0xFF OUT PORTC, R16 LDI R16, 0x00 OUT DDRC, R16
PINx.n
States of a Port
DDRx PORTx 0
Out 0
Out 1
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Instructions SBI ioReg, bit CBI ioReg, bit SBIC ioReg, bit SBIS ioReg, bit
Functions Set bit in I/O register Clear bit in I/O register Skip if bit in I/O register Cleared Skip if bit in I/O register Set
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I/O Registers
Tables below shows the lower 32 I/O registers
Address Mem 20 21 22 23 24 25 26 27 28 29 2A I/O 00 01 02 03 04 05 06 07 08 09 0A Name TWBR TWSR TWAR TWDR ADCL ADCH ADCSRA ADMUX ACSR UBRRL UCSRB Address Mem 2B 2C 2D 2E 2F 30 31 32 33 34 35 I/O 0B 0C 0D 0E 0F 10 11 12 13 14 15 Address Name UCSRA UDR SPCR SPSR SPDR PIND DDRD PORTD PINC DDRC PORTC
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Mem 36 37 38 39 3A 3B 3C 3D 3E 3F
I/O 16 17 18 19 1A 1B 1C 1D 1E 1F
Name PINB DDRB PORTB PINA DDRA PORTA EECR EEDR EEARL EEARH
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Port Bit D0 D1 D2 D3 D4 D5 D6 D7
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These single-bit instructions are widely used for I/O operations. They allow you to monitor a single pin and make a decision depending on whether it is 0 or 1 Note that SBIC and SBIS can be used for any of the lower 32 I/O registers including I/O Ports A, B, C, D and so on
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End of Lecture 2
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