Einstein College of Engineering Velocity Control Adaptive Control Digital Logic Control Micro Processors Control.

Control loop basics

A familiar example of a control loop is the action taken when adjusting hot and cold faucet valves to maintain the faucet water at the desired temperature. This typically involves the mixing of two process streams, the hot and cold water. The person touches the water to sense or measure its temperature. Based on this feedback they perform a control action to adjust the hot and cold water valves until the process temperature stabilizes at the desired value. Sensing water temperature is analogous to taking a measurement of the process value or process variable (PV). The desired temperature is called the setpoint (SP). The input to the process (the water valve position) is called the manipulated variable (MV). The difference between the temperature measurement and the setpoint is the error (e) and quantifies whether the water is too hot or too cold and by how much. After measuring the temperature (PV), and then calculating the error, the controller decides when to change the tap position (MV) and by how much. When the controller first turns the valve on, it may turn the hot valve only slightly if warm water is desired, or it may open the valve all the way if very hot water is desired. This is an example of a simple proportional control. In the event that hot water does not arrive quickly, the controller may try to speed-up the process by opening up the hot water valve more-and-more as time goes by. This is an example of an integral control. Making a change that is too large when the error is small is equivalent to a high gain controller and will lead to overshoot. If the controller were to repeatedly make changes that were too large and repeatedly overshoot the target, the output would oscillate around the setpoint in either a constant, growing, or decaying sinusoid. If the oscillations increase with time then the system is unstable, whereas if they decrease the system is stable. If the oscillations remain at a constant magnitude the system is marginally stable. In the interest of achieving a gradual convergence at the desired temperature (SP), the controller may wish to damp the anticipated future oscillations. So in order to compensate for this effect, the controller may elect to temper their adjustments. This can be thought of as a derivative control method. If a controller starts from a stable state at zero error (PV = SP), then further changes by the controller will be in response to changes in other measured or unmeasured inputs to the process that impact on the process, and hence on the PV. Variables that impact on the process other than the MV are known as disturbances. Generally controllers are used to reject disturbances and/or implement setpoint changes. Changes in feedwater temperature constitute a disturbance to the faucet temperature control process. In theory, a controller can be used to control any process which has a measurable output (PV), a known ideal value for that output (SP) and an input to the process (MV) that will affect the relevant PV. Controllers are used in industry to regulate temperature, pressure, flow rate, chemical composition, speed and practically every other variable for which a measurement exists.

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Proportional control

The fly-ball governor is a classic example of proportional control. A proportional control system is a type of linear feedback control system. Two classic mechanical examples are the toilet bowl float proportioning valve and the fly-ball governor. The proportional control system is more complex than an on-off control system like a bi-metallic domestic thermostat, but simpler than a proportional-integral-derivative (PID) control system used in something like an automobile cruise control. On-off control will work where the overall system has a relatively long response time, but will result in instability if the system being controlled has a rapid response time. Proportional control overcomes this by modulating the output to the controlling device, such as a continuously variable valve. An analogy to on-off control is driving a car by applying either full power or no power and varying the duty cycle, to control speed. The power would be on until the target speed is reached, and then the power would be removed, so the car reduces speed. When the speed falls below the target, with a certain hysteresis, full power would again be applied. It can be seen that this looks like pulse-width modulation, but would obviously result in poor control and large variations in speed. The more powerful the engine, the greater the instability; the heavier the car, the greater the stability. Stability may be expressed as correlating to the power-to-weight ratio of the vehicle. Proportional control is how most drivers control the speed of a car. If the car is at target speed and the speed increases slightly, the power is reduced slightly, or in proportion to the error (the actual versus target speed), so that the car reduces speed gradually and reaches the target point with very little, if any, "overshoot", so the result is much smoother control than on-off control. Further refinements like PID control would help compensate for additional variables like hills, where the amount of power needed for a given speed change would vary, which would be accounted for by the integral function of the PID control.

Proportional Control Theory

In the proportional control algorithm, the controller output is proportional to the error signal, which is the difference between the set point and the process variable. In other words, the output of a proportional controller is the multiplication product of the error signal and the proportional gain. This can be mathematically expressed as

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where

Pout: Output of the proportional controller Kp: Proportional gain e(t): Instantaneous process error at time t. e(t) = SP PV SP: Set point PV: Process variable

PID controller

A proportionalintegralderivative controller (PID controller) is a generic control loop feedback mechanism (controller) widely used in industrial control systems a PID is the most commonly used feedback controller. A PID controller calculates an "error" value as the difference between a measured process variable and a desired setpoint. The controller attempts to minimize the error by adjusting the process control inputs. The PID controller calculation (algorithm) involves three separate parameters, and is accordingly sometimes called three-term control: the proportional, the integral and derivative values, denoted P, I, and D. Heuristically, these values can be interpreted in terms of time: P depends on the present error, I on the accumulation of past errors, and D is a prediction of future errors, based on current rate of change.[1] The weighted sum of these three actions is used to adjust the process via a control element such as the position of a control valve or the power supply of a heating element. In the absence of knowledge of the underlying process, a PID controller is the best controller. [2] By tuning the three constants in the PID controller algorithm, the controller can provide control action designed for specific process requirements. The response of the controller can be described in terms of the responsiveness of the controller to an error, the degree to which the controller overshoots the setpoint and the degree of system oscillation. Note that the use of the PID algorithm for control does not guarantee optimal control of the system or system stability. Some applications may require using only one or two modes to provide the appropriate system control. This is achieved by setting the gain of undesired control outputs to zero. A PID controller will be called a PI, PD, P or I controller in the absence of the respective control actions. PI controllers are fairly common, since derivative action is sensitive to measurement noise, whereas the absence of an integral value may prevent the system from reaching its target value due to the control action.

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PID controller theory

The PID control scheme is named after its three correcting terms, whose sum constitutes the manipulated variable (MV). Hence:

Where Pout, Iout, and Dout are the contributions to the output from the PID controller from each of the three terms, as defined below.

The proportional term (sometimes called gain) makes a change to the output that is proportional to the current error value. The proportional response can be adjusted by multiplying the error by a constant Kp, called the proportional gain. The proportional term is given by:

where Pout: Proportional term of output Kp: Proportional gain, a tuning parameter SP: Setpoint, the desired value PV: Process value (or process variable), the measured value e: Error = SP PV t: Time or instantaneous time (the present) A high proportional gain results in a large change in the output for a given change in the error. If the proportional gain is too high, the system can become unstable (see the section on loop tuning). In contrast, a small gain results in a small output response to a large input error, and a less responsive (or sensitive) controller. If the proportional gain is too low, the control action may be too small when responding to system disturbances.
Droop

A pure proportional controller will not always settle at its target value, but may retain a steady-state error. Specifically, the process gain - drift in the absence of control, such as cooling of a furnace

Einstein College of Engineering towards room temperature, biases a pure proportional controller. If the process gain is down, as in cooling, then the bias will be below the set point, hence the term "droop". Droop is proportional to process gain and inversely proportional to proportional gain. Specifically the steady-state error is given by: e = G / Kp Droop is an inherent defect of purely proportional control. Droop may be mitigated by adding a compensating bias term (setting the setpoint above the true desired value), or corrected by adding an integration term (in a PI or PID controller), which effectively computes a bias adaptively. Despite droop, both tuning theory and industrial practice indicate that it is the proportional term that should contribute the bulk of the output change.
Integral term

The contribution from the integral term (sometimes called reset) is proportional to both the magnitude of the error and the duration of the error. Summing the instantaneous error over time (integrating the error) gives the accumulated offset that should have been corrected previously. The accumulated error is then multiplied by the integral gain and added to the controller output. The magnitude of the contribution of the integral term to the overall control action is determined by the integral gain, Ki. The integral term is given by:

where Iout: Integral term of output Ki: Integral gain, a tuning parameter SP: Setpoint, the desired value PV: Process value (or process variable), the measured value

Einstein College of Engineering e: Error = SP PV t: Time or instantaneous time (the present) : a dummy integration variable The integral term (when added to the proportional term) accelerates the movement of the process towards setpoint and eliminates the residual steady-state error that occurs with a proportional only controller. However, since the integral term is responding to accumulated errors from the past, it can cause the present value to overshoot the setpoint value (cross over the setpoint and then create a deviation in the other direction). For further notes regarding integral gain tuning and controller stability, see the section on loop tuning.
Derivative term

The rate of change of the process error is calculated by determining the slope of the error over time (i.e., its first derivative with respect to time) and multiplying this rate of change by the derivative gain Kd. The magnitude of the contribution of the derivative term (sometimes called rate) to the overall control action is termed the derivative gain, Kd. The derivative term is given by:

where Dout: Derivative term of output Kd: Derivative gain, a tuning parameter SP: Setpoint, the desired value PV: Process value (or process variable), the measured value e: Error = SP PV t: Time or instantaneous time (the present) The derivative term slows the rate of change of the controller output and this effect is most noticeable close to the controller setpoint. Hence, derivative control is used to reduce the magnitude of the overshoot produced by the integral component and improve the combined controller-process stability. However, differentiation of a signal amplifies noise and thus this term in the controller is

Einstein College of Engineering highly sensitive to noise in the error term, and can cause a process to become unstable if the noise and the derivative gain are sufficiently large. Hence an approximation to a differentiator with a limited bandwidth is more commonly used. Such a circuit is known as a Phase-Lead compensator.
Summary

The proportional, integral, and derivative terms are summed to calculate the output of the PID controller. Defining u(t) as the controller output, the final form of the PID algorithm is:

where the tuning parameters are: Proportional gain, Kp Larger values typically mean faster response since the larger the error, the larger the proportional term compensation. An excessively large proportional gain will lead to process instability and oscillation. Integral gain, Ki Larger values imply steady state errors are eliminated more quickly. The trade-off is larger overshoot: any negative error integrated during transient response must be integrated away by positive error before reaching steady state. Derivative gain, Kd Larger values decrease overshoot, but slow down transient response and may lead to instability due to signal noise amplification in the differentiation of the error.

Motion control
Motion control is a sub-field of automation, in which the position and/or velocity of machines are controlled using some type of device such as a hydraulic pump, linear actuator, or an electric motor, generally a servo. Motion control is an important part of robotics and CNC machine tools, however it is more complex than in the use of specialized machines, where the kinematics are usually simpler. The latter is often called General Motion Control (GMC). Motion control is widely used in the packaging, printing, textile, semiconductor production, and assembly industries. The basic architecture of a motion control system contains:

A motion controller to generate set points (the desired output or motion profile) and close a position and/or velocity feedback loop. A drive or amplifier to transform the control signal from the motion controller into a higher power electrical current or voltage that is presented to the actuator. Newer "intelligent" drives can close the position and velocity loops internally, resulting in much more accurate control. An actuator such as a hydraulic pump, air cylinder, linear actuator, or electric motor for output motion. One or more feedback sensors such as optical encoders, resolvers or Hall effect devices to return the position and/or velocity of the actuator to the motion controller in order to close the position and/or velocity control loops. Mechanical components to transform the motion of the actuator into the desired motion, including: gears, shafting, ball screw, belts, linkages, and linear and rotational bearings.

Einstein College of Engineering The interface between the motion controller and drives it controls is very critical when coordinated motion is required, as it must provide tight synchronization. Historically the only open interface was an analog signal, until open interfaces were developed that satisfied the requirements of coordinated motion control, the first being SERCOS in 1991 which is now enhanced to SERCOS III. Later interfaces capable of motion control include Profinet IRT, Ethernet Powerlink, and EtherCAT. Common control functions include:

Velocity control. Position (point-to-point) control: There are several methods for computing a motion trajectory. These are often based on the velocity profiles of a move such as a triangular profile, trapezoidal profile, or an S-curve profile. Pressure or Force control. Trans-mutational vector mapping. Electronic gearing (or cam profiling): The position of a slave axis is mathematically linked to the position of a master axis. A good example of this would be in a system where two rotating drums turn at a given ratio to each other. A more advanced case of electronic gearing is electronic camming. With electronic camming, a slave axis follows a profile that is a function of the master position. This profile need not be salted, but it must be an animated function.

Adaptive control
Adaptive control involves modifying the control law used by a controller to cope with the fact that the parameters of the system being controlled are slowly time-varying or uncertain. For example, as an aircraft flies, its mass will slowly decrease as a result of fuel consumption; we need a control law that adapts itself to such changing conditions. Adaptive control is different from robust control in the sense that it does not need a priori information about the bounds on these uncertain or time-varying parameters; robust control guarantees that if the changes are within given bounds the control law need not be changed, while adaptive control is precisely concerned with control law changes.

Classification of adaptive control techniques

In general one should distinguish between: 1. Feedforward Adaptive Control 2. Feedback Adaptive Control

Applications
When designing adaptive control systems, special consideration is necessary of convergence and robustness issues. Typical applications of adaptive control are (in general):

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Self-tuning of subsequently fixed linear controllers during the implementation phase for one operating point; Self-tuning of subsequently fixed robust controllers during the implementation phase for whole range of operating points; Self-tuning of fixed controllers on request if the process behaviour changes due to ageing, drift, wear etc.; Adaptive control of linear controllers for nonlinear or time-varying processes; Adaptive control or self-tuning control of nonlinear controllers for nonlinear processes; Adaptive control or self-tuning control of multivariable controllers for multivariable processes (MIMO systems);

Usually these methods adapt the controllers to both the process statics and dynamics. In special cases the adaptation can be limited to the static behavior alone, leading to adaptive control based on characteristic curves for the steady-states or to extremum value control, optimizing the steady state. Hence, there are several ways to apply adaptive control algorithms.

BOOLEAN VARIABLES & TRUTH TABLES BOOLEAN ALGEBRA DIFFERS IN A MAJOR WAY FROM ORDINARY ALGEBRA IN THAT BOOLEAN CONSTANTS AND VARIABLES ARE ALLOWED TO HAVE ONLY TWO POSSIBLE VALUES, 0 OR 1. BOOLEAN 0 AND 1 DO NOT REPRESENT ACTUAL NUMBERS BUT INSTEAD REPRESENT THE STATE OF A VOLTAGE VARIABLE, OR WHAT IS CALLED ITS LOGIC LEVEL. SOME COMMON REPRESENTATION OF 0 AND 1 IS SHOWN IN THE FOLLOWING DIAGRAM. IN BOOLEAN ALGEBRA, THERE ARE THREE BASIC LOGIC OPERATIONS: AND ,OR, AND NOT. THESE LOGIC GATES ARE DIGITAL CIRCUITS CONSTRUCTED FROM DIODES, TRANSISTORS, AND RESISTORS CONNECTED IN SUCH A WAY THAT THE CIRCUIT OUTPUT IS THE RESULT OF A BASIC LOGIC OPERATION (OR, AND, NOT) PERFORMED ON THE INPUTS. TRUTH TABLE A TRUTH TABLE IS A MEANS FOR DESCRIBING HOW A LOGIC CIRCUIT'S OUTPUT DEPENDS ON THE LOGIC LEVELS PRESENT AT THE CIRCUIT'S INPUTS. IN THE FOLLOWING TWO-INPUT LOGIC CIRCUIT, THE TABLE LISTS ALL POSSIBLE COMBINATIONS OF LOGIC LEVELS PRESENT AT INPUTS A AND B ALONG WITH THE CORRESPONDING OUTPUT LEVEL X.

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WHEN EITHER INPUT A OR B IS 1, THE OUTPUT X IS 1. THEREFORE THE "?" IN THE BOX IS AN OR GATE.

OR OPERATION THE EXPRESSION X = A + B READS AS "X EQUALS A OR B". THE + SIGN STANDS FOR THE OR OPERATION, NOT FOR ORDINARY ADDITION. THE OR OPERATION PRODUCES A RESULT OF 1 WHEN ANY OF THE INPUT VARIABLE IS 1. THE OR OPERATION PRODUCES A RESULT OF 0 ONLY WHEN ALL THE INPUT VARIABLES ARE 0.

An example of three input OR gate and its truth table is as follows:

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With the OR operation, 1 + 1 = 1, 1+ 1 + 1 = 1 and so on. AND Operation The expression X = A * B reads as "X equals A AND B". The multiplication sign stands for the AND operation, same for ordinary multiplication of 1s and 0s.The AND operation produces a result of 1 occurs only for the single case when all of the input variables are 1.The output is 0 for any case where one or more inputs are 0

An example of three input AND gate and its truth table is as follows:

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With the AND operation, 1*1 = 1, 1*1*1 = 1 and so on. NOT Operation The NOT operation is unlike the OR and AND operations in that it can be performed on a single input variable. For example, if the variable A is subjected to the NOT operation, the result x can be expressed as x = A' where the prime (') represents the NOT operation. This expression is read as: x equals NOT A x equals the inverse of A x equals the complement of A Each of these is in common usage and all indicate that the logic value of x = A' is o pposite to the logic value of A. The truth table of the NOT operation is as follows:

1'=0 0' = 1

because because NOT 0 is 1

NOT

is

The NOT operation is also referred to as inversion or complementation, and these terms are used interchangeably. NOR Operation

Einstein College of Engineering NOR and NAND gates are used extensively in digital circuitry. These gates combine the basic operations AND, OR and NOT, which make it relatively easy to describe then using Boolean algebra. NOR gate symbol is the same as the OR gate symbol except that it has a small circle on the output. This small circle represents the inversion operation. Therefore the output expression of the two input NOR gate is: X = (A + B)'

An example of three inputs OR gate can be constructed by a NOR gate plus a NOT gate:

NAND Operation NAND gate symbol is the same as the AND gate symbol except that it has a small circle on the output. This small circle represents the inversion operation. Therefore the output expression of the two input NAND gate is: X = (AB)'

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Describing Logic Circuits Algebraically Any logic circuit, no matter how complex, may be completely described using the Boolean operations, because the OR gate, AND gate, and NOT circuit are the basic building blocks of digital systems. This is an example of the circuit using Boolean expression:

If an expression contains both AND and OR operations, the AND operations are performed first (X=AB+C: AB is performed first), unless there are parentheses in the expression, in which case the operation inside the parentheses is to be performed first (X= (A+B) +C: A+B is performed first). Circuits containing Inverters Whenever an INVERTER is present in a logic-circuit diagram, its output expression is simply equal to the input expression with a prime (') over it.

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Evaluating Logic Circuit Outputs Once the Boolean expression for a circuit output has been obtained, the output logic level can be determined for any set of input levels. These are two examples of the evaluating logic circuit output: Let A=0, B=1, C=1, D=1 X = A'BC (A+D)' = 0'*1*1* (0+1)' = 1 *1*1* (1)' = 1 *1*1* 0 =0

Let A=0, B=0, C=1, D=1, E=1 X = [D+ ((A+B)C)'] * E = [1 + ((0+0)1 )'] * 1 = [1 + (0*1)'] * 1 = [1+ 0'] *1 = [1+ 1 ] * 1 =1

In general, the following rules must always be followed when evaluating a Boolean expression: 1. First, perform all inversions of single terms; that is, 0 = 1 or 1 = 0. 2. Then perform all operations within parentheses. 3. Perform an AND operation before an OR operation unless parentheses indicate otherwise. 4. If an expression has a bar over it, perform the operations of the expression first and then invert the result. Determining Output Level from a Diagram The output logic level for given input levels can also be determined directly from the circuit diagram without using the Boolean expression.

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Implementing Circuits from Boolean Expression If the operation of a circuit is defined by a Boolean expression, a logic-circuit diagram can he implemented directly from that expression. Suppose that we wanted to construct a circuit whose output is y = AC+BC' + A'BC. This Boolean expression contains three terms (AC, BC', A'BC), which are ORed together. This tells us that a three-input OR gate is required with inputs that are equal to AC, BC', and A'BC, respectively. Each OR-gate input is an AND product term, which means that an AND gate with appropriate inputs can be used to generate each of these terms. Note the use of INVERTERs to produce the A' and C' terms required in the expression.

Boolean Theorems

Einstein College of Engineering Investigating the various Boolean theorems (rules) can help us to simplify logic expressions and logic circuits.

Multivariable Theorems The theorems presented below involve more than one variable: (9) (10) (11) (12) (13a) (13b) (14) (15) x + y = y + x (commutative law) x * y = y * x (commutative law) x+ (y+z) = (x+y) +z = x+y+z (associative law) x (yz) = (xy) z = xyz (associative law) x (y+z) = xy + xz (w+x)(y+z) = wy + xy + wz + xz x + xy = x [proof see below] x + x'y = x + y

Proof of (14) x + xy = x (1+y) = x * 1 [using theorem (6)] = x [using theorem (2)]

DeMorgan's Theorem

Einstein College of Engineering DeMorgan's theorems are extremely useful in simplifying expressions in which a product or sum of variables is inverted. The two theorems are: (16) (x+y)' = x' * y' Theorem (16) says that when the OR sum of two variables is inverted, this is the same as inverting each variable individually and then ANDing these inverted variables.

(17) (x*y)' = x' + y' Theorem (17) says that when the AND product of two variables is inverted, this is the same as inverting each variable individually and then ORing them.

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Example X = [(A'+C) * (B+D')]' = (A'+C)' + (B+D')' [by theorem (17)] = (A''*C') + (B'+D'') [by theorem (16)] = AC' + B'D

Three Variables DeMorgan's Theorem (18) (x+y+z)' = x' * y' * z' (19) (xyz)' = x' + y' + z'

Universality of NAND & NOR Gates It is possible to implement any logic expression using only NAND gates and no other type of gate. This is because NAND gates, in the proper combination, can be used to perform each of the Boolean operations OR, AND, and INVERT.

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In a similar manner, it can be shown that NOR gates can be arranged to implement any of the Boolean operations.

Alternate Logic Gate Representations The left side of the illustration shows the standard symbol for each logic gate, and the right side shows the alternate symbol. The alternate symbol for each gate is obtained from the standard symbol by doing the following: 1. Invert each input and output of the standard symbol. This is done by adding bubbles (small circles) on input and output lines that do not have bubbles, and by removing bubbles that are already there. 2. Change the operation symbol from AND to OR, or from OR to AND. (In the special case of the INVERTER, the operation symbol is not changed.)

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Several points should be stressed regarding the logic symbol equivalences: 1. The equivalences are valid for gates with any number of inputs. 2. None of the standard symbols have bubbles on their inputs, and all the alternate symbols do. 3. The standard and alternate symbols for each gate represent the same physical circuit: there is no difference in the circuits represented by the two symbols. 4. NAND and NOR gates are inverting gates, and so both the standard and alternate symbols for each will have a bubble on either the input or the output. AND and OR gates are noninverting gates, and so the alternate symbols for each will have bubbles on both inputs and output. Concept of Active Logic Levels: When an input or output line on a logic circuit symbol has no bubble on it, that line is said to be active-HIGH. When an input or output line does have a bubble on it, that line is said to be active-LOW. The presence or absence of a bubble, then, determines the active-HIGH/activeLOW status of a circuit's inputs and output, and is used to interpret the circuit operation.

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Boolean Function A Boolean function is an algebraic expression consists of binary variables, the constants 0 & 1, and the Boolean operators.For a set of given values of the variables, the function is evaluated to either 0 or 1 e.g. f = x y + x z The Boolean function f has 3 binaryvariables x, y and z The function is 1 if x and y are both 1 or if x is 1 and z is 0. Otherwise, f = 0 Operator Precedence The operator precedence is: 1. Parentheses 2. NOT 3. AND 4. OR e.g. f = x y + x z Precedence: z, x y, x z, x y + x z e.g. f = (a +b) (c+d) Precedence: a+b, d, c+d, (a +b) (c+d) The parentheses precedence is the same as in normal algebra Boolean Function Truth Table Boolean function can be represented by truth table as well.If the function has n variables, its truth table will have 2n rows e.g. f = x y + x z f has 3 variables so 23 combinations

Einstein College of Engineering f is 1 when the expression is evaluated to 1 otherwise it is 0.

Minterm In a Boolean function, a binary variable (x) may appear either in its normal form (x) or in its complement form (x).Consider 2 binary variables x and y and an AND operation, there are 4 and only 4 possible combinations: xy, xy, xy & xy Each of the 4 product terms is called a MINTERM or STANDARD PRODUCT By definition, a Minterm is a product which consists of all the variables in the normal form or the complement form but NOT BOTH. e.g. for a function with 2 variables x and y: xy is a minterm but x is NOT a minterm e.g. for a function with 3 variables x, y andz: xyz is a minterm but xy is NOT a minterm Maxterm Consider 2 binary variables x and y and an OR operation, there are 4 and only 4 possible combinations: x+y, x+y, x+y, x+y.Each of the 4 sum terms is called a MAXTERM or STANDARD SUM.By definition, a Maxterm is a sum in which each variable appears once and only once either in its normal form or its complement form but NOT BOTH. Minterms and Maxterms for 3 Variables

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Minterm Boolean Expression Boolean functions can be expressed with minterms, e.g.f1(x,y,z) = m1 + m4 + m6 = m(1, 4, 6) f2(x,y,z) = m2 + m4 + m6+ m7 = m(2, 4, 6, 7)

Maxterm Boolean Expression Boolean functions can also be expressed with maxterms, e.g.f1 = xyz+xyz+xyz+xyz+xyz f1 = (xyz+xyz+xyz+xyz+xyz) = (x+y+z)(x+y+z)(x+y+z)(x+y+z)(x+y+z) = M0M2M3M5M7 = M(0, 2, 3, 5, 7) f2 = M0M1M3M5 = M(0, 1, 3, 5)

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Literal A Literal is a variable in a product or sum term xy is a 2-literal product term xyz has 3 literals x + xy + xyz is an expression of sum of products with 3 product terms.The 3 product terms have 1, 2 and 3 literals respectively x(x+y)(x+y+z) is an expression of product of sums.The 3 sum terms have 1, 2 and 3 literals Express Boolean Functions in Minterms If product terms in a Boolean function are not minterms, they can be converted to minterms e.g. f(a,b,c) = a + bc + abc Function f has 3 variables, therefore, each minterm must have 3 literals Neither a nor bc are minterms.They can be converted to minterm.abc is a minterm Conversion to Minterms e.g. f(a,b,c) = a + bc + abc To convert a to a minterm, the 2 variables (b, c) must be added, without changing its functionality .Since a=a1 & 1 = b+b, a= a(b + b) = ab + ab Similarly, ab = ab(c + c) = abc + abc and ab = ab(c+c) = abc + abc bc = bc(a+a) = abc + abc f = abc+abc+abc+abc+abc+abc+abc Express Boolean Functions in Maxterms By using the Distribution Law: x+yz = (x+y)(x+z), a Boolean function can be converted to an expression in product of maxterms e.g. f(a,b,c) = a+bc = (a+b)(a+c) {not maxterms} = (a+b+cc)(a+c+bb) {cc=0} = (a+b+c)(a+b+c)(a+c+b)(a+c+b) = (a+b+c)(a+b+c)(a+c+b) Boolean Function Manipulation

Einstein College of Engineering Boolean functions can be manipulated with Boolean algebra.Manipulation can transform logic expressions, but still keep the same logic functionality.Manipulation can reduce the complexity, hence, easier to be implemented in hardware, i.e. fewer logic gates Boolean Function Manipulation Example f = xy + xyz + xz = x(y + yz) + xz {common factor} = x[(y+y)(y+z)] + xz {Distribution law} = x(y+z) + xz {y + y = 1} = xy + xz + xz {Distribution law} = xy + (x + x)z {common factor} = xy + z {x + x = 1} Simplify f1=abc+ab+abc and f2=(a+b)(a+b) to the minimum literals f1 = abc+ab+abc = ab(c+c) + ab = ab + ab = (a+a)b = b f2 =(a+b)(a+b) = ab(a+b) {DeMorgan} = aba+abb = ab + ab = ab QUINE-McCLUSKEY MINIMIZATION Quine-McCluskey minimization method uses the same theorem to produce the solution as the K-map method, namely X(Y+Y')=X Minimization Technique

The expression is represented in the canonical SOP form if not already in that form. The function is converted into numeric notation. The numbers are converted into binary form. The minterms are arranged in a column divided into groups. Begin with the minimization procedure. Each minterm of one group is compared with each minterm in the group immediately below. Each time a number is found in one group which is the same as a number in the group below except for one digit, the numbers pair is ticked and a new composite is created. This composite number has the same number of digits as the numbers in the pair except the digit different which is replaced by an "x". The above procedure is repeated on the second column to generate a third column. The next step is to identify the essential prime implicants, which can be done using a prime implicant chart. Where a prime implicant covers a minterm, the intersection of the corresponding row and column is marked with a cross. Those columns with only one cross identify the essential prime implicants. -> These prime implicants must be in the final answer. The single crosses on a column are circled and all the crosses on the same row are also circled, indicating that these crosses are covered by the prime implicants selected. Once one cross on a column is circled, all the crosses on that column can be circled since the minterm is now covered. If any non-essential prime implicant has all its crosses circled, the prime implicant is redundant and need not be considered further.

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Next, a selection must be made from the remaining nonessential prime implicants, by considering how the non-circled crosses can be covered best. One generally would take those prime implicants which cover the greatest number of crosses on their row. If all the crosses in one row also occur on another row which includes further crosses, then the latter is said to dominate the former and can be selected. The dominated prime implicant can then be deleted.

Example Find the minimal sum of products for the Boolean expression, f= (1,2,3,7,8,9,10,11,14,15), using Quine-McCluskey method.

Firstly these minterms are represented in the binary form as shown in the table below. The above binary representations are grouped into a number of sections in terms of the number of 1's as shown in the table below. Binary representation of minterms Minterms 1 2 3 7 8 9 10 11 14 15 U 0 0 0 0 1 1 1 1 1 1 V 0 0 0 1 0 0 0 0 1 1 W 0 1 1 1 0 0 1 1 1 1 X 1 0 1 1 0 1 0 1 0 1

Group of minterms for different number of 1's No of 1's 1 1 1 2 2 2 3 3 3 Minterms 1 2 8 3 9 10 7 11 14 U 0 0 1 0 1 1 0 1 1 V 0 0 0 0 0 0 1 0 1 W 0 1 0 1 0 1 1 1 1 X 1 0 0 1 1 0 1 1 0

Einstein College of Engineering 4 15 1 1 1 1

Any two numbers in these groups which differ from each other by only one variable can be chosen and combined, to get 2-cell combination, as shown in the table below. 2-Cell combinations Combinations (1,3) (1,9) (2,3) (2,10) (8,9) (8,10) (3,7) (3,11) (9,11) (10,11) (10,14) (7,15) (11,15) (14,15) U 0 0 1 1 0 1 1 1 1 1 V 0 0 0 0 0 0 0 0 0 1 1 W 0 1 1 0 1 1 1 1 1 1 1 X 1 1 0 0 1 1 1 0 1 1 -

From the 2-cell combinations, one variable and dash in the same position can be combined to form 4-cell combinations as shown in the figure below. Combinations (1,3,9,11) (2,3,10,11) (8,9,10,11) (3,7,11,15) (10,11,14,15) U 1 1 V 0 0 0 W 1 1 1 X 1 1 -

The cells (1,3) and (9,11) form the same 4-cell combination as the cells (1,9) and (3,11). The order in which the cells are placed in a combination does not have any effect. Thus the (1,3,9,11) combination could be written as (1,9,3,11). From above 4-cell combination table, the prime implicants table can be plotted as shown in table below. Prime Implicants Table Prime 1 2 3 7 8 9 10 11 14 15

Einstein College of Engineering Implicants (1,3,9,11) (2,3,10,11) (8,9,10,11) (3,7,11,15) -

X X

X X

X X -

X X

X X -

X X X -

X X X X -

X X

X -

The columns having only one cross mark correspond to essential prime implicants. A yellow cross is used against every essential prime implicant. The prime implicants sum gives the function in its minimal SOP form. Y = V'X + V'W + UV' + WX + UW Logic Combinational logic blocks have the outputs depending on the combinations of the current inputs. Sequential logic blocks have the outputs depending on the current inputs as well as any previous inputs. Binary Adder Binary Adder is for binary number addition Logic Circuit to be discussed: Half Adder Full Adder Ripple Adder Carry Look Ahead Adder Half Adder o o o o Half adder is for addition of 2 single bits It has two 1-bit inputs and two 1-bit outputs The inputs are the 2 bits to be added (a, b) The outputs are 1-bit sum (s) & 1-bit carry (c)

The logic is:

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Binary Addition The half adder adds 2 single-bit inputs It cannot complete a full addition

To complete a full addition, the adder needs to take in 3 inputs: a, b and the carry from the previous bit. Full Adder To carry the addition, an adder with 3 inputs is required. A Full Adder takes in 3 inputs (a, b and ci) and produces 2 outputs (s, co) a & b are the 2 bits to be added, ci is the carry input (carry over from the previous bit) and co is the carry output (to the next bit)

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Logic for Full Adder Logic equations derived from the truth table:

s = a b ci co = ab + bci + aci Full Adder The below implementation shows implementing the full adder with AND-OR gates, instead of using XOR gates. The basis of the circuit below is from the above Kmap. Circuit-SUM

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Circuit-CARRY

Full adder can be built from 2 half adders s = a b ci co = ab+bci+aci = ab+(abci+abci)+(abci+abci) = ab + abci + ci (ab+ab) = ab + ci (a b)

n-bit Ripple Adder To perform an addition of 2 n-bit numbers An-1A1A0 & Bn-1B1B0, where An-1 & Bn-1 are theMSB & A0B0 are the LSB, we need a n-bit adder,which can be built from n fulladders

Einstein College of Engineering Ripple Adder: Carry ripples through the chain

Carry-Look-Ahead Adder The delay generated by an N-bit adder is proportional to the length N of the two numbers X and Y that are added because the carry signals have to propagate from one full-adder to the next. For large values of N, the delay becomes unacceptably large so that a special solution needs to be adopted to accelerate the calculation of the carry bits. This solution involves a "look-ahead carry generator" which is a block that simultaneously calculates all the carry bits involved. Once these bits are available to the rest of the circuit, each individual three-bit addition (Xi+Yi+carry-ini) is implemented by a simple 3-input XOR gate. The design of the look-ahead carry generator involves two Boolean functions named Generate and Propagate. For each input bits pair these functions are defined as: Gi = Xi . Yi Pi = Xi + Yi The carry bit c-out(i) generated when adding two bits Xi and Yi is '1' if the corresponding function Gi is '1' or if the c-out(i-1)='1' and the function Pi = '1' simultaneously. In the first case, the carry bit is activated by the local conditions (the values of Xi and Yi). In the second, the carry bit is received from the less significant elementary addition and is propagated further to the more significant elementary addition. Therefore, the carry_out bit corresponding to a pair of bits Xi and Yi is calculated according to the equation: carry_out(i) = Gi + Pi.carry_in(i-1) For a four-bit adder the carry-outs are calculated as follows carry_out0 = G0 + P0 . carry_in0 carry_out1 = G1 + P1 . carry_out0 = G1 + P1G0 + P1P0 . carry_in0 carry_out2 = G2 + P2G1 + P2P1G0 + P2P1P0 . carry_in0 carry_out3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1 . carry_in0 The set of equations above are implemented by the circuit below and a complete adder with a look-ahead carry generator is next. The input signals need to propagate through a maximum of 4 logic gate in such an adder as opposed to 8 and 12 logic gates in its counterparts illustrated earlier.

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Pi is called Carry Propagate Gi is called Carry Generate With Pi and Gi, we obtain the sum & carry for the full adder:

Ci+1= Gi + PiCi C1 = G0 + P0C0 C2 = G1 + P1C1 = G1 + P1(G0 + P0C0) = G1 + P1G0 + P1P0C0 C3 = G2 + P2C2 = G2 + P2(G1 + P1G0 + P1P0C0) = G2 + P2G1 + P2P1G0 + P2P1P0C0 Carry no longer depend on its previous stage Look-Ahead Carry Generator

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Speed: 2 gate delays for all carry Cost: more gates

Sums can be calculated from the following equations, where carryout is taken from the carry calculated in the above circuit. sum_out0 = X 0 sum_out1 = X 1 Y0 Y1 carry_out0 carry_out1

Einstein College of Engineering sum_out2 = X 2 sum_out3 = X 3 Y2 Y3 carry_out2 carry_out3

MSI Adder Adders are available in Medium Scale Integration (MSI) devices Both TTL and CMOS are available, e.g. 74183: TTL 1-bit Full Adder 7482: TTL 4-bit Carry-Look-Ahead Adder 4008: CMOS 4-bit Carry-Look-Ahead Adder 74182: 4-bit Look-Ahead Carry Generator 4-bit Addition

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To add 2 4-bit numbers: Z = X + Y

8-bit Addition To add 2 8-bit numbers: Z = X + Y

Subtractor Subtractor circuits take two binary numbers as input and subtract one binary number input from the other binary number input. Similar to adders, it gives out two outputs, difference and borrow (carry-in the case of Adder). There are two types of subtractors.

Half Subtractor Full Subtractor

Half Subtractor

Einstein College of Engineering The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow). The logic symbol and truth table are shown below. Symbol

Truth Table X 0 0 1 1 Y 0 1 0 1 D 0 1 1 0 B 0 1 0 0

From the above table we can draw the Kmap as shown below for "difference" and " borrow". The boolean expression for the difference and Borrow can be written.

From the equation we can draw the half-subtractor as shown in the figure below.

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Full Subtractor A full subtractor is a combinational circuit that performs subtraction involving three bits, namely minuend, subtrahend, and borrow-in. The logic symbol and truth table are shown below. Symbol

Truth Table X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Bin 0 1 0 1 0 1 0 1 D 0 1 1 0 1 0 0 1 Bout 0 1 1 1 0 0 0 1

From above table we can draw the Kmap as shown below for "difference" and "borrow".

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The boolean expression for difference and borrow can be written as D = X'Y'Bin + X'YBin' + XY'Bin' + XYBin = (X'Y' + XY)Bin + (X'Y + XY')Bin' = (X =X Y)'Bin + (X Y Bin Y)Bin'

Bout = X'.Y + X'.Bin + Y.Bin From the equation we can draw the full-subtractor as shown in figure below.

Full-subtractor circuit is more or less same as a full-adder with slight modification.

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Parallel Binary Subtractor Parallel binary subtractor can be implemented by cascading several full-subtractors. Implementation and associated problems are those of a parallel binary adder, seen before in parallel binary adder section. Below is the block level representation of a 4-bit parallel binary subtractor, which subtracts 4-bit Y3Y2Y1Y0 from 4-bit X3X2X1X0. It has 4-bit difference output D3D2D1D0 with borrow output Bout.

A serial subtractor can be obtained by converting the serial adder using the 2's complement system. The subtrahend is stored in the Y register and must be 2's complemented before it is added to the minuend stored in the X register. The circuit for a 4-bit serial subtractor using full-adder is shown in the figure below.

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Comparator Comparator compares binary numbers. Logic comparing 2 bits: a and b

Magnitude Comparator Comparator compares binary numbers 4-bit Magnitude Comparator: Inputs: A3A2A1A0 & B3B2B1B0 Outputs: Y A>B, Y A<B, Y A=B For each bit, let: Si = AiBi + AiBi = (AiBi + AiBi) Si is true when Ai = Bi For A = B, we must have: A3=B3 and A2=B2 and A1=B1 and A0=B0 Hence, Y A=B = S3S2S1S0 136 Logic For A > B For A > B, there are 4 cases: 1. A3B3 is 10 and A2 A1 A0 & B2B1B0 can be anything: A=1xxx, B=0xxx 2. A3=B3 and A2B2 is 10 and A1 A0 & B1B0 can be anything: A=11xx, B=10xx or A=01xx, B=00xx 3. A3=B3 and A2=B2 and A1B1=10 and A0B0 is xx: e.g. A=011x, B=010x 4. A3=B3 and A2=B2 and A1=B1 and A0B0 is 10: e.g.

Einstein College of Engineering A=1011, B=1010 Y A>B=A3B3+S3A2B2+S3S2A1B1+S3S2S1A0B0 Logic For A < B For A < B, there are also 4 cases: 1) A3B3 is 01 and A2A1A0 & B2B1B0 can be anything: 1. A=0xxx, B=1xxx 2) A3=B3 and A2B2 is 01 and A1 A0 & B1B0 can be 1. anything: A=10xx, B=11xx or A=00xx, B=01xx 3) A3=B3 and A2=B2 and A1B1=01 and A0B0 is xx: e.g. 1. A=110x, B=111x 4) A3=B3 and A2=B2 and A1=B1 and A0B0 is 01: e.g. 1. A=1000, B=1001 Y A<B=A3 B3+S3A2 B2+S3S2A1 B1+S3S2S1A0 B0 4-bit Comparator Logic Circuit

MSI: 7485 4-bit Magnitude Comparator

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Comparison of 4-bit Numbers

Comparison of 8 - bit Numbers

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Decoder A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different.Binary Decoder has n inputs and 2noutputs also called as n-to-2n decoder. Inputs have all the 2n combinations and the corresponding output will be activated for each input combinations.Decoding is necessary in applications such as data multiplexing, 7 segment display and memory address decoding. Enable inputs must be on for the decoder to function, otherwise its outputs assume a single "disabled" output code word. Figure below shows the pseudo block of a decoder.

A binary decoder has n inputs and 2 n outputs. Only one output is active at any one time, corresponding to the input value. Figure below shows a representation of Binary n-to-2n decoder

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e.g. 3-to-8 decoder has 3 inputs and 8 outputs

3-to-8 Decoder Function Table

3-to-8 Decoder Logic Circuit

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2-to-4 Decoder with Output Enable

Implement Logic Function with Decoder

Any n-variable logic function, in canonical sum-of-minterms form can be implemented using a single n-to-2n decoder to generate the minterms, and an OR gate to form the sum. The output lines of the decoder corresponding to the minterms of the function are used as inputs to the or gate. Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2n decoder with m OR gates. Suitable when a circuit has many outputs, and each output function is expressed with few minterms.

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(Ex) Full adder using decoder S(x, y, z) = C(x, y, z) = (1,2,4,7) (3,5,6,7)

Truth Table

From the truth table we know the values for 1 1 0 1 which the sum 1 1 1 1 (s) is active and also the carry (c) is active. Thus we have the equation as shown above and a circuit can be drawn as shown below from the equation derived.

X 0 0 0 0 1 1

Y 0 0 1 1 0 0

Z 0 1 0 1 0 1

C 0 0 0 1 0 1

S 0 1 1 0 1 0 0 1

Use a 3-to-8 decoder to implement: f = xyz + xyz + xyz (m1 + m5 + m7)

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MSI Decoders 1. 2-to-4 Decoder 2. 3-to-8 Decoder 3. 4-to-16 Decoder 4. BCD-to-Decimal Decoder 5. BCD-to-Seven-Segment Decoder e.g. Low Power Schottky TTL: 74LS138 3-to-8 Decoder where G1, G2A and G2B are enable pins Logic Symbol

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74LS138 3-to-8 Decoder

Implement Logic Function with74LS138 Use a 3-to-8 decoder to implement: f = xyz + xyz + xyz (m1 + m5 + m7)

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4-to-16 Decoder Use 2 3-to-8 decoders Inputs: D, C, B, A Outputs: Y0 Y15 When D = 0, top decoder is enabled When D = 1,bottom decoderis enabled En is enable

Binary Encoders

Einstein College of Engineering An encoder is a combinational circuit that performs the inverse operation of a decoder. If a device output code has fewer bits than the input code has, the device is usually called an encoder. e.g. 2n-to-n, priority encoders. The simplest encoder is a 2n-to-n binary encoder, where it has only one of 2n inputs = 1 and the output is the n-bit binary number corresponding to the active input. It can be built from OR gates

e.g. 4-to-2 Encoder

Octal-to-Binary Encoder Octal-to-Binary take 8 inputs and provides 3 outputs, thus doing the opposite of what the 3to-8 decoder does. At any one time, only one input line has a value of 1. The figure below shows the truth table of an Octal-to-binary encoder. Truth Table I0 1 0 0 0 0 I1 0 1 0 0 0 I2 0 0 1 0 0 I3 0 0 0 1 0 I4 0 0 0 0 1 I5 0 0 0 0 0 I6 0 0 0 0 0 I7 0 0 0 0 0 Y2 0 0 0 0 1 Y1 0 0 1 1 0 Y0 0 1 0 1 0

Einstein College of Engineering 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 1 1 1 0 1 1 1 0 1

For an 8-to-3 binary encoder with inputs I0-I7 the logic expressions of the outputs Y0-Y2 are: Y0 = I1 + I3 + I5 + I7 Y1= I2 + I3 + I6 + I7 Y2 = I4 + I5 + I6 +I7 Based on the above equations, we can draw the circuit as shown below

Priority Encoder

If more then two inputs are active simultaneously, the output is unpredictable or rather it is not what we expect it to be.This ambiguity is resolved if priority is established so that only one input is encoded, no matter how many inputs are active at a given point of time. The priority encoder includes a priority function. The operation of the priority encoder is such that if two or more inputs are active at the same time, the input having the highest priority will take precedence. e.g. 4-to-2 PriorityEncoder A3 has the highest priority A0 has the lower priority

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74148 8-to-3 Priority Encoder

16-to-4 Priority Encoder Cascade two 74148 8-to-3 priority encoders. The Input 15 has highest priority

Multiplexer A multiplexer (MUX) is a digital switch which connects data from one of n sources to the output. A number of select inputs determine which data source is connected to the output. The block diagram of MUX with n data sources of b bits wide and s bits wide select line is shown in below figure.

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MUX acts like a digitally controlled multi-position switch where the binary code applied to the select inputs controls the input source that will be switched on to the output as shown in the figure below. At any given point of time only one input gets selected and is connected to output, based on the select input signal.

The operation of a multiplexer can be better explained using a mechanical switch as shown in the figure below. This rotary switch can touch any of the inputs, which is connected to the output. As you can see at any given point of time only one input gets transferred to output.

2x1 MUX

A 2 to 1 line multiplexer is shown in figure below, each 2 input lines A to B is applied to one input of an AND gate. Selection lines S are decoded to select a particular AND gate. The truth table for the 2:1 mux is given in the table below.

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Design of a 2:1 Mux To derive the gate level implementation of 2:1 mux we need to have truth table as s hown in figure. And once we have the truth table, we can draw the K-map as shown in figure for all the cases when Y is equal to '1'. Combining the two 1' as shown in figure, we can drive the output y as shown below Y = A.S + B.S Truth Table B 0 0 0 0 1 1 1 Kmap A 0 0 1 1 0 0 1 1 S 0 1 0 1 0 1 0 1 Y 0 0 1 0 0 1 1 1

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MSI MUX 74150: 16-to-1 74153: Dual 4-to-1 74157: Quad 2-to-1 74151: 8-to-1