designfeature

Steve Sandler, Senior Engineer Danny Chow, Engineering Scientist Daniel Fu, Engineering Scientist

AEi Systems, LLC, Los Angeles

Quantifying Harmonic Distortion in Nonisolated Boost PFCs

A detailed analysis of the total harmonic distortion for a nonisolated boost topology with average current-mode control using the UC1854A and the UCC3817.
any continuous-conduction-mode PFC controllers use a nonisolated boost topology with average current-mode control. Examples of such controllers are the UC1852, UC1854/UC1854A/UC1854B family and the UC2817/18. These devices create a reference curVFF rent source, IAC, used as the reference current for the average VFF current-mode control. Fig. 1 shows the schematic of a PFC circuit. The input current is a function of the IAC current as it is applied in the following function within the PFC controller: (Eq. V1) FF
VCC R3 100 D3 IAC RFUSE Vac + C81 1.5 F IN _ R9 2 k PKLIMIT R10 10 k RMOUT 4.02 k C112 1.2 nF C111 270 pF R26 12 k IAC C6 150 nF VSENSE C14 3.3 F R13 100 k RFF 30.1 k CFF 2.2 F R01 383 k Bridge + C13 0.47 F R02 383 k R2 51 D4 L1 D2 RSENSE 0.25 R28 4.02 k PKLIMIT R17 20 U1 controller GND PKLIMIT CAOUT CAI MOUT IAC VAOUT VFF VFF DRV VCC CT SS RT VSENSE ENA VREF C5 1 F REF R14 20 k R5 10 k VSENSE R171 499 k R18 499 k RT 10 k C3 100 F VCC CT 560 pF CSS 0.01 F D1 VOUT Q1 C11 220 F C1 1 F C2 1 F
FBR

VFBR

REF

R291 274 k

R21 249 k

Fig. 1. Simplified PFC schematic with a single controller in which the input current is a function of the IAC reference current source.

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VFF VFF
Where: RT1 X2 1 m (measurement?) VAO = Output of the voltage-sensing KBPC806 R3 Lin 1 M amplifier + D1 VFF = Scaled and filtered version of the unknown + input voltage IN IAC = Current reference. R2 V3 14.5 Ideally, IAC is a scaled replica of the _ Tran generators = SIN FBR 120 VPK rectified input voltage. This ultimately is the waveform that the current signal will R1 follow. V6 100 M RMOUT = Terminating resistance for the + B1 multiplier output current. Voltage RSENSE = Input-current sensing resistor. V(3,4) > 0? VFBR = Forward voltage of the input I(R3): rectifier diodes. -I(R3) VRMS = The AC input voltage. VFF is used to stabilize the voltage-loop Fig. 2. Schematic for the input full-bridge diodes that contribute a THD of 1.54161%. gain against input-voltage variations. Conduction of IAC begins when the AC input voltage A(1) = 1.5831 10-4 exceeds the sum of two bridge-rectifier diodes and the voltA(2) = 0 age at the IAC pin, VIAC. The IAC pin is different for each A(3) = 1.67082 10-6 The Total Figure Harmonic Distortion (THD) for any number of controller, ranging from as low as 0.5 V for the UC1854A/B, 2 AEi Systems VFF VFF VFF harmonics also can be determined. For example, evaluating to a high of 6 V for the original UC1854. This conducVV FF VFF the THD up to the 13th harmonic: tion angle can be determined based on the input voltage FF as assumptions: VFF VFBR = 0.75 V VFF VRMS = 85 VRMS (Eq.6) RIAC = 736 k V PRMS = 250 W DistIAC =V 1.406%. FFFF V VV FBR FBR FF VIAC = 1.4 V. VFBR

THD Due to the Full-Bridge Diodes

FBR FBR

FBR

(Eq.2)

Solving for
FBR

(Eq.3)

Thus, this is the angle at which current just begins flowing through RAC. The instantaneous current is then defined by: (Eq.4)

for angles from to - and from + to 2-. Due to the symmetrical nature of the waveform in both x and y directions, the Fourier coefficients can be evaluated within a single quadrant, using only A coefficients. (Eq.5)

Under this particular operating condition, the THD is VFF 1.4%, based solely on the forward voltage of the input rectiVFBR fier diodes and the voltage at the VIAC pin. Fig. 2 shows the schematic of the input full-bridge diodes. Individual harmonics can be evaluated as well. In Table 1 (page 30), the SPICE Fourier analysis results show that the THD is 1.54%. These results show that the majority of the THD is from the 3rd through the 9th harmonic, A(n) which is generally difficult to filter, % n while the higher order harmonics A(1) are generally filterable. There are no 3 1.05541 even harmonics.
5 7 9 0.63226 0.45057 0.34935

VAO, VFF, RMOUT and RSENSE Contribution to THD

Then, the peak magnitude of any harmonic from the fundamental to infinity can be determined.

In addition to the full-bridge 11 0.28472 diodes, the ripples at the VAO 13 0.23979 and VFF pins of the IC chip also introduce distortion into the system. The ripple at VAO is a function of the error amplifier frequency compensation. The VFF or VRMS ripple is a function of the specific controller. For

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example, the UC2817 uses an internal circuit to create the VFF signal with the addition of only a resistor and a capacitor. The UC1854A requires many additional components. The ripples at VAO and VFF are assumed to be 30 mV and 20 mV, respectively, based on simulation results. For the purposes here, the THD is therefore: VAO = 2.1 V VAO RIPPLE = 0.03 V VFFRIPPLE = 0.02 V K1 = 0.018 RMOUT = 4020 RSENSE = 0.15 The distoration, including the VAO and VF terms, is defined in Eq. 7 (in box). DistIAC = 2.09258%.
R16 100 D7 R15 51 k

Now, the THD due to the full bridge, VAO, VFF, RSENSE and RMOUT is 2.09%.

Maximum Duty-Cycle Limitation to THD

The next source of distortion is a result of the maximum duty cycle of the boost converter. The continuous-conduction transfer function of the boost topology is: (Eq.8) In the boost converter PFC, the output voltage is a constant, while the input voltage changes in accordance with the sinusoidal signal. The minimum input voltage for the controller to regulate occurs at maximum duty cycle. Assuming 97% maximum duty cycle,
C10 1 F C11 1 F High temperature see EVM warnings and restrictions D1 6 A, 600 V VO VO +

VCC

D8

IAC AC2 VLINE 85 to 265 VRMS AC1 F1

R21 R13 383 k 383 k

C14 1.5 F 400 V

C13 0.47 F 600 V D3 6A 600 V R14 0.25 5 W

L1 1 mH D2 8 A, 600 V

High voltage see EVM warnings and restrictions

Q1

VOUT C12 220 F 385 Vdc 450 V GND

UCC3817 R12 2 k R9 4.02 k R10 4.02 k 1 GND 2 PKLIMIT VCC 15 3 CAOUT 4 CAI 5 MOUT R8 12 k D6 (optional) R7 100 k C8 270 pF IAC C9 1.2 nF C7 150 nF C15 3.3 F 6 IAC RT 12 VSENSE 11 7 VAOUT 8 VFF OVP/EN 10 R6 30 k CT 14 SS 13 DRVOUT 16 D4 D5 (optional)

R17 20 VCC C3 1 F CER C2 100 F AI EI C1 560 pF C4 0.01 F R1 12 k VO

High voltage see EVM warnings and restrictions

R11 10 k VREF

R2 R19 499 k 499 k R3 20 k C5 1 F R20 274 k R5 10 k

C6 2.2 F

R4 249 k

VREF 9 VREF

Fig. 3. Schematic for a PFC circuit using the UCC3817 as a controller.

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Fig. 3 AEi Systems

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(Eq.7)

(Eq.11)

(Eq.12)

VOUT = 380 V DMAX = 0.97 VIN = VOUT(1-DMAX) (Eq. 9) VIN = 11.4 V. The minimum input voltage for operation is 11.4 V. Therefore, the conduction angle due to the maximum duty cycle is: (Eq. 10) See Eq. 11 in box.

IOUT = 250/380 A

COUT = 250 uF F = 60 Hz (Eq. 14)

= 0.10752 Now, the total harmonic distortion due to full-bridge diodes, VFF /VAO ripples, RMOUT, RSENSE and maximum duty cycle can be reformulated as shown in Eq. 12 (in box). The final THD for the system is 2.85%.

(Eq. 15) (Eq. 16) C(1) = 0 A(2) = 0.65789 A(1) = 0 B(2) = 0 B(1) = 0 The ripple voltage at the output capacitor, or any harmonic, is shown in Eq. 17.  (Eq. 17) The VAO ripple at twice the line frequency, n=2, is calculated to be:

THD Analysis for SLUU077C (UCC3817)

Referring to Fig. 3, the VAORIPPLE is a function of C7 along with R2 and R19. The pole created by R7 and C7 is approximately 10 Hz, so that the VAORIPPLE equals: R2 = 499 k R19 = 499 k C7 = 0.15 F (Eq. 13) For the output capacitor current:

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Maximum Duty (%) THD (%) 6.799 4.064 2.492 2.132

(Eq. 18)

93 95 97 99

Number of harmonics; 14 THD:1.54161%

Harmonic 0 1 2 3 4 5 6 7 8 9 10 11 12 13 frequency 0 60 120 180 240 300 360 420 480 540 600 660 720 780 Magnitude 2.90541e-009 0 0.000115736 179.802 5.80794e-009 93.6039 1.3533e-006 -2.0727 5.80859e-009 97.207 7.99073e-007 -3.1959 5.80877e-009 100.81 5.63648e-007 -3.9129 5.80895e-009 104.413 4.33166e-007 -4.0928 5.80912e-009 108.016 3.49991e-007 -3.6379 5.80935e-009 111.619 2.92229e-007 -2.4967 Phase 0 179.802 93.6039 -2.0727 97.207 -3.1959 100.81 -3.9129 104.413 -4.0928 108.016 -3.6379 111.619 -2.4967 Normal magnitude 0 1 5.01826e-005 0.0116929 5.01882e-005 0.00690427 5.01898e-005 0.00487011 5.01913e-005 0.00374271 5.01928e-005 0.00302404 5.01948e-005 0.00252496 Normal phase 0 0 -86.198 -181.87 -82.595 -183 -78.992 -183.71 -75.389 -183.89 -71.786 -183.44 -68.183 -182.3

Table 2. For 85 VRMS input and 250-W output power, the relationship between maximum duty cycle and total harmonic distortion as derived from MathCAD calculations.

(Eq. 19) Then, we can solve VAO as a function of operating point (input voltage and output power): DMAX = 0.97 POUT = 250 W K = 115 VAO = 2.2 V F = 60 Hz COUT = 25010-6

Table 1. THD is slightly higher than the MathCAD calculation due to the nonlinear characteristics of the diodes model.
R12 R13 VRECT 383 k 383 k VFF R15 30.1 k C1 R3 2.2 F 100 k VAOUT + + C2 150 nF R4 499 k

IAC VFF

C9 2.2 F

VSENSE VAOUT VSENSE SS SS C4 10 nF GND CAI

VOUT R5 499 k

R6 20 k

C7 = 0.15 F RFF = 30 k CFF = 2.2 F VRMS = 85 V. The nominal THD of the application circuit shown in Fig. 4 is calculated to be 2.49% using the equations derived in this article. The THD result form a SPICE simulation is 2.54%. These results are very close and the differences are primarily due to the nonlinearity of the input rectifier diodes, which is not included in the equations for simplification. DistIAC = 2.49237% Fourier components of transient response IAC DC component = 1.119095E-03. Typically, the range of maximum duty cycle of the UCC3817 is from 93% to 99% according to its data sheet (see Table 2). The maximum duty cycle is the major contributor to the THD. The maximum duty cycle alone can increase the THD by more than 100% when DMAX changes from 97% to 93%.

VCC R161 100 R151 R181 24 k 24 k LSOURCE 25 nH VLINE V1 C8 1.5 F RSOURCE 0.1 m C5 1.2 nF R9 12 k

R2 4.02 k

MOUT +

R8 4.02 k RT VCC + CT R19 10 k VCC C10 20 F

R20 10 k

C15 270 pF

Limiter CAO

C12 1 F

R7 2 k

VOFF = 0 VAMPL = 120 FREQ = 60

R11 10 M

Ref 9 V R18 REF + 10 OVP/EN k PKLIMIT U7 UCC2817 DRVOUT L1 Duty 1 mH U8 VIN VOUT GND D

R14 EN 274 k

VOUT R17 249 k

R22 10 k

U5 In+

KBPC808 In-

BOOST2 RCURRENT SENSOR 0.25 C14 0.47 F COUT 220 F R10 0.2

Out+ Out-

D1 HFA08TB60

R16 0.652

Fig. 4. SLUU077C PFC circuit used for THD simulation exhibits a THD of 2.53871%.

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