TDS Application Notes: Correcting Mistimed I/O Introduction Output vectors from logic simulators usually require some

level of modification before theyre ready for tester programs to use. The EDA world is the unconstrained world of software, where the only limitations are those imposed by the software itself. Device simulations can be run at virtually any rate and resolution. ATEs, however, live in the physical world, where there are real hardware and resource limitations. In order for simulation waveforms to be useable in a functional test program, they must be groomed to take tester requirements and device specifications into account. Lets look at how I/O timing errors can be introduced in simulation runs, and what we can do to correct them. The problem originates in the way I/O information is handled in the two environments. The Problem Many logic simulators simply ignore I/O as a signal entity. But ATEs require I/O information, as they will have the same kind of circuitry connected outside a driver and a receiver (refer to Figure 1). Typically during testing, the part drives for awhile, then goes to high impedance when its enable line goes off. Some time later, the tester talks hence the need for I/O information. This creates more than just noise and could result in a bus contention. When I/O timing is incorrect, it may be that what you should be doing is looking at the part, but are in fact driving it. But often the I/O information were looking for to tell the tester when to talk and when to listen may not be available outside the part. For instance, the kidsn of data that come from a VCD file to describe I/O information will only contain Zero for a time, X for a time, and One for a time there are no directionality data. In that case, we can log the data from an internal node (see Figure 2) and then use the TDS input converter to combine the two signals into one signal in the SEF file that contains both level and direction. The Signal Definition file for our example might contain a clause like the following: DB0 I (R/W 1) 0 (R/W 0) which says that DB0 is an input when R/W is a one and an output when R/W is a zero. But, since the I/O data is from an internal node, propagation delay within the device may cause a lag between the transition on the internal node and the time it affects behavior at the output on DB0 (see Figure 3). The problem is further aggravated on testers that cant make the transition to X except at a cycle boundary. Slightly mistimed I/O can create cycle boundary problems. For example, the testing of DB0 and DB1 shown in Figure 3 will require cycle boundaries at 98ns on DB0 and 100ns on DB1, resulting in cycle boundaries 2ns apart and a Cycle Too Short error. This small difference in timing creates a big problem for the tester, unless we adjust for that timing differential. The Solution The SnapIO Conditioner provides one solution to this problem. It looks at a group of signals and moves I/O transitions to be coincident with level transitions on specified signals. In the example in Figure 3, the SnapIO Conditioner would move the I/O transition on DB0 to 100ns, simultaneous with the level transitions, and eliminate the noise that resulted in the short cycle. Using the signal DB0, the SnapIO command would contain: EarlyTime=0ns LateTime=5ns Priority=Late I/OandLevel=I/O This will allow DB0 to snap to a later time that is within 5ns of its I/O change. Another way to fix this problem uses the Move Conditioner. In this case, instead of combining R/W and DB0 with the input converter, we leave them separate and then modify R/W in the SEF file. For

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example, to move the R/W signal level transition to be coincident with the DB0 I/O transition, the Move Conditioner statement R/W (D:U +2ns) specifies that all R/W transitions from D to U will have their event times increased by 2ns. The CombineIO Conditioner can then be used to combine the two signals into one signal, as the input converter did in the first example.

Figure 3. Mistimed R/W internal signal combined with DB0. I/O change occurs at 98ns (where the data change and the real I/O transition occurs) rather than at 100ns.

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