SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

SCLS094B DECEMBER 1982 REVISED MAY 1997

Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

SN54HC74 . . . J OR W PACKAGE SN74HC74 . . . D, DB, N, OR PW PACKAGE (TOP VIEW)

description
The HC74 contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The SN54HC74 is characterized for operation over the full military temperature range 55C to 125C. The SN74HC74 is characterized for operation from 40C to 85C.

1CLR 1D 1CLK 1PRE 1Q 1Q GND

1 2 3 4 5 6 7

14 13 12 11 10 9 8

VCC 2CLR 2D 2CLK 2PRE 2Q 2Q

SN54HC74 . . . FK PACKAGE (TOP VIEW)

1D 1CLR NC VCC 2CLR 1CLK NC 1PRE NC 1Q

4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13

2D NC 2CLK NC 2PRE

NC No internal connection FUNCTION TABLE INPUTS PRE L H L H H CLR H L L H H CLK X X X D X X X H L OUTPUTS Q H L H H L Q L H H L H

H H L X Q0 Q0 This configuration is unstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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1Q GND NC 2Q 2Q

SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SCLS094B DECEMBER 1982 REVISED MAY 1997

logic symbol
1PRE 1CLK 1D 1CLR 2PRE 2CLK 2D 2CLR 4 3 2 1 10 11 12 13 S C1 1D R 9 8 2Q 6 5 1Q

1Q

2Q

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, N, PW, and W packages.

logic diagram (positive logic)

PRE CLK C C C C Q TG C C D TG TG TG Q C CLR C C

absolute maximum ratings over operating free-air temperature range

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero.

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SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SCLS094B DECEMBER 1982 REVISED MAY 1997

recommended operating conditions

SN54HC74 MIN VCC VIH Supply voltage High-level High l l input i p voltage l g VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO tt TA L Low-level l l input i p voltage l g Input voltage Output voltage Input (rise fall) I p transition ii ( i and df ll) ) time i Operating free-air temperature VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 4.5 V VCC = 6 V 2 1.5 3.15 4.2 0 0 0 0 0 0 0 0 55 0.5 1.35 1.8 VCC VCC 1000 500 400 125 NOM 5 MAX 6 SN74HC74 MIN 2 1.5 3.15 4.2 0 0 0 0 0 0 0 0 40 0.5 1.35 1.8 VCC VCC 1000 500 400 85 C ns V V V V NOM 5 MAX 6 UNIT V

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC 2V IOH = 20 20 A VOH VI = VIH or VIL IOH = 4 mA IOH = 5.2 mA IOL = 20 A VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC Ci VI = VCC or 0 VI = VCC or 0, IO = 0 4.5 V 6V 4.5 V 6V 2V 4.5 V 6V 4.5 V 6V 6V 6V 2 V to 6 V 3 MIN 1.9 4.4 5.9 3.98 5.48 TA = 25C TYP MAX 1.998 4.499 5.999 4.3 5.8 0.002 0.001 0.001 0.17 0.15 0.1 0.1 0.1 0.1 0.26 0.26 100 4 10 SN54HC74 MIN 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1000 80 10 MAX SN74HC74 MIN 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1000 40 10 nA A pF V V MAX UNIT

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SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SCLS094B DECEMBER 1982 REVISED MAY 1997

timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC 2V fclock Clock y Cl k frequency f q 4.5 V 6V 2V PRE or CLR l low tw P l duration Pulse d i CLK high low high or l 4.5 V 6V 2V 4.5 V 6V 2V Data D tsu S i b f Setup time before CLK PRE or CLR i inactive i 4.5 V 6V 2V 4.5 V 6V 2V th Hold data after H ld time, i d f CLK 4.5 V 6V TA = 25C MIN MAX 0 0 0 100 20 17 80 16 14 100 20 17 25 5 4 0 0 0 6 31 36 SN54HC74 MIN 0 0 0 150 30 25 120 24 20 150 30 25 40 8 7 0 0 0 MAX 4.2 21 25 SN74HC74 MIN 0 0 0 125 25 21 100 20 17 125 25 21 30 6 5 0 0 0 ns ns ns MAX 5 25 29 MHz MH UNIT

switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V fmax 4.5 V 6V 2V PRE or CLR tpd CLK Q or Q Q or Q 4.5 V 6V 2V 4.5 V 6V 2V tt Q or Q 4.5 V 6V TA = 25C MIN TYP MAX 6 31 36 10 50 60 70 20 15 70 20 15 28 8 6 230 46 39 175 35 30 75 15 13 SN54HC74 MIN 4.2 21 25 345 69 59 250 50 42 110 22 19 MAX SN74HC74 MIN 5 25 29 290 58 49 220 44 37 95 19 16 ns ns MH MHz MAX UNIT

operating characteristics, TA = 25C

PARAMETER Cpd Power dissipation capacitance per flip-flop TEST CONDITIONS No load TYP 35 UNIT pF

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SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SCLS094B DECEMBER 1982 REVISED MAY 1997

PARAMETER MEASUREMENT INFORMATION

From Output Under Test Test Point CL = 50 pF (see Note A) Low-Level Pulse 50% High-Level Pulse VCC 50% tw VCC 50% 0V VOLTAGE WAVEFORMS PULSE DURATIONS VCC 0V tsu Data Input 50% 10% 90% th 90% VCC 50% 10% 0 V tf Out-of-Phase Output In-Phase Output tPLH 50% 10% tPHL 90% 50% 10% tf 90% tr tPLH 50% 10% 90% tr tPHL 90% VOH 50% 10% VOL tf VOH VOL VCC 50% 50% 0V 50% 0V

LOAD CIRCUIT

Reference Input

50%

Input

tr

VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES

VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

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Copyright 1996, Texas Instruments Incorporated