INSTITUTO DE ELETRNICA DE POTNCIA

Departamento de Engenharia Eltrica Centro Tecnolgico UNIVERSIDADE FEDERAL DE SANTA CATARINA

Interruptores MOSFET, IGBTs e MCTs Principais caractersticas para o comando

Textos extrados de livros, de relatrios internos do INEP e de notas de aplicaes da IR e da Motorola: O transistor IGBT aplicado em eletrnica de Potncia - BASCOP, Ren Pastor Torrico; PERIN, Arnaldo Jos; Editora Sagra Luzzatto, Porto Alegre RS, 1997.

AN-937 (v.Int)

Gate Drive Characteristics and Requirements for HEXFETs

Topics covered: Gate drive vs base drive Enhancement vs Depletion N vs P-Channel Max gate voltage Zener diodes on gate? The most important factor in gate drive: the impedance of the gate drive circuit Switching 101 or Understanding the waveforms What happens if gate drive impedance is high? dv/dt induced turn-on Can a TTL gate drive a standard HEXFET ? The universal buffer Power dissipation of the gate drive circuit is seldom a problem Can a C-MOS gate drive a standard HEXFET ? Driving HEXFET s from linear circuits Drive circuits not referenced to ground Gate drivers with optocouplers Gate drive supply developed from the drain of the power device Gate drivers with pulse transformers Gate drivers with choppers Drive requirements of Logic Level HEXFET s How fast is a Logic Level HEXFET driven by a logic circuit? Simple and inexpensive isolated gate drive supplies A well-kept secret: Photovoltaic generators as gate drivers Driving in the MHz? Use resonant gate drivers Related topics (Note: Most of the gate drive considerations and circuits are equally applicable to IGBTs. Only MOSFETs are mentioned for the sake of simplicity. Special considerations for IGBTs are contained in INT-990)

1. GATE DRIVE VS BASE DRIVE

The conventional bipolar transistor is a current-driven device. As illustrated in Figure 1(a). a current must be applied between the base and emitter terminals to produce a flow of current in the collector. The amount of a drive required to produce a given output depends upon the gain, but invariably a current must be made to flow into the base terminal to produce a flow of current in the collector.
CURRENT IN BASE PRODUCES CURRENT IN COLLECTOR IC IB VOLTAGE AT GATE
+ + +

PRODUCES CURRENT IN DRAIN

ID

CURRENT SOURCE (a) Bipolar Transistor

VOLTAGE SOURCE (b) HEXFET

Figure 1. Bipolar Transistor is Current Driven, HEXFET is Voltage Driven

The HEXFETis fundamentally different: it is a voltage-controlled power MOSFET device. A voltage must be applied between the gate and source terminals to produce a flow of current in the drain (see Figure 1b). The gate is isolated electrically from the source by a layer of silicon dioxide. Theoretically, therefore, no current flows into the gate when a DC voltage is applied to it though in practice there will be an extremely small current, in the order of nanoamperes. With no voltage applied between the gate and source electrodes, the impedance between the drain and source terminals is very high, and only the leakage current flows in the drain.

AN-936 (v.Int)

The Do's and Don'ts of Using MOS-Gated Transistors

(HEXFET is the trademark for International Rectifier Power MOSFETs) In this application note, some of the most common do's and don'ts of using power HEXFETs are described. The objective is to help the user get the most out of these remarkable devices, while reducing "on the job" learning time to a minimum. Topics Covered: Be Mindful of the Reverse Blocking Characteristics of the Device Be Careful When Handling and Testing Power HEXFET s Beware of Unexpected Gate-to-Source Voltage Spikes Beware of Drain or Collector Voltage Spikes Induced by Switching Do Not Exceed the Peak Current Rating Stay within the Thermal Limits of the Device Pay Attention to Circuit Layout Be Careful When Using the Integral Body-Drain Diode Be On Your Gaurd When Comparing Current Ratings

1. BE MINDFUL OF THE REVERSE BLOCKING CHARACTERISTICS OF THE DEVICE

IGBTs have a limited reverse blocking capability of approximately 20-30 V, with high leakage. This is characterized in IRs data sheets with a Reverse Avalanche Energy (EARV). This rating is useful to absorb energy spikes due to the stray inductance in series with the anti-parallel diode. This is a significant advantage over bipolar transistors and power darlingtons. A feature of power MOSFETs is that they inherently have built into them an integral reverse body-drain diode. The existence of this diode is explained by reference to Figure 1. When the source terminal is made positive with respect to the drain, current can flow through the middle of the source cell, across a forward biased P-N junction. In the "reverse" direction, the power HEXFET thus behaves like a P-N junction rectifier. The integral body-drain diode is a real circuit element, and its current handling capability is typically as high as that of the transistor itself. Some circuits require an "inverse" rectifier to be connected across the switching device, and in these circuits it will often be possible to utilize the body-drain diode of the HEXFET provided the proper precautions are taken. Figure 1. Basic HEXFET Structure

2. BE CAREFUL WHEN HANDLING & TESTING POWER HEXFETS

The user's first "contact" with a MOS-gated transistor could be a package of parts arriving on his desk. Even at this stage, it behooves one to be knowledgeable about some elementary precautions. Being MOS devices, HEXFETs can be damaged by static charge when handling, testing or installing into a circuit. Power Devices have large input capacitance, and are able to absorb static charge without excessive buildup of voltage. In order to avoid possible problems, however, the following procedures should be followed as a matter of good practice, wherever possible: MOS-gated transistors should be left in their anti-static shipping bags, or conductive foam, or they should be placed in metal containers or conductive tote bins, until required for testing or connection into a circuit. The person handling the device should ideally be grounded through a suitable wrist strap, though in reality this added precaution is seldom essential. Devices should be handled by the package, not by the leads. When checking the electrical characteristics of the MOS-gated transistors on a curve tracer, or in a test circuit, the following precautions should be observed: Test stations should use electrically conductive floor and table mats that are grounded. Suitable mats are available commercially.

AN-936 (v.Int) When inserting the device in a curve tracer or a test circuit, voltage should not be applied until all terminals are solidly connected into the circuit. When using a curve tracer, a resistor should be connected in series with the gate to damp spurious oscillations that can otherwise occur on the trace. A suitable value of resistance is 100 ohms. For repeated testing, it is convenient to build this resistor into the test fixture. When switching from one test range to another, voltage and current settings should be reduced to zero, to avoid the generation of potentially destructive voltage surges during switching.

The next step is to connect the device into an actual circuit. The following simple precautions should be observed: Work stations should use electrically grounded table and floor mats. Soldering irons should be grounded.

Now that the device has been connected into its circuit, it is ready for the power to be applied. From here on, success in applying the device becomes a matter of the integrity of the circuit design, and of what circuit precautions have been taken to guard against unintentional abuse of its ratings. The following are the interrelated device and circuit considerations that lead to reliable, trouble-free design.

3. BEWARE OF UNEXPECTED GATE-TO-SOURCE VOLTAGE SPIKES

Excessive voltage will punch through the gate-source oxide layer and result in permanent damage. This seems obvious enough, but it is not so obvious that transient gate-to-source overvoltages can be generated that are quite unrelated to, and well in excess of, the amplitude of the applied drive signal. The problem is illustrated by reference to Figure 2. If we assume that the impedance, Z, of the drive source is high, then any positive-going change of voltage applied across the drain and source terminals (caused, for example, by the switching of another device in the circuit) will be reflected as a positivegoing voltage transient across the source and the drain terminals, in the approximate ratio of: 1 C gs C dg

1+

The above ratio is typically about 1 to 6. This means that a change of drain-to-source voltage of 300V, for example, could produce a voltage transient approaching 50V between the gate and source terminals. In practice this aiming voltage will not appear on the gate if the dv/dt is positive because the MOS-gated device goes in conduction at approximately Vgs = 4V, thereby clamping the dv/dt at the expense of a current transient and increased power dissipation. However, a negative-going dv/dt will not be clamped. This calculation is based upon the worst case assumption that the transient impedance of the drive circuit is high by comparison with the gate-to-source capacitance of the device. This situation can, in fact, be quite easily approximated if the gate drive circuit contains inductancefor example the leakage inductance of an isolating drive transformer. This inductance exhibits a high impedance for short transients, and effectively decouples the gate from its drive circuit for the duration of the transient. The negative-going gate-to-source voltage transient produced under the above circumstances may exceed the gate voltage rating of the device, causing permanent damage. It is, of course, true that since the applied drain transient results in a voltage at the gate which tends to turn the device ON, the overall effect is to an extent self-limiting so far as the gate voltage transient is concerned. Whether this self-limiting action will prevent the voltage transient at the gate from exceeding the gate-source voltage rating of the device depends upon the impedance of the external circuit. Spurious turn-on is of itself undesirable, of course, though in practical terms one may grudgingly be able to accept this circuit operating imperfection, provided the safe operating area of the device is not violated. Notice that a voltage clamp (a conventional zener diode is suitable for this purpose) to prevent the gate-source voltage rating from being exceeded will not prevent the dv/dt induced turn-on, as the gate will not reach the zener voltage. In many instances the zener is responsible for generating oscillations in the gate circuit, particularly when a significant amount of stray inductance is present. A more fundamental solution, of course, is to make the impedance of the gate circuit low enough that not only is the gate-source voltage rating not exceeded, but also the voltage transient at the gate is contained to a level at which spurious turn-on does not occur.

AN-936 (v.Int)

"POSITIVE GOING" CHANGE

DRAIN-SOURCE VOLTAGE

"NEGATIVE GOING" CHANGE

DRIVE SOURCE IMPEDANCE Z

CDG

G CDS CGS WITH NO CLAMPING

GATE-SOURCE VOLTAGE S

WITH NO CLAMPING

EXTERNALLY CONNECTED CLAMPING ZENER DIODE

Figure 2. A Rapidly Changing Applied Drain-Source Voltage will Produce Gate-Source Transients

LS +E +E OVERVOLTAGE TRANSIENT DUE TO L R (b) CLAMPED INDUCTIVE LOAD (a) UNCLAMPED INDUCTIVE LOAD L LS D S

R LS OVERVOLTAGE TRANSIENT DUE TO LS E L

VDS

LS = STRAY CIRCUIT INDUCTANCE

Figure 3. Drain-Source Overvoltage Transient when Switching Off with Unclamped Inductive Load

Figure 4. Drain-Source Overvoltage Transient Produced by Stray Circuit Inductance When Switching Off with Clamped, Inductive Load

It should be remembered that a collapse of voltage across the device (i.e., a negative-going dv/dt) will produce a transient negative voltage spike across the gate-source terminals. In this case, of course, there will be no tendency for the device to turn ON, and hence no tendency for the effect to be self-limiting. A zener diode connected to clamp positive transients will automatically clamp negative-going transients, limiting them to the forward conduction voltage drop of the zener.

AN-936 (v.Int)

4. BEWARE OF DRAIN OR COLLECTOR VOLTAGE SPIKES INDUCED BY SWITCHING

The uninitiated designer is often not aware that self-inflicted overvoltage transients can be produced when the device is switched OFF, even though the DC supply voltage for the drain circuit is well below the VDS rating of the transistor. Figure 3 shows how a voltage spike is produced when switching the device OFF, as a result of inductance in the circuit. The faster the device is switched, the higher the overvoltage will be. Inductance is always present to some extent in a practical circuit, and therefore, there is always danger of inducing overvoltage transients when switching OFF. Usually, of course, the main inductive component of the load will be "clamped", as shown in Figure 4. Stray circuit inductance still exists, however, and overvoltage transients will still be produced as a resultto say nothing of the fact that the clamping diode may not provide an instantaneous clamping action, due to its "forward recovery" characteristic. The first approach to this problem is to minimize stray circuit inductance, by means of careful attention to circuit layout, to the point that whatever residual inductance is left in the circuit can be tolerated. HEXFETs have an inductive energy rating that makes capable of withstanding these inductive spikes, assuming that the data sheet limits for energy and temperature are not violated. IGBTs, however, do not have an avalanche rating, and a clamping device should be connected, physically as close as possible to the drain and source terminals, as shown in Figure 5. A conventional zener diode, or a "transorb" clamping device, are satisfactory for this purpose. An alternative clamping circuit is shown in Figure 6, depending on the voltage and current rating of the circuit. The capacitor C is a reservoir capacitor and charges to a substantially constant voltage, while the resistor R is sized to dissipate the "clamping energy" while maintaining the desired voltage across the capacitor. The diode D must be chosen so that its forward recovery characteristic does not significantly spoil the transient clamping action of the circuit. A simple RC snubber can also be used, as shown in Figure 7. Note, however, that an RC snubber not only limits the peak voltage, it also slows down the effective switching speed. In so doing, it absorbs energy during the whole of the switching period, not just at the end of it, as does a voltage clamp. A snubber is therefore less efficient than a true voltage clamping device. Note that the highest voltage transient occurs when switching the highest level of current. The waveform of the voltage across the device should be checked with a high-speed oscilloscope at the full load condition to ensure that switching voltage transients are within safe limits.

5. DO NOT EXCEED THE PEAK CURRENT RATING

All power transistors have a specified maximum peak current rating. This is conservatively set at a level that guarantees reliable operation and it should not be exceeded. It is often overlooked that, in a practical circuit, peak transient currents can be obtained that are well in excess of the expected normal operating current, unless proper precautions are taken. Heating, lighting and motor loads, for example, consume high in-rush currents if not properly controlled. A technique that ensures that the peak current does not exceed the capability of the device is to use a current sensing control that switches it OFF whenever the current instantaneously reaches a preset limit. Unexpectedly high transient current can also be obtained as a result of rectifier reverse recovery, when a transistor is switched ON rapidly into a conducting rectifier. This is illustrated in Figure 8. The solution is to use a faster rectifier, or to slow down the switching of the transistor to limit the peak reverse recovery current of the rectifier.

LS +E

LS

OVERVOLTAGE TRANSIENT CLAMPED BY ZENER

(c) CLAMPED INDUCTIVE LOAD WITH LOCAL D-S ZENER CLAMP

LS D

VDS

CLAMPING ZENER

Figure 5. Overvoltage Transient at Switch-Off Clamped by Local Drain-Source Zener

6. STAY WITHIN THE THERMAL LIMITS

AN-936 (v.Int) Power transistors are thermally limited. They must be mounted on a heatsink that is adequate to keep the junction temperature within the rated under the "worst case" condition of maximum power dissipation and maximum ambient temperature. It must be remembered that in a switching application, the total power is due to the conduction losses and the switching loss. Switching time and switching losses of HEXFETs are essentially independent of temperature, but the conduction losses increase with increasing temperature, because RDS(on) increases with temperature. IGBTs, on the contrary, have switching losses that highly dependent of temperature, while conduction losses are not. This must be taken into account when sizing the heatsink. The required thermal resistance of the heatsink can be calculated as follows: The transistor conduction power, PT, is given approximately by PT = On-state Voltage x Drain or Collector current The switching energy depends upon the voltage and current being switched and the type of load. The total switching loss, PS, is the total switching energy, T, multiplied by the operating frequency, f. eT is the sum of the energies due to the individual switchings that take place in each fundamental operating cycle: PS = T f The total power dissipation is the sum of the conduction power, PT, and the switching power, PS. P = PT + PS
LS

+E

EC E

D 0 C EC R

Figure 6. Overvoltage Transient at Switch-Off Limited by Local Clamp

Since: TJA = PRth where: Rth = junction-to-ambient thermal resistance The junction-to-ambient thermal resistance, RJA, is made up of the internal junction-to-case thermal resistance, RJC, plus the case-toheatsink thermal resistance, RCS, plus the sinkto-ambient thermal resistance, RSA. The first two terms are fixed for the device, and the required thermal resistance of the heatsink, RSA, for a given junction temperature rise DTJ-A, can be calculated from: RS-A = RJ-A - (RJC + RC-S)

+E

OVERVOLTAGE TRANSIENT REDUCED BY SNUBBER R LS

(d) CLAMPED INDUCTIVE LOAD WITH LOCAL D-S SNUBBER VDS SNUBBER

LS D S

Figure 7. Overvoltage Transient at Switch-Off Limited by Local Capacitor-Resistor Snubber

7. PAY ATTENTION TO CIRCUIT LAYOUT

AN-936 (v.Int) Stray inductance in the circuit can cause overvoltage transients, slowing down of the switching speed, unexpected unbalance of current between parallel connected devices, and unwanted oscillations. In order to minimize these effects, stray circuit inductance must be minimized. This is done by keeping conduction paths as short as possible, by minimizing the area of current loops, by using twisted pairs of leads, and by using ground plane construction. Local decoupling capacitors alleviate the affects of any residual circuit inductance, once these measures have been taken. Circuit layout should be kept as symmetrical as possible in order to maintain balanced currents in parallel connected HEXFETs or IGBTs. The gates of parallel connected devices should be decoupled by small ferrite beads placed over the gate connections, or by individual resistors in series with each gate. These measures prevent parasitic oscillations.

8. BE CAREFUL WHEN USING THE INTEGRAL BODY-DRAIN DIODE

The HEXFET's integral body-drain diode exhibits minority carrier reverse recovery. Reverse recovery presents a potential problem when switching any rectifier off; the slower the rectifier, the greater the problem. By comparison with the HEXFET itself, the switching speed of the integral reverse rectifier is quite slow. The switching speed of a circuit which utilizes the body-drain diode of the HEXFET may therefore be limited by the rectifier. Whether this will be so depends upon the circuit and the operating conditions.
I

Regardless of the overall circuit configuration, or the particular application, the "local" circuit operating situation that is troublesome occurs when the freewheeling current from an inductive load is commutated from the integral rectifier of one HEXFET to the transistor of an "opposite" HEXFET, the two devices forming a tandem series connected pair across a low impedance voltage source, as shown in Figure 8. This local circuit configuration occurs in most chopper and inverter schemes. If the incoming HEXFET switches ON too rapidly, the peak reverse recovery current of the integral body-drain diode of the opposite HEXFET will rise too rapidly, the peak reverse recovery current rating will be exceeded, and the device may possibly be destroyed.

IF: INDUCTIVE LOAD CURRENT IS FREE-WHEELING IN THE BODY-DRAIN DIODE OF THIS DEVICE THEN: TAKE CARE WHEN SWITCHING-ON THIS DEVICE

Figure 8. Local Circuit Configuration and Operating Condition Requiring Special Care When Using the HEXFET's Integral Body-Drain Diode.

The peak reverse recovery current of the rectifier can be reduced by slowing down the rate of change of current during the commutation process. The rate of change of current can be controlled by purposefully slowing down the rate of rise of the gate driving pulse. Using this technique, the peak current can be reduced to almost any desired extent, at the expense of prolonging the high dissipation switching period. The oscillograms in Figure 9 illustrate the effect. By slowing the total switch-ON time from 300ns to 1.8ms, the peak current of the IRF330 has been decreased from 20A to 10A. The energy dissipation associated with the unrestrained switch-ON in Figure 9(a) is 0.9mJ, whereas it is 2.7mJ for the controlled switch-ON of Figure 9(b). Note also that it is not necessary to slow the switching-OFF of the HEXFET, hence the energy dissipation at switch-OFF will be relatively small by comparison with that at switch-ON. For operation at frequencies up to a few kHz, where ultra-fast switching is not mandatory, slowing the applied gate drive signal to reduce the peak reverse recovery current of the "opposite" rectifier offers a good practical solution.

AN-936 (v.Int)

9. BE ON YOUR GUARD WHEN COMPARING CURRENT RATINGS

The user can be forgiven if he assumes that the continuous drain current rating, that appears on the data sheet represents the current at which the device can actually be operated continuously in a practical system. To be sure, that's what it should represent; unfortunately it often does not. Frequently a "continuous" current rating is assigned to the device which in practical terms cannot be used, because the resulting conduction power dissipation would be so large as to require a heatsink with an impractically low thermal resistance, and/or an impractically low ambient operating temperature. The best advice to the user is to compare different types on the basis of high temperature conduction and switching losses, and not of current rating. For MOSFETS, it is sufficient to compare RDS(on) at 25 C, and this provides a common basis for comparison. This parameter, taken in conjunction with the junction-case thermal resistance, is a much better indication of the power MOSFET true current handling capability.

100V

10mV
(a) I(max) = 20A, di/dt = 50A/ms. Switching time = 300nsec.

2S

10mV
(b) I(max) = 20A, di/dt = 50A/s. Switching time = 1.8 ms..

2S

Figure 9. Oscillograms of IRF330 Switching into Reverse Rectifier of Another IRF330 with Freewheeling Current of 4A. Top Trace: Voltage 100V/div. Bottom Trace: Current 4A/div. Time Scale: 2ms/div.

AN-937 (v.Int) When a voltage is applied between the gate and source terminals, an electric field is set up within the HEXFET. This field inverts the channel (Figure 2) from P to N, so that a current can flow from drain to source in an uninterrupted sequence of N-type silicon (drain-channel-source). Field-effect transistors can be of two types: enhancement mode and depletion mode. Enhancement-mode devices need a gate voltage of the same sign as the drain voltage in order to pass current. Depletion-mode devices are naturally on and are turned off by a gate voltage of the same polarity as the drain voltage. All HEXFETs are enhancementmode devices.

SOURCE METALLIZATION

SILICON GATE CHANNEL

INSULATING OXIDE

N SOURCE

GATE OXIDE

TRANSISTOR TRANSISTOR DRAIN DRAIN All MOSFET voltages are referenced to the source CURRENT CURRENT terminal. An N-Channel device, like an NPN transistor, has a drain voltage that is positive with respect to the source. Being enhancement-mode DIODE CURRENT devices, they will be turned on by a positive voltage Figure 2. Basic HEXFET Structure on the gate. The opposite is true for P-Channel devices, that are similar to PNP transistors. Although it is common knowledge that HEXFETtransistors are more easily driven than bipolars, a few basic considerations have to be kept in mind in order to avoid a loss in performance or outright device failure.

2. GATE VOLTAGE LIMITATIONS

Figure 2 shows the basic HEXFETstructure. The silicon oxide layer between the gate and the source regions can be punctured by exceeding its dielectric strength. The data sheet rating for the gate-to-source voltage is between 10 and 30 V for most HEXFETs. Care should be exercised not to exceed the gate-to-source maximum voltage rating. Even if the applied gate voltage is kept below the maximum rated gate voltage, the stray inductance of the gate connection, coupled with the gate capacitance, may generate ringing voltages that could lead to the destruction of the oxide layer. Overvoltages can also be coupled through the drain-gate self-capacitance due to transients in the drain circuit. A gate drive circuit with very low impedance insures that the gate voltage is not exceeded in normal operation. This is explained in more detail in the next section. Zeners are frequently used to protect the gate from transients. Unfortunately they also contribute to oscillations and have been known to cause device failures. A transient can get to the gate from the drive side or from the drain side. In either case, it would be an indication of a more fundamental problem: a high impedance drive circuit. A zener would compound this problem, rather than solving it. Sometimes a zener is added to reduce the ringing generated by the leakage of a gate drive transformer, in combination with the input capacitance of the MOSFET. If this is necessary, it is advisable to insert a small series resistor (5-10 Ohms) between the zener and the gate, to prevent oscillations.

3. THE IMPEDANCE OF THE GATE CIRCUIT

To turn on a power MOSFET a certain charge has to be supplied to the gate to raise it to the desired voltage, whether in the linear region, or in the saturation (fully enhanced) region. The best way to achieve this is by means of a voltage source, capable of supplying any amount of current in the shortest possible time. If the device is operated as a switch, a large transient current capability of the drive circuit reduces the time spent in the linear region, thereby reducing the switching losses. On the other hand, if the device is operated in the linear mode, a large current from the gate drive circuit minimizes the relevance of the Miller effect, improving the bandwidth of the stage and reducing the harmonic distortion. This can be better understood by analyzing the basic switching waveforms at turn-on and turn-off for a clamped inductive load, as shown in Figures

AN-937 (v.Int) 3 and 5. Figure 3 shows the waveforms of the drain current, drain-to-source voltage and gate voltage during the turn-on interval. For the sake of simplicity, the equivalent impedance of the drive circuit has been assumed as purely resistive.
DRAIN-SOURCE VOLTAGE
LOAD

DRAIN-SOURCE I
STRAY INDUCTANCE DRIVE CIRCUIT RESISTANCE G

SE UL EP V I R "D UIT C R CI EN "OP

VTH t 0 t1 t2 t3 t4

GATE-SOURCE VOLTAGE

"OPEN CIRCUIT" DRIVE PULSE

SOURCE INDUCTANCE

Figure 3. Waveforms at Turn-On

VOLTAGE DROP ACROSS THIS L MEANS THAT THE DRAIN VOLTAGE FALL RESULTING IN DISCHARGE OF THIS CAPACITOR RESULTING IN MORE CURRENT THROUGH THIS RESISTANCE

DRAIN-SOURCE VOLTAGE ID CURRENT

DRIVE

+ IS
THIS INDUCED VOLTAGE SUBSTRACTS FROM THE DRIVE VOLTAGE RESULTING IN

G-S VOLTAGE "OPEN CIRCUIT" DRIVE PULSE t0 t1 t2 t4 GATE VOLTAGE GIVING I VTH t3

RESULTING IN THIS VOLTAGE RISING MORE SLOWLY RESULTING IN SLOW RISE OF IS

Figure 4. Diagrammatic Representation of Effects When Switching-ON

Figure 5. Waveforms at Turn-OFF

At time, t0, the drive pulse starts to rise. At t0 it reaches the threshold voltage of the HEXFETs and the drain current starts to increase. At this point, two things happen which make the gate-source voltage waveform deviate from its original path. First, inductance in series with the source which is common to the gate circuit (common source inductance) develops an induced voltage as a result of the increasing source current. This voltage counteracts the applied gate drive voltage, and slows down the rate of rise of voltage appearing directly across the gate and source terminals; this in turn slows down the rate of rise of the source current. This is a negative feedback effect: increasing current in the source produces a counteractive voltage at the gate, which tends to resist the change of current. The second factor that influences the gate-source voltage is the so called Miller effect. During the period t1 to t2 some voltage is dropped across unclamped stray circuit inductance in series with the drain, and the drain-source voltage starts to fall. The

AN-937 (v.Int) decreasing drain-source voltage is reflected across the drain-gate capacitance, pulling a discharge current through it, and increasing the effective capacitive load on the drive circuit. This in turn increases the voltage drop across the source impedance of the drive circuit, and decreases the rate of rise of voltage appearing between the gate and source terminals. Obviously, the lower the impedance of the gate drive circuit, the less this effect will be. This also is a negative feedback effect; increasing current in the drain results in a fall of drain-to-source voltage, which in turn slows down the rise of gate-source voltage, and tends to resist the increase of drain current. These effects are illustrated diagramatically in Figure 4. This state of affairs continues throughout the period t1 to t2, as the current in the HEXFETrises to the level of the current, IM, already flowing in the freewheeling rectifier, and it continues into the next period, t2 to t3, when the freewheeling rectifier goes into reverse recovery. Finally, at time t3 the freewheeling rectifier starts to support voltage and drain current and voltage start to fall. The rate of fall of drain voltage is now governed almost exclusively by the Miller effect, and an equilibrium condition is reached, under which the drain voltage falls at just the rate necessary for the voltage between gate and source terminals to satisfy the level of drain current estab-lished by the load. This is why the gate-to-source voltage falls as the recovery current of the freewheeling rectifier falls, then stays constant at a level corresponding to the drain current, while the drain voltage falls. Obviously, the lower the impedance of the gate-drive circuit, the higher the discharge current through the drain-gate self-capacitance, the faster will be the fall time of the drain voltage and the switching losses. Finally, at time t4, the HEXFETis switched fully on, and the gate-to-source voltage rises rapidly towards the applied open circuit value. Similar considerations apply to the turn-off interval. Figure 5 shows theoretical waveforms for the HEXFETin the circuit of Figure 4 during the turn-off interval. At to the gate drive starts to fall until, at tl , the gate voltage reaches a level that just sustains the drain current and the device enters the linear mode of operation. The drain-tosource voltage now starts to rise. The Miller effect governs the rate-of-rise of drain voltage and holds the gate-to-source voltage at a level corresponding to the constant drain current. Once again, the lower the impedance of the drive circuit, the greater the charging current into the drain-gate capacitance, and the faster will be the rise time of the drain voltage. At t3 the rise of drain voltage is complete, and the gate voltage and drain current start to fall at a rate determined by the gate-source circuit impedance.

A STEP OF VOLTAGE CAUSES

VDS Q1

We have seen how and why a low gate drive VDS Q2 impedance is important to achieve high switching performance. However, even when A TRANSIENT switching performance is of no great concern, it ON THE GATE is important to minimize the impedance in the VGS Q1 gate drive circuit to clamp unwanted voltage transients on the gate. With reference to Figure 6, when one HEXFETis turned on or off, a step VGS Q2 of voltage is applied between drain and source of the other device on the same leg. This step of voltage is coupled to the gate through the gate-toFigure 6. Transients of Voltage Induced on the Gate by Rapid drain capacitance, and it can be large enough to Changes on the Drain-to-Source Voltage turn the device on for a short instant (dv/dt induced turn-on). A low gate drive impedance would keep the voltage coupled to the gate below the threshold.

AN-937 (v.Int) In summary: MOS-gated transistors should be driven from low impedance (voltage) sources, not only to reduce switching losses, but to avoid dv/dt induced turn-on and reduce the susceptibility to noise.

4. DRIVING STANDARD HEXFETS FROM TTL

Table 1 shows the guaranteed sourcing and sinking currents for different TTL families at their respective voltages. From this table, taking as an example of the 74LS series, it is apparent that, even with a sourcing current as low as 0.4 mA, the guaranteed logic one voltage is 2.4V (2.7 for 74LS and 74S). This is lower than the possible threshold of a HEXFET . The use of a pull-up resistor in the output, as shown in Figure 7, takes the drive voltage up to 5 V, as necessary to drive the gate of Logic Level HEXFETs, but is not sufficient to fully enhance standard HEXFETs. Section 8 covers the drive characteristics of the logic level devices in detail.

Logic Conditions
Logic Zero Min. sink current for VOL

54 / 74 16mA < 0.4V

54H / 74H 20mA < (0.4V) /

(54L) / 74L 20mA < (0.3V) / 0.4V -0.2mA >2.4V 50ns

(54LS) / 74LS (4) / 8 < (0.4V) / 0.5V -0.4mA > (2.5) / 2.7V 12ns

74S 20mA 0.5V -1.0mA >2.7V 4ns

Logic One
Max. source current for VOH Typical Gate Propagation Delay -0.4mA >2.4V 10ns -0.5mA >2.4V 7ns

Table 1. Driving HEXFETs from TTL (Totem Pole Outputs) Open collector buffers, like the 7406, 7407, etc., possibly with several drivers connected in parallel as shown in Figure 9, give enough voltage to drive standard devices into full enhancement, i.e. data sheet on-resistance. The impedance of this drive circuit, however, gives relative long switching times. Whenever better switching performance is required, interface circuits should be added to provide fast current sourcing and sinking to the gate capacitances. One simple interface circuit is the complementary source-follower stage shown in Figure 9. To drive a MOSFET with a gate charge of 60 nC in 60 ns an average gate current of 1 A has to be supplied by the gate drive circuit, as indicated in INT-944. The on-resistance of the gate drive MOSFETs has to be low enough to support the desired switching times. With a gate charge of 60 nC and at a switching frequency is 100kHz, the power lost in the gate drive circuit is approximately: P = VGS x QG x f = 12 x 60 x 10 x 100 x 10 = 72mW The driver devices must be capable of supplying 1A without significant voltage drop, but hardly any power is dissipated in them.
-9 3

PULL-UP RESISTOR

VH

TTL (TOTEM POLE)

LOAD

Figure 7. Direct Drive from TTL Output

5. DRIVING STANDARD HEXFETS FROM C-MOS

While the same general considerations presented above for TTL would also apply to C-MOS, there are three substantial differences that should be kept in mind: 1. C-MOS has a more balanced source/sink characteristic that, on a first approximation, can be thought of as a 500 ohm resistance for operation over 8V and a 1k ohm for operation under 8V (Table 2).

AN-937 (v.Int) 2. 3. C-MOS can operate from higher supply voltages than 5V so that HEXFETsaturation can be guaranteed. Switching times are longer than those for TTL (Table 2). VH

12V

680

680 IRF320

7407 Figure 8. High Voltage TTL driver and its waveforms When C-MOS outputs are directly coupled to the gate of a HEXFET, the dominant limitation to performance is not the switching time, but the internal impedance (assuming that C-MOS are operated from a 10V or higher voltage supply). It will certainly not be able to turn OFF the HEXFETas fast as the TTL, while the turn-ON waveform will be slightly better than what can be achieved with a 7407 with a 680 ohm pull-up resistor. Of course, gates can be paralleled in any number to lower the impedance and this makes C-MOS a very simple and convenient means of driving HEXFETs. Drivers can also be used, like the 4049 and 4050 which have a much higher current sinking capability (Table 2), but they do not yield any significant improvement in current sourcing. For better switching speeds, buffer circuits, like the one shown in Figure 9, should be considered, not only to provide better current sourcing and sinking capability, but also to improve over the switching times of the CMOS output itself and the dv/dt noise immunity.

IRF7307 OR IRF7507 +12V

VH

LOAD

7 8 1 K 2 1

INPUT

7407 4 3

Figure 9. Simple Interface to Drive HEXFETs from TTL

6. DRIVING HEXFETS FROM LINEAR CIRCUITS

The complementary source follower configuration of Figure 9 can also be used in linear applications to improve drive capability from an opamp or other analog source. Most operational amplifiers have a very limited slew rate, in the order of few V/microsec. This would limit the bandwidth to less than 25kHz. A larger bandwidth can be obtained with better operational amplifiers followed by a current booster, like the ones shown in Figures 10 or 11. For a system bandwidth of 1MHz, the opamp bandwidth must be significantly higher than 1MHz and its slew rate at least 30V/s.

AN-937 (v.Int)

Standard Buffered Outputs

Logic Supply Voltage

4049 / 4050 Drivers

10V 40mA -1.25mA > 9.5V 50ns 20ns 15V 40mA -3.75mA > 13.5V 40ns 15ns

15V 5V Logic Conditions 5V 10V Logic Zero: 1.5mA 3.5mA 4mA 20mA Approximate sink current for VOL < 1.5V -0.5mA -13mA -3.4mA -1.25mA Logic One: > 4.6V > 9.5V > 13.5V > 2.5V Minimum source current for VOH Typical switching times of logic drive signals: 100ns 50ns 40ns 100ns RISE 100ns 50ns 40ns 40ns FALL Table 2. Driving HEXFET s from C-MOS (Buffered) When analog signals determine the switching frequency or duty cycle of a HEXFET, as in PWM applications, a voltage comparator is normally used to command the switching. Here, too, the limiting factors are the slew rate of the comparator and its current drive capability. Response times under 40ns can be obtained at the price of low output voltage swing (TTL compatible). Once again, the use of output buffers like the ones shown in Figures 9, may be necessary to improve drive capability and dv/dt immunity. If better switching speeds are desired. a fast op-amp should be used. In many applications, when the HEXFET is turned on, current transfers from a freewheeling diode into the HEXFET. If the switching speed is high and the stray inductances in the diode path are small, this transfer can occur in such a short time as to cause a reverse recovery current in the diode high enough to short out the dc bus. For this reason, it may be necessary to slow down the turn-on of the HEXFETwhile leaving the turn-off as fast as practical. Low impedance pulse shaping circuits can be used for this purpose, like the ones in Figures 12 and 13.

+12V

VH

LOAD IRF7309 OR IRF7509 FET INPUT OP AMP INPUTS + 4 -12V 5 6 3 0.1 F CER 7 8 2 1

Figure 10. Dual Supply Op-Amp Drive Circuit

VH

+12V

7. DRIVE CIRCUITS NOT REFERENCED TO GROUND

To drive a HEXFETinto saturation, an appropriate voltage must be applied between the gate and source. If the load is connected between source and ground, and the drive voltage is applied between gate and ground, the effective voltage between gate and source decreases as the device turns on. An equilibrium point is reached in which the amount of current flowing in the load is such that the voltage between gate and source maintains that amount of drain current and no more. Under these conditions the voltage drop across the MOSFET is certainly higher than the threshold voltage and the power dissipation can be very high. For this reason, the gate drive circuit is normally referenced to the source rather than to the ground. There are
FET INPUT OP AMP. 2 CA3103

LOAD IRF7307 OR IRF7507 7 8 2 1

+ 4

3 0.1 F CER 5 6

Figure 11. Single Supply Op-Amp Drive Circuit (Voltage Follower)

AN-937 (v.Int) basically three ways of developing a gate drive signal that is referenced to a floating point: 1. 2. By means of optically coupled isolators. By means of pulse transformers.

By means of DC to DC chopper circuits with transformer isolation.

INPUT PULSE T = RC WITH DIODE CONNECTED AS SHOWN IRF7307 OR IRF7507 8 INPUT 2 4 2 1 555 6 1 3 R C 5 6 4 4.7K 7 8 +12V VH

LOAD

Figure 12. A pulse shaper. The 555 is used as an illustration of a Schmitt Trigger pulse shaper

7.1 MGDs with optocouplers

Most optocouplers require a separate supply grounded to the source on the receiving end of the optical link and a booster stage at the output, as shown in Figure 14a. One of the major difficulties encountered in the use of optocouplers is their susceptibility to noise. This is of particular relevance in applications where high currents are being switched rapidly. Because of the dv/dt seen by the VEE pin, the optocoupler needs to be rated for high dv/dt, in the order of 10 V/ns.

VINPUT SLOPE OF V V/SEC RC WITH DIODE CONNECTED AS SHOWN +12V

VH

LOAD C 7 8 2

R CA3103

INPUT

+ 4 C 5 6

Figure 15a shows an MGD with under-voltage lockout and negative gate bias. When powered with a 19 V floating source, the gate drive Figure 13. Pulse shaper implemented with an integrator voltage swings between +15V and 3.9V. D1 and R2 offset the emitter voltage by 3.9V. The switching waveforms shown in Figure 15b are similar to those in Figure 14b except for the negative bias. Q3, D2 and R5 form the under voltage lockout circuit. The LED D2 is used as low voltage, low current reference diode. Q3 turns on when the voltage at the anode of D2 exceeds the sum of the forward voltage of LED and the base-emitter voltage of Q3. This enables the operation of the optocoupler. The tripping point of the under voltage lock-out circuit is 17.5V. The start-up wave forms are shown in Figure 16.

AN-937 (v.Int)

IRF7307 OR IRF7507 7 8 2 1 GATE R1 3.3k 2 ISO1

A VCC OUT EN

BATT1 15V

8 7 6 5 C1 0.1

3 + C2 10 5 6 3.9V EMITTER

VEE

Figure 14a. Simple high current optoisolated driver The auxiliary supply for the optocoupler and its associated circuitry can be developed from the drain voltage of the MOSFET itself, as shown in Figure 17, 18 and 19. This supply can be used in conjunction with the UV-lockout shown in Figure 15 to provide a simple high-quality optoisolated drive. The circuit in Figure 17a can be modified to provide higher output current. By changing C1 to 680pF and R3 to 5.6k, its performance changes to what is shown in Figures 20, 21 and 22. Other methods of developing isolated supplies are discussed in Section 9.

Input: 5V/div

7.2 Pulse transformers

A pulse transformer is, in principle, a simple, reliable and highly noise-immune method of providing isolated gate drive. Unfortunately it has many limitations that must be overcome with additional components. A transformer can only transfer to the secondary the AC component of the input signal. Consequently, their output voltage swings from negative to positive by an amount that changes with the duty cycle, as shown in Figure 23. As a stand-alone component they can be used for duty cycles between 35 and 65%. Output : 5V/div Horiz: 500ns/div Figure 14b: Waveforms associated with the circuit of Figure 14a when loaded with 100nF

IRF7309 OR IRF7509 7 8 R3 10k R5 4.7K 2 1 ISO1

A VCC OUT EN

BATT1 19V

IN+

R1 3.3k

D2 LED 8 7 6 5 2N2222 UNDERVOLTAGE LOCK-OUT OUTPUT BUFFER C1 0.1 R4 1K Q3 R5 1K 5 6 4 3

C2 10 D1 3.9V

GATE EMITTER C3 10 3.9V

IN-

VEE

HCPL2200

SINGLE TO SPLIT POWER SUPPLY

Figure 15a: Optoisolated driver with UV lockout and negative gate bias

AN-937 (v.Int)

VBATT1 5V/div Input: 5V/div Output: 5V/div

Output : 5V/div

FILE: 01A-POL.DAT Horiz: 500ns/div Figure 15b: Waveforms of the circuit in Figure 21a when loaded with 100nF

Horiz: 20ms/div File: 01-UV.dat Figure 16. Start-up waveforms for the circuit of Figure 15a.
Gate Voltage: 10V/div

VCC(300V) Q1 IRF840 R1 DRIVE 10 DRVRTN Q2 IRF840 R4 R 15VRTN R2 100 D1 1N4148 C2 0.1 D3 15V C1 D2 1N4148 R3 +15V

Q1 drain voltage: 200V/div

G2 C2 ripple voltage: 0.5V/div Horiz: 5s/div File: GPS-1.plt

Figure 17a. Drive supply developed from the drain voltage

Figure 17b. Waveforms of the circuit in Figure 23a.C1 = 100 pF, R3 = 5.6 k, f = 50 kHz

Zener Current (mA)

2 C2 voltage: 5V/div.

0 20 30 40 50 60 70 Frequency (kHz) 80 90 100

Figure 18. Zener current (max output current) for the circuit in Figure 23a.

Horiz.: 500s/div File: GPS-3.PLT Figure 19. Start-up voltage at 50 kHz for the circuit in Figure 23a.

AN-937 (v.Int) They have the additional advantage of providing a negative gate bias. One additional limitation of pulse transformers is the fact that the gate drive impedance is seriously degraded by the leakage inductance of the transformer. Best results are normally obtained with a few turns of twisted AWG30 wire-wrap wire on a small ferrite core. Lower gate drive impedance and a wider duty-cycle range can be obtained with the circuit in Figure 24a. In this circuit, Q1 and Q2 (a single Micro-8 package) are used to buffer the input and drive the primary of the transformer. The complementary MOS output stage insures low output impedance and performs wave shaping. The output stage is fed by a dc restorer made by C2 and D1 that references the signal to the positive rail. D1 and D2 are also used to generate the gate drive voltage. The input and output wave form with 1nF load capacitance are shown in Figure 24b. The turn-on and turn-off delays are 50ns. The rise and fall times are determined by the 10 Ohm resistor and the capacitive load. This circuit will operate reliably between 20 and 500 kHz, with on/off times from 0.5 to 15 microsecs.
20 Gate voltage: 10V/div. Zener Current (mA)

Drain voltage: 200V/div.

10

C2 ripple voltage: 1V/div 0 Horiz: 2s/div 10 File: gps-4.plt 20 30 40 50 60 70 Frequency (kHz) 80 90 100

Figure 20. Waveforms of the circuit in Figure 23a. with C1=680pF, R3=1k, f=100kHz.

Figure 21. Zener current (max output current) for the circuit in Figure 23a. with C1 = 680pF, R3 = 1k

C2 voltage: 5V/div

VGS 0

Figure 23. Volt-seconds across winding must balance

Horiz: 100s/div. File: GPS-6.plt

Figure 22. Start-up voltage at 100 kHz for the circuit in Figure 23a. with C1=680pF, R3=R3=1k Due to the lack of an under voltage lock-out feature, the power-up and power down behavior of the circuit is important. Intentionally C1 and C2 are much bigger in value then C3 so that the voltage across C3 rises to an adequate level during the first incoming pulse. The power-up wave forms at 50kHz switching frequency and 50% duty cycle are shown in Figure 25. During the first pulse, the output voltage is 10V only, and drops back below 10V at the fifth pulse.

AN-937 (v.Int)

+12V 8 2 IN 4 Q2 IR7509 12VRTN 3 1 Q1 IR7509

D1 IN4148

2 3 Q3

1 C1 T1 C2 1

R2 10 R3 G

Q4

3 2

10 C4 0.1 R1 100K E 1n LOAD

D2 5 6

IN4148 IRFL014 OR IRFD014 T1: CORE: 331X1853E2A A1=2600 (PHILIPS, OD=0.625", Ae=0.153CM^2) PRIMARY: 17T, SEC.: 27T

Figure 24a. Improving the performance of a gate drive transformer

Input: 5V/div.

Output: 5V/div.

Figure 24b. Waveforms associated with the circuit of Figure 24a

HORIZ: 50S/div.

FILE: X2-START.PLT

Figure 25. Waveforms during start-up for the circuit in Figure 24a.

+12V 7 8 2 1 INPUT 4 C1 0.1 12VRTN 5 6 3 0.47 C2 1 D4 11DQ04 100K C1 1 T1 2 3 4 U2

VCC IN VB HO

R3 8.2K 8 7 6 5 R4 220

D5 C 11DF6 R2 1K G

FAULT CS COM VS

IR2127/8

C5 10n E

T1: CORE: 331X185 3E2A, A1=2600 (OD=0.625", Ae=0.153 CM^2) PRIMARY: 17T, AWG 28 SEC: 27T, AWG 28

Figure 26a. Transformer-coupled MGD with UV lockout and short-circuit protection

AN-937 (v.Int) The power down of the circuit is smooth and free from voltage spikes. When the pulse train is interrupted at the input, the C2 capacitor keeps the input of the CMOS inverter high and R1 discharges C3. By the time the input to the CMOS inverter drops below the threshold voltage of Q4, C3 is completely discharged the output remains low. The addition of a MOS-Gate Driver IC improves the performance of the circuit in Figure 24a, at the expenses of prop delay. The circuit shown in Figure 26a has the following features: - No secondary supply required - Propagation delay ~500ns (CL= 10nF) - Duty cycle range 5% to 85% - Nominal operating frequency 50kHz (20kHz to 100kHz) - Short circuit protection with Vce sensing. Threshold Vce = 7.5V - Undervoltage lock-out at Vcc = 9.5V - Over voltage lock out at Vcc = 20V

Input: 5V/div. Input: 2V/div.

Output: 5V/div.

Output: 5V/div. IR2121 ERR pin: 5V/div.

Horiz.: 500ns/div. Horiz: 1s/div. FILE: X1-ERR.PLT

Figure 26b. Waveforms associated with the circuit of Figure 26a.

Figure 27. Shutdown due to high VCEsat

The short circuit protection is implemented with a Vce sensing circuit in combination with the current sense input (CS) of IR2127/8. When the HO pin if U2 goes high R3 starts charging C5. Meanwhile the IGBT turns on, the collector voltage drops to the saturation level, D5 goes into conduction and C5 discharges. When the collector voltage is high, D5 is reverse biased and the voltage on C5 keeps raising. When C5 voltage exceeds 250mV the IR2127/8 shuts down the output. The fault to shut-down delay is approximately 2 microsecs. For operation with a large duty cycle, several options are available. The circuits described in AN-950 use a saturating transformer to transfer the drive charge to the gate. The circuit shown in Figure 28a, on the other hand, achieves operation over a wide range of duty cycles by using the MGD as a latch. It has the following features: - Frequency range from DC to 900kHz. - Turn-on delay: 250ns. - Turn-off delay 200ns - Duty cycle range from 1% to 99% at 100kHz. - Under voltage and over voltage lockout. - Optional short circuit protection, as shown in Figure 26a In the circuit of Figure 28a the transformer is small (8 turns), since it transmits only short pulses to the secondary side. The MGD on the secondary side of the transformer is latched by the feedback resistor R4. Figures 28b and 28c show the performance of this circuit at the two extremes of 900 kHz and 2.5 Hz

AN-937 (v.Int)
IRF7509 OR IRF7309 +12V 7 8 C1 1 IN 4 3 1nF R1 560 5 12VRTN TRANSFORMER: CORE: 266CT125-3E2A, (OD=0.325", Ae=0.072cm,^2, A1=2135) PRIMARY: 8T, AWG 28 SEC: 8T, AWG 28 6 2 1 C2 R2 T1 4.7K R3 18K 1 2 3 4 R4 18K U1
VCC IN ERR VSS VB HO CS VS

+15V 8 7 6 5

R5 18K G C3 1 E 15VRTN

IR2121

Figure 28a. Transformer-coupled MGD for operation from DC to 900 kHz

Input: 5V/div. Input: 2V/div.

Output: 10V/div.

Reference 60Hz: 10V/div. Output: 25.ns/div. Horiz.: 25.ns/div. File: XP-900K.PLT Horiz: 50ms/div. File: XP-2P5HZ.PLT

Figure 28b. Waveforms associated with the circuit of Figure 28a operated at 900 kHz

Figure 28c. Waveforms associated with the circuit of Figure 28a operated at 2.5 Hz

7.2 Chopping gate drives

Chopper circuits can maintain a gate drive signal for an indefinite period of time, have good noise immunity performance and, with some additional circuitry, the isolated supply can be avoided. The basic operating principle is shown in Figure 29. To turn on the MOSFET, a burst of high frequency is transmitted to the secondary side. The MOSFET is turned off by interrupting the high frequency. The diode and the bipolar transistor form a crowbar that rapidly discharges the gate. In addition to providing the gate drive signal, the high frequency transformer is frequently used to power auxiliary circuitry, like short-circuit protection, thus avoiding a dedicated supply.

8. DRIVE REQUIREMENTS AND SWITCHING CHARACTERISTICS OF LOGIC LEVEL HEXFETS

Many applications require a power MOSFET to be driven directly from 5 V logic circuitry. The on-resistance of standard power MOSFETs is specified at 10 V gate drive, and are generally not suitable for direct interfacing to 5V logic unless an oversized MOSFET is employed.

AN-937 (v.Int) Logic level HEXFETs are specifically designed for operation from 5V logic and have guaranteed on-resistance at 5 or 4.5 V gate voltage. Some have guaranteed on-resistance at 2.7 V. Some important considerations for driving logic level HEXFETs are discussed in this section and typical switching performance of these is illustrated when driven by some common logic drive circuits.

8.1 Comparison to Standard HEXFETs

Some devices are available as Logic-level HEXFETs as well as standard HEXFETs. The logic-level version uses a thinner gate oxide and different doping concentrations. This has the following effects on the input characteristics: Gate Threshold voltage is lower. Transconductance is higher. Input capacitance is higher. Gate-source breakdown voltage is lower.

While input characteristics are different, reverse transfer capacitance, on-resistance, drain-source breakdown voltage, avalanche energy rating, and output capacitance are all essentially the same. Table 3 summarizes the essential comparisons between standard and logic level HEXFETs.

Characteristics and Ratings

Gate Threshold Voltage On-Resistance Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Charge Gate-Source Gate-Drain Total Drain Source Breakdown Voltage Continuous Drain Current Single Pulse Avalanche Energy Max. Gate-Source Voltage VGS(on) RDS(on) gfs Crs Crss Crss Qgs Qgd Qg BVDSS

Standard HEXFET (IRF Series)

2 - 4V

Comparable Logic Level HEXFET (IRL Series)

1 - 2V

Logic level HEXFET has same value of RDS(on) VGS = 5V as standard HEXFETat VGS = 10V RDS(on) of logic level HEXFET also speed at VGS = 4V Typically 39% larger for logic level HEXFET Typically 33% larger for logic level HEXFET Essentially the same Essentially the same Essentially the same Essentially the same Essentially same as VGS = 10V

Essentially same at VGS = 5V Same

Same ID Same EAS + 20V +10V VGS Table 3: Essential Comparisons of Standard and Logic Level HEXFETs

The gate charge for full enhancement of the logic level HEXFETis, however, about the same as for a standard HEXFETbecause the higher input capacitance is counteracted by lower threshold voltage and higher transconductance. Since the logic level HEXFETneeds only one half the gate voltage, the drive energy is only about one half of that needed for the standard HEXFET. Since the gate voltage is halved, the gate drive resistance needed to deliver the gate charge in a given time is also halved, relative to a standard HEXFET. In other words, for the same switching speed as a standard HEXFETpower MOSFET, the drive circuit impedance for the logic level HEXFETmust be approximately halved. The equivalence of switching times at one half the gate resistance for the logic level HEXFETis illustrated by the typical switching times for the IRL540 and the IRF540 HEXFETs shown in Table 4, using data sheet test conditions.

AN-937 (v.Int)

Gate Resistance
RG ( ) 9 4.5

Gate Voltage

Drain Current

Typical Values (ns)

tr 50 56

VGS tr tD on ID tD on (V) (A) 10 28 15 72 40 5 28 15 72 44 Table 4: Typical Resistive Switching Times for IRL540 and IRF540

TTL families do not actually deliver 5V in their VOH condition, even into an open circuit. The 5V level can, however, be reached by the addition of a pull-up resistor from the output pin to the 5V bus, as illustrated in Figure 30. Without the pull-up resistor, the RDS(on) value at VGS = 5V may not be attained, and the value specified at VGS = 4V should be used for worst case design.

CONTROL INPUT

15 V +5V

4 8 7 3 555 2 5 8

LOAD 470 LOAD LOGIC INPUTS

RET

Figure 30. Pull-up resistor used to deliver 5V gate drive Figure 29.

8.2 Driving Logic Level HEXFETs

The gate threshold voltage of MOSFETs decreases with temperature. At high temperature it can approach the VOL(max) specification of the logic driver. Care should be exercised to insure that VTH(min) at the highest operating temperature is greater than VOL(max) of the various logic families in order to guarantee complete turn off.
+VDD RL D LD DRIVE R1 G R1 G D LD RL +VDD

LS

LS

S LW SIG. RET. RET. SIG. RET.

S LW

RET.

Figure 31a. High common mode inductance

Figure 31b. Minimum common mode inductance

AN-937 (v.Int) Common source inductance plays a significant role in switching performance. In the circuit of Figure 31a the switching performance is degraded due to the fact that VGS is reduced by (LS + LW) di/dt, where di/dt is the rate of change of the drain current. By eliminating LW from the drive circuit, VGS can approach the applied drive voltage because only LS (the internal source inductance) is common. This can be done by separately connecting the power return and the drive signal return to the source pin of the switching HEXFET, as shown in Figure 31b. Thus, the load current ID does not flow through any of the external wiring of the drive circuit; consequently, only the internal source inductance LS is common to both load and drive circuits. In the case of logic level HEXFETs, for which VGS is 5V and not 10V, the loss of drive voltage due to common mode inductance has proportionately twice the effect as it would on a 10V drive signal, even though actual values of LS and LW are the same.

8.3 Resistive Switching Tests

In the following tests of switching performance, the physical layout of the test circuit was carefully executed so to minimize the common source inductance. The following precautions were also observed: 1. 2. 3. 4. 5. RL was built by paralleling 0.5W resistors to achieve the desired load resistance (see Table 5). To minimize inductance in the load circuit, a 10 F low-ESR low-ESL capacitor was connected directly from +VDD to the source of the DUT. To provide a low source impedance for the 5V gate pulse of the DUT, a 0.1 F low-ESR low-ESL capacitor was connected directly between pin 14 and pin 7 of the driver IC. To provide minimum common source impedance, the source of the DUT was the common return point of all ac and dc system grounds. To reduce stray inductances and thus achieve maximum switching speeds, the physical size of the high current loop (RL, DUT, 10 F) was reduced to the smallest practical limits.
+5V +VDD = 0.5 BVDSS RL DUT +5V 0 SIG. GEN. VSS 1 2 3 0.1pF 50 7, 4, 5, 9 10, 12, 13 0.1pF SCOPE

15

Figure 32. Switching test circuit. Logic level driver is one-quarter of a quad NAND gate. Only the 5 volt families have been tested as logic level HEXFETdrives: bipolar and CMOS (and their derivatives), as indicated below. TTL GATES DM7400N: 74F00PC: DM74S00N: DM74LS00N: DM74AS00N: Standard TTL High Speed TTL Schottky TTL Low Power Schottky TTL Advanced Schottky TTL

AN-937 (v.Int) CMOS GATES 74AC00PC: 74ACT00PC: MM74HC00N: MM74HCT00N: Advanced CMOS TTL Compatible CMOS Micro CMOS TTL Compatible Micro CMOS

BIPOLAR DS0026: High Speed MOSFET Driver

The test conditions for the resistive switching performance is shown in Table 5. The resistive switching times obtained with the above TTL and CMOS gates are tabulated in Table 6. In this table ton = Time in microseconds from 90% to 10% VDD and toff = Time in microseconds from 10% to 90% VDD. Inductive switching gives faster voltage rise times than resistive switching due to the resonant charging of the output capacitance of the device. Voltage fall times are essentially the same.

LOGIC LEVEL HEXFET

IRLZ14 IRLZ24 IRLZ34 IRLZ44 IRLZ514 IRLZ524 IRLZ524 IRLZ544

SWITCHING VOLTAGE (V)

SWITCHING CURRENT (A)

RDSON ( )
0.24 0.12 0.06 0.034 0.60 0.30 0.18 0.085

RL ( )
3.25 1.5 1.2 0.7 9.5 5.9 4.0 1.9

8 30 16 30 24 30 40 30 5 50 8 50 12 50 25 50 Table 5. Resistive Switching Conditions

Logic Family Quad, Dual Input Nand Gate

DM7400N STANDARD TTL 7400FDOPC HIGH SPEED TTL DM7400 SCHOTTKY TTL DM74LS LOW POWER SCHOTTKY TTL DM4SDON ADVANCED SCHOTTKY TTL 74ACOOPC ADVANCED CMOS 74ACTOOPC TTL COMPATIBLE CMOS MM74CHCOON MICRO CMOS MM74HCTCO4 TTL COMPATIBLE MICRO CMOS DS0026 HIGH SPEED MOSFET DRIVER

IRLZ14 ton toff

0.173 0.124 0.133 0.174 0.126 0.012 0.012 0.066 0.066 0.052 0.018 0.008 0.092 0.038 0.008 0.007 0.006 0.039 0.030 0.005

IRLZ24 ton toff

0.663 0.490 0.549 0.778 0.567 0.120 0.121 0.179 0.179 0.016 0.026 0.013 0.020 0.093 0.013 0.012 0.011 0.091 0.060 0.005

Logic Level HEXFET, IRLZ34 IRLZ44 IRL514 IRL524 ton toff ton toff ton toff ton toff
0.700 0.429 0.503 0.706 0.446 0.125 0.125 0.227 0.227 0.014 0.076 0.068 0.032 0.146 0.023 0.027 0.016 0.147 0.123 0.007 1.491 0.863 1.068 1.438 0.896 0.251 0.233 0.508 0.504 0.032 0.146 0.146 0.142 0.342 0.149 0.139 0.127 0.328 0.269 0.016 0.151 0.104 0.116 0.155 0.111 0.036 0.033 0.058 0.068 0.021 0.022 0.004 0.006 0.040 0.005 0.004 0.044 0.044 0.035 0.004 0.238 0.159 0.183 0.240 0.161 0.052 0.052 0.092 0.092 0.036 0.041 0.034 0.041 0.062 0.127 0.028 0.027 0.068 0.051 0.004

IRL534 ton toff

0.263 0.176 0.212 0.267 0.176 0.066 0.060 0.111 0.111 0.036 0.060 0.059 0.057 0.090 0.058 0.055 0.055 0.096 0.086 0.005

IRL544 ton toff

0.616 0.372 0.441 0.567 0.336 0.125 0.120 0.232 0.232 0.029 0.124 0.136 0.132 0.199 0.130 0.125 0.122 0.213 0.186 0.009

Table 6. Results of the resistive load switching test

Typical Test Oscillograms IRLZ24: 60V, 0.1 Ohm, N-Channel, TO-220 logic level HEXFETwas driven by each of the logic families listed in Table 4 and the comparative resistive switching times photographed.

AN-937 (v.Int)

9. SIMPLE AND INEXPENSIVE METHODS TO GENERATE ISOLATED GATE DRIVE SUPPLIES

. In several applications, dc-to-dc converters are used to power the MOS Gate Driver. Although the gate drive requires little power, the noisy environment, the isolation voltage and creepage distance requirements and the high dv/dt between the primary and secondary size make the design of the DC-to-DC converter somewhat complicated. Its key parameters are listed below: OUTPUT VOLTAGE, CURRENT. The output voltage of the DC-to-DC converter is the sum of the positive and negative drive voltage to the gate. The load current required from the DC-to-DC converter is the sum of the current consumption of the drive circuit and the average drive current to the gate. dv/dt CAPABILITY. When the DCDC converter powers a high side switch, the secondary side of the converter is connected to the output of the power circuit. The rapid change of high voltage at the output of power circuit stresses the isolation of the transformer and injects noise to the primary side of the transformer. Switching noise at the primary side disturbs the operation of the converter and the control circuit for the power stage, causing false triggering and shoot-through. Therefore a transformer with high voltage isolation, appropriate creepage distances and low winding-towinding capacitance is required in this application.
4X IN4148 12K 1N4148 20K IRFD110 5 6 1n 12V RTN 4 13 12 11 100 1F T1

+12V

V0

1F RL

CD4093

f = 100kHz (OD = 0.75", Ae=0.148CM^2, AI=3000) PRIMARY: 14 TURNS, AWG 30 TEFLON INSULATED WIRE SECONDARY: 24 TURNS, AWG 30 TEFLON INSULATED WIRE

T1 TRANSFORMER: DORE: PHILIPS 240XT250-3EA2 TOROID

Figure 33a. 100 kHz Forward converter

SMALL SIZE. To reduce the interwinding capacitances the transformer must be made small. This implies operation at high frequency. Small size and compact layout help reducing the EMI and RFI generated by the converter. Figure 33a shows a forward converter made with two CD4093 gates to generate the clock and drive the MOSFET. Energy as transferred to the secondary when the MOSFET is on, in about 33% of the cycle. When the MOSFET is off, the secondary winding is used to demagnetize the transformer and transfer the magnetizing energy to the load, thus eliminating the need for a demagnetizing winding. The switching waveforms are shown in Figure 33b. The ringing in the drain voltage during the fly-back period is due to the loose coupling between the primary and the secondary windings. The load current vs. output voltage characteristic of the circuit is shown in Figure 34. When the output current falls below 5 mA, the circuit works as flyback converter because the demagnetizing current flows through the output. A minimum load of 5mA is required to limit the output voltage at 15V.
35 Drain voltage: 10V/div. 30 Output Voltage (V) Gate voltage: 5V/div. Horiz: 2s/div. 25

20 15

10 0 20 40 60 80 100 120 Load current (mA)

Figure 33b. Waveforms associated with the circuit in Figure 33a

Figure 34. Load current vs. output voltage at 100 kHz, Rout = 27.7 Ohms

AN-937 (v.Int) If the converter is loaded with a 4X constant and predictable load, a zener IN4148 V0 +12V can provide the necessary regulation. T1 14 1 1F 3 1K 1N4148 Otherwise a three-terminal regulator 2 or a small zener-driven MOSFET may IRFD110 9 6K be necessary. 10 1F 8 The circuit in Figure 35a is similar to 100 RL 13 5 the previous one, except that the 11 4 6 12 higher switching frequency is higher (500 kHz) and the transformer is f = 500kHz 220p smaller. The remaining three gates in 7 CD4093 12V the package are connected in parallel RTN to drive the MOSFET and reduce the T1: CORE: PHILIPS 266CT125-3E2A (od=0.375", Ae=0.072CM^2, AL=2135 switching losses. The switching waveforms are shown in Figure 35b. PRIMARY: 4T, AWG 30, SECONDARY: 7T, AWG30 The output resistance (Rout) of this Figure 35a. 500 kHz Forward converter circuit is higher than the circuit shown in Figure 33a, mainly because the stray inductance of the smaller transformer is higher and the effects of the stray inductance are higher. Figure 37a shows a pushpull operated at 500 kHz. The single gate oscillator produces a 50% duty cycle output, while the remaining gates in the package are used to drive the push-pull output stage. The primary of the transformer sees half the voltage compared to the previous circuit, therefore the number of turns at the primary were reduced to half.
30 Drain Voltage: 10V/div. 25 Output voltage (V) Gate voltage: 5V/div. Horiz.: 250ns/div.

20

15

10 0 10 20 30 Load current (mA) 40 50

Figure 35b. Waveforms associated with the circuit in Figure 35a

Figure 36. Load current vs. output voltage, Rout = 27.7 Ohms

10. PHOTOVOLTAIC GENERATORS AS GATE DRIVERS

A photovoltaic generator is a solid state power supply powered by light, normally an LED. The combination of the LED and the photovoltaic generator in one package is called a Photovoltaic Isolator or PVI and is available in a 8-pin DIP package. As a voltage source, the PVI can function as a dc transformer by providing an isolated low current to a load. While an optoisolator requires a bias supply to transmit a signal across a galvanic barrier, the PVI actually transmits the energy across the barrier. More information on the PVI can be found in Application Note GBAN-PVI-1 which appears in the Microelectronic Relay Designer s Manual. This data book also contains the data sheet for the photovoltaic isolator, the PVI1050. A circuit is also provided in the AN to significantly speed up turn off of the switch. As a gate driver the PVI has significant limitations: its short circuit current is in the order of 30 microA with a very high internal impedance. Its simplicity, however, makes it appealing in solid-state relay replacements, where switching times are not important and switching transients are not present. A typical application is the ac switch described below. The IGBT and the power MOSFET are not suited to switching AC waveforms directly. The IGBT can only conduct current in one direction while the power MOSFET has an anti-parallel diode that will conduct during every negative half-cycle. Bidirectional blocking capability can be achieved by connecting two power MOSFETs source to source, or two IGBTs with anti-parallel diodes emitter to emitter, as shown in Figure 39.

AN-937 (v.Int) In the case of the MOSFET, there is the possibility that, for low current levels, the current flows through both MOSFET channels, instead that one MOSFETs and diode, thereby achieving lower overall voltage drop. The MOSFET channel is a bidirectional switch, that is, it can conduct current in the reverse direction. If the voltage across the MOSFET channel is less than the VF of the intrinsic diode (which typically has a higher VF than discrete diodes), then the majority of the current will flow through the MOSFET channel instead of the intrinsic diode. The gate drive for both the MOSFETs and IGBTs must be referenced to the common sources or emitters of the devices. Since this node will be swinging with the AC waveform, an isolated drive is necessary. The PVI can be used, as shown in Figure 40.

+12V 1 10K 5 6 2 9 4 CD4093 12V RTN 220p 8 13 12 14 3 10 100 11 4 1F 2

7, 8 100nF 100nF T1 1 3 7T 2T 5, 6

1N4148

V0

1F

RL

IRF7307

7 f = 500kHz

1N4148 T1: CORE: PHILIPS 266CT125-3E2A (od=0.375", Ae=0.072CM^2, AL=2135 PRIMARY: 4T, AWG 30, SECONDARY: 7T, AWG30

Figure 37a. 500 kHz Forward converter

11. RESONANT GATE DRIVE TECHNIQUES

As indicated in Section 14, gate drive losses in hard switching are equal to Qgs x Vgs x f. An IRF630 operated at 10 Mhz with a gate voltage of 12 V would have gate drive losses of 3.6 W, independent from the value of the gate drive resistor. Clearly, to achieve hard switching at this frequency, the resistance of the gate drive circuit is limited to whatever is associated with the internal impedance of the driver and with the gate structure of the device itself. Furthermore, the stray inductance of the gate drive circuit must be limited to tens of nH. The design and layout of such a circuit is not an easy task. An alternative method to drive the gate in such an application is to design a resonant circuit that makes use of the gate capacitance and stray inductance as its reactive components, adding whatever inductance is necessary to achieve resonance at the desired frequency. This method can reduce the peak of the gate drive current and losses in half, while simplifying the design of the gate drive circuit itself. Since the gate charge is not dissipated at every switching transition, but stored in a reactive component, the gate drive losses are proportional to the resistance of the gate drive circuit, rather than being independent from it. More information on this gate drive method can be found in an article by ElHamamsy: Design of High-Efficiency RF Class-D Power Amplifier and in references at the end of this article (IEEE Transactions on Power Electronics, May 1994, page 297).

Buffer input: 5V/div.

Buffer Output: 5V/div.

Horiz.: 500ns/div Figure 37b. Waveforms associated with the circuit in Figure 37a

20 19 18 17 16

Related Topics
15

MOS-Gate Driver Ics Transformer drive with wide duty cycle capability Gate Charge Three-phase MOS-Gate Driver Photovoltaic Isolators (PVI)

14 13 0 10 20 30 40 50 60

Figure 38. Load current vs. output voltage, Rout=27.7 Ohms

AN-944 (v.Int)

Use Gate Charge to Design the Gate Drive Circuit for Power MOSFETs and IGBTs
Topics covered: Background Test method How to interpret the gate charge curve How to estimate switching times How to compare different devices

1.

Input behavior of a MOS-gated transistor

Designers unfamiliar with MOSFET or IGBT input characteristics begin drive circuit design by determining component values based on the gate-to-source, or input, capacitance listed on the data sheet. RC value based on the gate-to-source capacitance normally lead to a gate drive that is hopelessly inadequate. Although the gate-to-source capacitance is an important value, the gate-to-drain capacitance is actually more significantand more difficult to deal withbecause it is a non-linear capacitance affected as a function of voltage; the gate-to-source capacitance is also affected as a voltage function, but to a much lesser extent. This gate-to-drain capacitance function is similar to that found in vacuum tube amplifiers. The gate-to-drain capacitance effect is akin to the Miller effect, a phenomenon by which a feedback path between the input and output of an electronic device is provided by the interelectrode capacitance. This affects the total input admittance of the device which results in the total dynamic input capacitance generally being greater than the sum of the static electrode capacitances. The phenomenon of the effects of the plate impedance and voltage gain on the input admittance was first studied in vacuum tube triode amplifier circuits by John M. Miller. Essentially, at high frequencies where the grid-to-plate (gate-to-drain) capacitance is not negligible, the circuit is not open but involves a capacitance that is a function of the voltage gain. Solving for the "Miller" effect is not exactly a straightforward process, even with vacuum tubes where much is known, but is even more difficult in MOSFETs. In actuality, the gate-to-drain capacitance though smaller in static value than the gate-to-source capacitance, goes through a voltage excursion that is often more than 20 times that of the gate-to-source capacity. Therefore, the gate-to-drain or Miller capacitance typically requires more actual charge than the input capacitance. To account for both gate-to-source and gate-to-drain capacitance in a way readily usable by designers, International Rectifier supplies a gate charge specifications .68F for its IGBTs and + HEXFET POWER ID SET 100 9V 100K MOSFETs. that can 2W be used to calculate .1F drive circuit +20V +20V HEXFET 1 requirements. Gate C1 .1F charge is defined as 22pF .1F 100pF 5V ID MONITOR the charge that must 5-10 MSEC +V + 1W5301 500Hz be supplied to the 8 - D1 gate, either to swing 5 1 3 1/2 7 DUT DS0026 the gate by a given 1N414B 4.7K 1K 100 V51 amount, or to achieve 4 U1A full switching.
U1B IG VGS

2.

Test Circuit

Figure 1. HEXFET POWER MOSFET Gate Charge Circuit. A typical test circuit that can be used to measure the gate charge is shown in Figure 1. In this circuit, an approximately constant current is supplied to the gate of the device-under-test from the 0.1 microfarad capacitor C1, through the regulator diode D1. A constant current in the drain circuit is set by setting the voltage on the gate of HEXFET POWER MOSFET 1, so the net measurement of the charge consumed by the gate is relative to a given current and voltage in the source-to-drain path.

AN-944 (v.Int)
OPW 2 VZR 0 2V 2S

1 WFM

2 WFM WFM 2S

OPW 0

VZR 0

2V

0 WFM

0 WFM WFM

OPW 3

VZR 0

2V

2S

An oscillogram of the gate-to-source voltage during testing, shown in Figure 2, relates the gate voltage to time. Since a constant current is supplied to the gate, the horizontal time scale is directly proportional to the charge supplied to the gate. With a suitable scaling factor, therefore, this oscillogram is a plot of gate voltage versus charge. The point on the oscillogram of the second voltage rise indicates where the device is fully switched on. During the first voltage rise, the gate-to-source capacitance is charging, and during the flat portion, the gate-to-drain capacitance is charging. This oscillogram therefore clearly differentiates between the charge required for the gate-source and gate-to-drain (Miller) capacitances. At the second voltage rise, both capacitances are charged to the extent needed to switch the given voltage and current. A more detailed explanation of the interpretation of this data is given later. The graph in Figure 3 represents gate voltage versus gate charge in nanocoulombs for an IRF130. Although the second voltage rise indicates the point at which the switching operation is completed, normal design safety margins will dictate that the level of drive voltage applied to the gate is greater than that which is just required to switch the given drain current and voltage. The total charge consumed by the gate will therefore in practice be higher than the minimum required-but not necessarily significantly so. For example, the gate charge required to switch 12 amps at 80 volts is 15 nanocoulombs (point A), and the corresponding gate voltage is about 7 volts. If the applied drive voltage has an amplitude of 10 volts (i.e. a 3 volt margin), then the total gate charge actually consumed would be about 20 nanocoulombs, (point B). As shown on the graph, whether switching 10 volts or 80 volts in the drain circuit, there is a much less than proportional difference in the charge required. This is because the Miller capacitance is a nonlinear function of voltage, and decreases with increasing voltage.
C VDS = 10V 10V 80V 80V B

14 2 WFM 3 WFM WFM 12 10

Figure 2. Gate Charge Waveform for Different Values of Drain Voltage (IRF130: lG = 1.5 mA, ID =1A, VDD = 10, 40 and 80 volts). The importance of the gate charge data to the designer is illustrated as follows. Taking the charge are required to switch a previous example, about 15 nanocoulombs of gate if 1.5 amps is supplied to the gate, the device will be drain voltage of 80 volts and a drain current of 12 amps. Since the 15 nC gate charge is the product of the gate input current and the switching time, switched in 10 nS. It follows that if 15 mA is supplied to the gate, then switching occurs in 1 ms, and so on. These simple calculations immediately tell the designer the trade-offs between the amount of current available from the drive circuit and the achievable switching time. With gate charge known, the designer can develop a drive circuit appropriate to the switching time required. Consider a typical practical example of a 100 kHz switcher, in which it is required to achieve a switching time of 100 nanoseconds.
VGS VOLTS

8 A 6 4 ID = 1A 2 ID = 12A

10

15

20

25

30

QG NANOCOULOMBS

Figure 3. Gate Voltage Versus Gate Charge for the IRF130.

AN-944 (v.Int) The required gate drive current is derived by simply dividing the gate charge, 15 X 10-9, by the required switching time, 100 X 10-9, giving 150 mA. From this calculation, the designer can further arrive at the drive circuit impedance. If the drive circuit applies 14 volts to the gate, for instance, then a drive impedance of about 50 ohms would be required. Note that throughout the flat part of the switching period (Figure 3), the gate voltage is constant at about 7 volts. The difference between the applied 14 volts and 7 volts is what is available to drive the required current through the drive circuit resistance. The gate charge data also lets the designer quickly determine average gate drive power. The average gate drive power, PDRIVE, is QGVGf. Taking the above 100 kHz switcher as an example, and assuming a gate drive voltage VG of 14 volts, the appropriate value of gate charge QG is 27 nanocoulombs (point C on Figure 3). The average drive power is therefore 27 X 10-9 X 14 X 105 = 0.038 Watts. Even though the 150 mA drive current which flows during the switching interval may appear to be relatively high. the average power is minuscule (0.004%) in relation to the power being switched in the drain current. This is because the drive current flows for such a short period that the average power is negligible. Thus actual drive power for MOSFETs is minute compared to bipolar requirements, which must sustain switching current during the entire ON condition. Average drive power, of course, increases at higher frequencies, but even at 5 MHz it would be only 1.9W.

3.

The Gate Charge Curve

The oscillograms of the gate-to-source voltage in Figure 2 neatly delineate between the charge required for the gate-to-source capacitance, and the charge required for the gate-to-drain, or Miller capacitance. The accompanying simplified test circuit and waveform diagram ( Figures 4 and 5 respectively) give the explanation. Before time t0, the switch S is closed; the device under test (DUT) supports the full circuit voltage, VDD, and the gate voltage and drain current are zero. S is opened at time t0; the gateto-source capacitance starts to charge, and the gate-to-source voltage increases. No current flows in the drain until the gate reaches the threshold voltage. During period T1 to t2, the gate-to-source capacitance continues to charge, the gate voltage continues to rise and the drain current rises proportionally. So long as the actual drain current is still building up towards the available drain current, ID, the freewheeling rectifier stays in conduction, the voltage across it remains low, and the voltage across the DUT continues to be virtually the full circuit voltage, VDD. The top end of the drain-to-gate capacitance CAD therefore remains at a fixed potential, whilst the potential of the lower end moves with that of the gate. The charging current taken by CAD during this period is small, and for practical purposes it can be neglected, since CAD is numerically small by comparison with GCS. At time t2, the drain current reaches ID, and the freewheeling rectifier +VDD shuts off; the potential of the drain now is no longer tied to the supply voltage, VDD. The drain current now stays constant at the value ID enforced by the circuit, whilst the drain voltage starts to fall. Since the gate voltage is inextricably related to the drain current by the intrinsic transfer characteristic of the DUT (so long as operation remains in the ID active region), the gate voltage now stays constant because the enforced drain current is constant. For the time being therefore, no further charge is consumed by the gate-to-source capacitance, because the gate voltage remains constant. Thus the drive current now diverts, CDG D in its entirety, into the Miller capacitance CAD, and the drive circuit charge now contributes exclusively to discharging the Miller G capacitance. The drain voltage excursion during the period t2 to t3 is relatively large, and hence the total drive charge is typically higher for the Miller S IG S CGS capacitance CAD than for the gate-to-source capacitance GCS. At t3 the drain voltage falls to a value equal to ID x RDS(ON) , and the DUT now comes out of the active region of operation. (In bipolar transistor Figure 4. Basic Gate Charge Test Circuit terms, it has reached saturation. The gate voltage is now no longer constrained by the transfer characteristic of the device to relate to the drain current, and is free to increase. This it does, until time t4, when the gate voltage becomes equal to the voltage behind the gate circuit current source. The time scale on the oscillogram of the gate-to-source voltage is directly proportional to the charge delivered by the drive circuit, because charge is equal to the product of current and time, and the current remains constant throughout the whole sequence. Thus the length of the period t0 to t1 represents the charge QGS consumed by the gate-to-source capacitance, whilst the length of the period t2 to t3 represents the charge QGD consumed by the gate-to-drain or "Miller" capacitance. The total charge at time t3 is the charge required to switch the given voltage VDD and current ID. The additional charge consumed after time t3 does not represent switching charge; it is simply the excess charge which will be delivered by the drive circuit because the amplitude of the applied gate drive voltage normally will be higher (as a matter of good design practice) than the bare minimum required to accomplish switching.

AN-944 (v.Int) 4. Beware When Comparing Different Products Manufacturers sometimes make technical claims for their products that appear to be plausible, but which in actuality do not stand up to scrutiny. A case in point concerns the input capacitance of a power MOSFET. Statements such as the input capacitance of device Y is less than that of device X, ergo Y is a faster switch than X, are frequently bandied about, but are just as frequently erroneous. Apart from the obvious speciousness of many such statements apples are frequently not compared with apples, and obviously larger chips have more self capacitance than smaller onesthe more basic fundamentals are generally overlooked. As this application note shows, of bottom line importance is the total gate charge required for switching. The lower the charge, the lower is the gate drive current needed to achieve a given switching time. A general comparison between hypothetical MOSFETs brands X and Y is illustrated in the Figure. Device X has a higher input capacitance; hence the initial slope of its gate charge characteristic is less than that of device Y. QGS of device X is, however, about the same as that of device Y, because it has a higher transconductance and therefore requires less voltage on its gate for the given amount of drain current (VGX is less than VGY) The Miller charge consumed by device X is considerably less than that consumed by device Y. The overall result is that the total charge required to switch device X, QX, is considerably less than that required to switch device Y, QY. Had the comparison between devices X and Y been made on the more superficial basis of input capacitances, it would have been concluded erroneously that Y is better than X. Another consideration is the energy required for switching. Again, device X scores handsomely over device Y in this example. The energy is the product of the gate charge and the gate voltage, and is represented by the area of the rectangle whose corner lies at the switching point. (Point 1 for device X, and point 2 for device Y.) It is obvious that X requires significantly less gate energy than Y. To summarize: beware of superficial comparisons. Check the full facts before deciding which MOSFET really has the edge in switching performance.
QGS QGD

VG GATE VOLTAGE VG(TH)

t0

t1

t2 DRAIN VOLTAGE

t3

t4 t DRAIN CURRENT

VDD ID

WAVEFORM

Figure 5. Basic Gate Charge Waveforms

VG QY QDGY QDGY DEVICE Y DEVICE X VGX 0 QDGX QX 1 2 AREA OF THIS RECTANGLE (0,2 DIAGONAL CORNERS) IS GATE ENERGY FOR DEVICE Y Q AREA OF THIS RECTANGLE (0,1 DIAGONAL CORNERS) IS GATE ENERGY FOR DEVICE X

VGY

Figure 6. Comparison of Gate Charge Characteristics of Different Device Types. Related Topics: Gate drive considerations for IGBT modules Gate drive characteristics of IGBTs Gate drive requirements of MOS-gated transistors High-voltage gate drive ICs Three-phase gate drive IC Gate drive IC for ballasts Transformer-isolated gate driver

AN-950 (v.Int)

Transformer-Isolated Gate Driver Provides very large duty cycle ratios

(HEXFET is the trademark for International Rectifier Power MOSFETs) Transformer coupling of low level signals to power switches offers several advantages such as impedance matching. DC isolation and either step up or step down capability. They also provide negative gate bias to reduce the risk of dv/dt induced turn-on. Unfortunately, transformers can deliver only AC signals since the core flux must be reset each half cycle. This constant volt seconds property of transformers results in large voltage swings if a narrow reset pulse, i.e., a large duty cycle is required (Figure 1).

-3E

T/3

NOTE: VOLT-SECONDS PRODUCT IN SHADED AREAS MUST BE EQUAL. THIS CAUSES RESET VOLTAGE TO BE 3 TIMES APPLIED VOLTAGE E.
Q1 Z1 T1

Figure 1. Constant-Volt-Seconds Characteristics of Transformers

Q2 POWER SWITCH

1:1

Figure 2. Wide Duty Cycle HEXFET Power MOSFET Driver circuit For this reason transformers in semiconductor drive circuits are limited to 50%, duty cycle or roughly equal pulse widths positive and negative because of drive voltage limitations of the semiconductors +12V themsevles. For large duty cycle ratios designers must choose an A LOW LEVEL LOGIC SIGNAL 0 alternative to the transformer, such as -12V an optical coupler to provide the +12V necessary drive isolation.
B 0 -12V +12V C 0 -12V VDS POWER HEXFET Q2 VGS POWER HEXFET Q2 T1 WINDING VOLTAGE

Optoisolators for power electronics require high dV/dt capability and are expensive. They also require additional floating power sources which add complexity and cost. Most of them require a buffer stage to handle the large gate capacitances, typical of power devices. If duty cycles are such that optoisolators are the only alternative, they can be used in a more cost-effective way as drivers for a MOS-gate driver.

Figure 3. Waveform Characteristics of HEXFET POWER MOSFET Driver Circuit

The circuit in Figure 2 provides a low impedance turn-on drive, and minimum pulse widths (on or off) of approximately 1 microsecond; furthermore, it can have any desired voltage ratio, and provides electrical isolation. In Figure 2, Q2 is the main power device, shown as a MOSFET, providing the switching function for a switching power supply, motor drive or other application requiring isolation between the low level logic and high power output. Ql is a low power HEXFET Power MOSFET such as the IRLML2803, which is used to control the drive signals to Q2, and T1 is a small 1:1 driver transformer providing electrical isolation from, and coupling to, the low level circuitry.

AN-950 (v.Int) The waveforms in Figure 3 explain the circuit operation. Waveform A is the desired logic signal to be switched by Q2. When this voltage is applied to the primary of T1 the waveform is supported by changing core flux until saturation occurs as shown in waveform B. At this time the winding voltages fall to zero and remain so until the core flux is reversed by the negative-going portion of waveform A saturation will again occur if the negativeapplied pulse exceeds the voltseconds capability of the core.

VIN

VO

GROUND REFERENCE LOGIC

Figure 4. Single Switch Regulators

During the positive portion of the secondary waveform, which, of course, has the same form as the primary, the intrinsic diode of Ql is in forward conduction and Q2 receives a positive gate drive voltage with a source impedance of Z1 plus the intrinsic diode forward impedance. In a practical circuit this can be less than 10 Ohms total, with a consequent turn-on time of around 75nsec. When T1 saturates, the intrinsic diode of Q1 isolates the collapse of voltage at the winding from the gate of the power device and the input capacitance Ciss of the power switch holds the gate bias at the fully enhanced condition for a time limited only by the gate leakage current of Q2 as indicated in Figure 3c. When waveform A goes 12 volts negative Ql will become fully enhanced; and the main switch Q2 will now be turned off at approximately -12V at a source impedance Z1 + RDS(ON) of Q2. This will again be less than 10 Ohms and will yield a turn-off time less than 100nsec. When T1 again saturates, during the negative half cycle, its winding voltages fall to zero and Q1 turns off. As T1 voltage collapses, the gate of Q2 also follows this voltage and remains at zero bias.

IRF840 IRFD1ZO

IRF840 IRFD1ZO HEXFET AVALANCE PROTECTION

IRF840 IRFD1ZO

IRF840 IRFD1ZO

Figure 5. High Voltage, High Power HEXFET Power MOSFET Switch (500V, 8A per Section)

The drain voltage of the power HEXFET Power MOSFET Q2 appears in Figure 3d, showing that it is indeed a mirror image of waveform A, the desired low level logic signal. Note that because T1 need only support a 12V signal, for 1msec or less, it is very smalland inexpensive. In a practical circuit Z1 is frequently a 0.1 mF capacitor, and the signal source is a low impedance driver such as a PWM controller or gate driver.

AN-950 (v.Int) It should be noted that the circuit in Figure 3(b) may not provide the necessary noise immunity when the power device is off. The gate-source voltage of Q2 in the OFF state returns to zero when T1 saturates and the only noise immunity is provided by the threshold voltage of Q2 (2V < VTH < 4V). In most applications it may be desirable to provide more noise immunity, by adding another small N-Channel HEXFET Power MOSFET (typically another IRLML2803) as shown in Figure 7. The circuit now provides -12V to the power MOSFET after the transformer saturates, and this reverse bias remains until the next positive half cycle of drive. Thus, a minimum of 14V noise immunity is provided which should be adequate for all applications. The cost and noise immunity of this solution is much less than alternatives using optoisolators and their auxiliary supplies. Figures 5 and 6 show two applications where this gate drive method is particularly advantageous. The first is a high-voltage, high-frequency switch. The second is a bi-directional ac switch.

Transformer T1 Considerations In the circuits illustrated, the transformers were built from miniature tape wound or ferrite toroids. Typical part numbers for these cores are as follows: (1) Tape Wound Cores Magnetics Inc. #80558-(1/2D)MA #52402-ID (2) Ferrite Toroids Ferroxcube #266CT 125-3E2A or equivalent

IRF840 IRFD1Z0 ON INTRINSIC DIODES

IRFD1Z0

IRFD1Z0

OFF

ADDITIONAL CAPACITANCE FOR LONG SWITCH PERIODS

IRF840

Figure 6. Bi-directional AC Switch using HEXFET POWER MOSFET

Figure 7. Driver Circuit with additional Noise Immunity

Choice of a core type is not critical provided that 10 to 20 turns bifilar of suitable wire can be hand-wound onto it. The size of core should be chosen so that adequate insulation thickness can be used for the isolation voltage requirements and to reduce interwinding capacitance. Square Permalloy 80 cores are more expensive than ferrite types, but they have much narrower hysteresis loops and hence need fewer ampere turns of excitation. This can make a critical difference when the driver has limited current capability. Bifilar windings improve the magnetic coupling of primary to secondary. and it is also important to space the turns to occupy 360 of the core circumference to minimize leakage inductance. Unity turn ratios between primary and secondary also serve to minimize leakage inductance and hence optimize the transformer coupling coefficient.

Related Topics: MOS-gate drivers Negative gate bias

PD- 92004

SMPS MOSFET

IRF740A
HEXFET Power MOSFET

Applications Switch Mode Power Supply ( SMPS ) l Uninterruptable Power Supply l High speed power switching
l

VDSS
400V

Rds(on) max
0.55

ID
10A

Benefits Low Gate Charge Qg results in Simple Drive Requirement l Improved Gate, Avalanche and dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche Voltage and Current l Effective Coss specified ( See AN 1001)
l

TO-220AB

GDS

Absolute Maximum Ratings

Parameter
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torqe, 6-32 or M3 screw

Max.
10 6.3 40 125 1.0 30 5.9 -55 to + 150 300 (1.6mm from case ) 10 lbfin (1.1Nm)

Units
A W W/C V V/ns C

Typical SMPS Topologies:

l l

Single transistor Flyback Xfmr. Reset Single Transistor Forward Xfmr. Reset ( Both for US Line Input only )
through are on page 8

Notes

www.irf.com

1
9/14/99

IRF740A
Static @ TJ = 25C (unless otherwise specified)
Parameter Drain-to-Source Breakdown Voltage V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) Gate Threshold Voltage V(BR)DSS IDSS IGSS Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Min. 400 2.0 Typ. 0.48 Max. Units Conditions V VGS = 0V, I D = 250A V/C Reference to 25C, ID = 1mA 0.55 VGS = 10V, ID = 6.0A 4.0 V VDS = VGS, ID = 250A 25 VDS = 400V, VGS = 0V A 250 VDS = 320V, VGS = 0V, TJ = 125C 100 VGS = 30V nA -100 VGS = -30V

Dynamic @ TJ = 25C (unless otherwise specified)

gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Coss Coss Coss eff. Parameter Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance Min. 4.9 Typ. 10 35 24 22 1030 170 7.7 1490 52 61 Max. Units Conditions S VDS = 50V, ID = 6.0A 36 ID = 10A 9.9 nC VDS = 320V 16 VGS = 10V, See Fig. 6 and 13 VDD = 200V ID = 10A ns RG = 10 RD = 19.5,See Fig. 10 VGS = 0V VDS = 25V pF = 1.0MHz, See Fig. 5 VGS = 0V, V DS = 1.0V, = 1.0MHz VGS = 0V, VDS = 320V, = 1.0MHz VGS = 0V, VDS = 0V to 320V

Avalanche Characteristics
Parameter
EAS IAR EAR Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy

Typ.

Max.
630 10 12.5

Units
mJ A mJ

Thermal Resistance
Parameter
RJC RCS RJA Junction-to-Case Case-to-Sink, Flat, Greased Surface Junction-to-Ambient Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time

Typ.
0.50

Max.
1.0 62

Units
C/W

Diode Characteristics
Min. Typ. Max. Units IS
ISM

VSD trr Qrr ton

Conditions D MOSFET symbol 10 showing the A G integral reverse 40 S p-n junction diode. 2.0 V TJ = 25C, IS = 10A, VGS = 0V 240 360 ns TJ = 25C, IF = 10A 1.9 2.9 C di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

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IRF740A
100
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP

100

I D , Drain-to-Source Current (A)

10

I D , Drain-to-Source Current (A)

VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP

10

0.1

4.5V

4.5V
20s PULSE WIDTH TJ = 25 C
1 10 100

0.01 0.1

0.1 0.1

20s PULSE WIDTH TJ = 150 C

1 10 100

VDS , Drain-to-Source Voltage (V)

VDS , Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

Fig 2. Typical Output Characteristics

100

3.0

ID = 10A

RDS(on) , Drain-to-Source On Resistance (Normalized)

I D , Drain-to-Source Current (A)

2.5

10

2.0

TJ = 150 C

1.5

1.0

TJ = 25 C
V DS = 50V 20s PULSE WIDTH 5.0 6.0 7.0 8.0 9.0 10.0

0.5

0.1 4.0

0.0 -60 -40 -20

VGS = 10V
0 20 40 60 80 100 120 140 160

VGS , Gate-to-Source Voltage (V)

TJ , Junction Temperature ( C)

Fig 3. Typical Transfer Characteristics

Fig 4. Normalized On-Resistance Vs. Temperature

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IRF740A
20
100000

ID = 10A VDS = 320V VDS = 200V VDS = 80V

VGS , Gate-to-Source Voltage (V)

10000

VGS = 0V, f = 1 MHZ Ciss = C gs + Cgd , C ds SHORTED Crss = C gd Coss = C ds + C gd

16

C, Capacitance(pF)

1000

Ciss

12

100

Coss

10

Crss

1 1 10 100 1000

0 0 10 20

FOR TEST CIRCUIT SEE FIGURE 13

30 40

VDS, Drain-to-Source Voltage (V)

Q G , Total Gate Charge (nC)

Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage

Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage

100

100

OPERATION IN THIS AREA LIMITED BY RDS(on)

ISD , Reverse Drain Current (A)

10us

10

I D , Drain Current (A)

TJ = 150 C TJ = 25 C
1

100us 10

1ms

0.1 0.2

V GS = 0 V
0.4 0.6 0.8 1.0 1.2 1.4

TC = 25 C TJ = 150 C Single Pulse

10 100

10ms 1000

VSD ,Source-to-Drain Voltage (V)

VDS , Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Forward Voltage

Fig 8. Maximum Safe Operating Area

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IRF740A
10.0

VDS VGS

RD

8.0

D.U.T.
+

RG

I D , Drain Current (A)

-VDD

6.0

10V
Pulse Width 1 s Duty Factor 0.1 %

4.0

Fig 10a. Switching Time Test Circuit

2.0

VDS 90%

0.0 25 50 75 100 125 150

TC , Case Temperature

( C)
10% VGS

Fig 9. Maximum Drain Current Vs. Case Temperature

td(on)

tr

t d(off)

tf

Fig 10b. Switching Time Waveforms

10

Thermal Response (Z thJC )

1 D = 0.50 0.20 0.1 0.10 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) P DM t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1 10

0.01

0.001 0.00001

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRF740A
1 5V

1400

EAS , Single Pulse Avalanche Energy (mJ)

TOP BOTTOM

1200

VDS

D R IV E R

ID 4.5A 6.3A 10A

1000

RG
20V tp

D .U .T
IA S

+ V - DD

800

0 .0 1

600

Fig 12a. Unclamped Inductive Test Circuit

V (B R )D SS tp

400

200

0 25 50 75 100 125 150

Starting TJ , Junction Temperature ( C)

IAS

Fig 12b. Unclamped Inductive Waveforms

QG

Fig 12c. Maximum Avalanche Energy Vs. Drain Current

10 V
QGS VG QGD
V DSav , Avalanche Voltage ( V )
580

560

Charge

540

Fig 13a. Basic Gate Charge Waveform

Current Regulator Same Type as D.U.T.

520

50K 12V .2F .3F

500

D.U.T. VGS
3mA

+ V - DS

480 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0

IAV , Avalanche Current ( A)

IG

ID

Current Sampling Resistors

Fig 13b. Gate Charge Test Circuit

Fig 12d. Typical Drain-to-Source Voltage Vs. Avalanche Current

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IRF740A
Peak Diode Recovery dv/dt Test Circuit
D.U.T

Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer

RG dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test

+ VDD

Driver Gate Drive P.W. Period D=

P.W. Period VGS=10V

D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt

VDD

Re-Applied Voltage Inductor Curent

Body Diode

Forward Drop

Ripple 5%

ISD

* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS

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Transistores IGBTs, caractersticas, aplicaes e circuitos de comando

Ren Pastor Torrico Bascop e Arnaldo Jos Perin
INEP Instituto de Eletrnica de Potncia Departamento de Engenharia Eltrica Centro Tecnolgico UFSC Caixa Postal 5119 88040-970 Florianpolis - SC

1 - ESTRUTURA FSICA E PRINCPIO DE OPERAO DO IGBT

Desde que se desenvolveu o primeiro no fim de 1957, tem surgido grandes progressos no desenvolvimento de dispositivos semicondutores de potncia. At 1970, os tiristores convencionais foram utilizados de maneira exclusiva para o controle da energia eltrica em aplicaes industriais. A partir de 1970, foram desenvolvidos os semicondutores totalmente controlados de potncia (na entrada em conduo e no bloqueio) para sua aplicao no desenvolvimento de conversores estticos de potncia. O IGBT tornou-se comercialmente disponvel na dcada de 80 com a primeira gerao. A evoluo das geraes de cada fabricante ocorre de uma maneira similar como mostrado no exemplo da Fig. 1 [1]. Observando as curvas da Fig. 1, possvel dizer que, com a evoluo, os dispositivos tem possibilitado a diminuio das perdas de conduo devido s cada vezes menores queda de tenso em estado de conduo VCesat. Ao mesmo tempo, tem possibilitado uma comutao cada vez mais rpida, o que diminui as perdas de comutao.
VCEsat [V] 4,5 4 primeira gerao 3,5 3 2,5 2 1,5 1 0,5 0 t f [ s] 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1,0 segunda gerao

terceira gerao quarta gerao

Fig. 1 - Curvas tpicas de evoluo das geraes dos IGBTs.

1.1 CARACTERSTICAS GERAIS Para vencer as limitaes dos transistores bipolares e MOSFET, realizou-se uma integrao de suas vantagens: capacidade de corrente de coletor (caracterstica do transistor bipolar) e controle por tenso aplicado entre gate-emissor (caracterstica do MOSFET de potncia), num nico dispositivo hbrido que denomina-se transistor IGBT (Insulated Gate Bipolar Transistor). Este dispositivo pertence famlia de dispositivos bi-MOS, sendo atualmente o mais avanado em tecnologia disponvel e o mais utilizado comercialmente pelas caractersticas indicadas a seguir [2]: Controle por tenso: a entrada em conduo e o bloqueio do dispositivo so controlados aplicando-se tenso entre gate e emissor. A caracterstica de entrada idntica ao MOSFET de potncia: sua elevada impedncia de entrada denota simplicidade para o circuito de comando, implicando em baixos custos. Baixas perdas de conduo: o canal do IGBT, em estado de conduo, consideravelmente menos resistivo pelo fato de ter-se o substrato P junto ao coletor, responsvel pela injeo dos portadores minoritrios (lacunas) na camada resistiva do canal (N-base). O fluxo de corrente de coletor dado pelos portadores minoritrios. Elevada capacidade de corrente de coletor: pelo fato de apresentar uma caracterstica de sada idntica ao transistor bipolar de potncia, o dispositivo possui uma elevada capacidade de conduo de corrente de coletor (centenas de ampres). Operao em tenses elevadas: com o incremento da espessura das camadas do substrato N-base, foi possvel alcanar tenses de operao acima de 1000V [3], sem ocorrer o incremento da resistncia do canal, fato este que acontece no MOSFET de potncia. No apresenta problemas de segunda avalanche: o dispositivo pode suportar simultaneamente elevadas tenses e correntes de curta durao sem apresentar problemas de destruio pelo fenmeno de segunda avalanche. Operao em Altas freqncias : possvel operar o interruptor at 200kHz em condies de comutao no dissipativa [7]. Em condies de comutao dissipativa o IGBT pode operar at freqncias de 25kHz. Devido s perdas de comutao pela presena da corrente de cauda (que ocorre na transio do estado conduo-bloqueio), a escolha da freqncia de operao do transistor, depender das condies de comutao (Hard Commutation ou Soft Commutation). Na literatura, este dispositivo tambm conhecido como Conductivity Modulated Field-Effect Transistor (COMFET)[5]. Por natureza, os IGBTs so mais rpidos que os transistores bipolares de potncia (BJT) por no apresentarem o problema do tempo de estocagem, porm so menos rpidos que os transistores MOSFETs de potncia.

EMISSOR

GATE

EMISSOR

N+

N+ R st T 2 P-BASE

N+ J1 J2

N+

P-BASE

N-BASE P+

T 1

R mod J3

METAL SiO (Dixido de Silcio) 2

COLETOR

Fig. 2 - Estrutura fsica e circuito equivalente do IGBT canal N.

1.2 ESTRUTURA FSICA A estrutura fsica de um transistor IGBT canal N mostrada na Fig. 2 e consiste basicamente de quatro camadas: substratos P+, N-base, P-base e N+. A sua construo baseada no semicondutor de silcio (Si). Para mudar suas caractersticas eltricas e torn-lo um melhor condutor, realizado o processo de dopagem, que consiste na adio, ao semicondutor, de elementos qumicos em pequena proporo. A estrutura constituda de camadas de substratos que so chamados P e N. O substrato tipo P obtido dopando o silcio com elementos qumicos trivalentes (trs eltrons na camada externa de valncia), que podem ser: Boro, Glio ou ndio. Por outro lado, o substrato tipo N obtido dopando o silcio com elementos qumicos pentavalentes (cinco eltrons na camada externa de valncia), que podem ser: Fsforo ou Antimnio [6]. No IGBT, a camada P+ um substrato com forte dopagem de Boro (pouco resistiva) e a camada N-base um substrato com dopagem de Fsforo (altamente resistiva). A formao da juno entre estas duas camadas permite a injeo de portadores minoritrios no canal quando o IGBT est no estado de conduo, reduzindo-se desta maneira de modo considervel a queda de tenso e, por conseqncia, a potncia dissipada internamente, neste estado [2]. Este processo tambm conhecido como modulao de condutividade. A modulao de condutividade no caso de um MOSFET no favorvel, pois o canal constitudo por elementos altamente resistivos (substrato tipo N) e a maior parte das suas perdas ocorre nesta regio em estado de conduo, tipicamente 70% num dispositivo de 500V [8]. A presena das quatro camadas gera um tiristor parasita, composto pelos transistores bipolares PNP e NPN, como mostram a Fig. 2 e a Fig. 3. A operao deste tiristor altamente indesejvel, pois provoca a perda do controle da corrente de coletor e, como conseqncia, a sua respectiva destruio por aquecimento. Para evitar sua destruio, a resistncia Rst do substrato P-base (Fig. 1) deve ser bem baixa, de maneira a reduzir a queda de tenso valores inferiores a 0,6 V (o transistor parasita NPN no deve ser polarizado). O componente MOSFET canal N do circuito equivalente, tem a funo de controlar a corrente de base do transistor PNP durante sua operao. Na realidade, no IGBT a corrente de coletor basicamente controlada atravs deste componente, dado pelos substratos N-base, P-base e N+. 1.3 PRINCPIO DE OPERAO Como o IGBT resulta da combinao de uma estrutura MOS e de uma estrutura bipolar, sua anlise difere de ambos os dispositivos de potncia. Para compreender sua operao, necessrio o conhecimento da fsica do transistor MOSFET e do transistor bipolar. Nesta seo descrito o princpio de operao do dispositivo e, para tal finalidade, no considerada a situao da operao do tiristor parasita que provoca perda de controle da corrente de coletor.
Coletor
Tiristor R mod T1

iC
PNP
(Gate) G

(Coletor) C

iMOS

ibasePNP
T2

Gate

NPN R st

(Emissor) E

Emissor Fig. 3 - Circuito equivalente do IGBT Canal N e o seu smbolo.

1.3.1 Capacidade de bloqueio reverso O IGBT no entra em conduo (fluxo de corrente de coletor) quando uma tenso negativa entre coletor-emissor (VCE) aplicada, apesar de ter-se uma tenso positiva entre gate-emissor (VGE) acima do valor de limiar (threshold voltage), pelo simples fato da juno J3 (formada entre as camadas P+ e N-base) estar polarizada reversamente. A polarizao reversa da juno provoca a formao de uma camada de depleo na regio, garantindo desta maneira a capacidade de bloqueio reverso do dispositivo. Esta caracterstica mostrada atravs da Fig. 3. importante deixar claro que a tenso de ruptura reversa, depende essencialmente da espessura da camada resistiva N-base. As duas tecnologias modernas existentes atualmente, PT (Punch-Through) e NPT (Non-Punch-Through), relativas estrutura do

dispositivo, apresentam caractersticas de sada diferentes [9].

IC regio ativa

incremento da tenso de gate

V CER caracterstica reversa I CR caracterstica direta

VCE

Fig. 4 - Caracterstica de sada do IGBT (genrico)

1.3.2 Capacidade de conduo direta Para que o IGBT encontre-se em estado de conduo direta (forward conduction), necessrio aplicar simultaneamente tenses positivas entre gate-emissor (VGE) e coletor-emissor (VCE). Aplicando-se estas duas tenses, vence-se a depleo da juno J2 entre as camadas P-base N-base e a depleo da juno J3 entre as camadas P+ N-base (ambas as junes devem ser polarizadas diretamente). A tenso gate-emissor positiva deve ser suficientemente elevada, acima da tenso de limiar, para que a resistncia do canal MOS seja pequena durante o fluxo de corrente de coletor. A resistncia no canal do IGBT baixa devido modulao de condutividade, proporcionada pela injeo de portadores minoritrios (lacunas) desde a regio P+ dentro da regio N-base altamente resistiva. A densidade de portadores minoritrios injetados na regio N-base tipicamente de 100 a 1.000 vezes maior que o nvel de portadores da camada N-base do MOSFET de potncia. Por este motivo reduzida drasticamente a resistncia do canal do IGBT em relao resistncia do canal do MOSFET de potncia. Esta caracterstica permite operar o IGBT com elevadas densidades de corrente durante o estado de conduo. Como a camada N-base do IGBT deixa de ser altamente resistiva com a injeo de portadores minoritrios, para aumentar a capacidade de operao com tenses acima de 1.000V suficiente aumentar a espessura desta camada. 1.3.3 Capacidade de bloqueio direto O bloqueio do IGBT, quando encontra-se em estado de conduo, alcanado reduzindo-se a tenso entre gate e emissor abaixo do valor de limiar (VGEth Gate-Emitter Threshold Voltage). A tenso abaixo do valor de limiar alcanada curto-circuitando o terminal gate ao terminal emissor com um resistor de baixo valor de resistncia. Com esta condio, a juno J2 polarizada reversamente bloqueando o fluxo de corrente atravs do canal MOS do dispositivo. O bloqueio realizado em condies de tenso coletor-emissor positiva. Observando o circuito equivalente do IGBT mostrado na Fig. 3, o bloqueio da corrente de coletor do IGBT realizado atravs do MOSFET que bloqueia a corrente de base do transistor PNP.
VGE iC vCE vCE iC aumento de R GE aumento de R GE cauda t t1 t

iC Ic

Fig. 5 - Caractersticas de bloqueio e corrente de coletor com a variao de RGE durante o bloqueio

A caracterstica de sada do IGBT controlada atravs da tenso aplicada entre gate-emissor VGE. Para realizar a transio do estado de conduo ao estado de bloqueio, o gate, que inicialmente tem um valor positivo de tenso, ligado ao emissor por um circuito externo, provocando-se a descarga da capacitncia intrnseca de entrada dada pelo paralelo das capacitncias entre coletor-gate e gate-emissor. A descida abrupta da tenso entre gate e emissor at um valor abaixo do limiar permite, como conseqncia, um decrescimento abrupto da corrente de coletor at um certo valor. Como resultado, tem-se a sbita reduo zero da corrente do canal MOS devido aos eltrons. A magnitude da queda abrupta da corrente de coletor - IC - no instante t1 (Fig. 5), grande devido ao baixo ganho de corrente (PNP), do transistor PNP do circuito equivalente, que situa-se na faixa de 0,4 a 0,5. Isto implica que a corrente de base do transistor PNP, que a mesma corrente que flui pelo canal MOS igual a: ibasePNP = iMOS = iC/(1+PNP). Aps cair abruptamente, a corrente de coletor decresce continuamente de maneira mais lenta devido alta densidade de portadores minoritrios injetados na regio N-base. Tais portadores necessitam de tempo para sua recombinao, o que resulta numa corrente de coletor residual indesejada que somente causa perda de energia durante a comutao de bloqueio do dispositivo. Esta corrente residual conhecida na literatura como corrente de cauda (tail current) [7]. A queda abrupta da corrente de coletor (Ic) causa variaes de corrente de coletor (dic/dt) de elevado valor, que devido presena de indutncias parasitas do layout e do prprio dispositivo, geram elevadas tenses sobre o interruptor durante o bloqueio, muitas vezes podendo provocar sua destruio. Esta queda abrupta pode ser alterada controlando-se a tenso entre gate-emissor durante o bloqueio. Isto alcanado com a descarga lenta da capacitncia de entrada atravs de uma resistncia adequada ligada entre gate e emissor durante o bloqueio. Na Fig. 5 mostrada a

diminuio da corrente de coletor (dic/dt) com o incremento do valor do resistor conectado entre gate e emissor durante o bloqueio. importante indicar que com o incremento do valor do resistor conectado entre gate e emissor (RGE) durante o bloqueio, o efeito da reduo da corrente de cauda, corrente indesejada, nfima [5] ( Fig. 5).

2 - CIRCUITOS DE COMANDO
Pelo fato de apresentar uma impedncia de entrada elevada, o IGBT controlado por um sinal de tenso adequado aplicado entre gate e emissor VGE, requerendo baixa potncia da fonte de tenso do circuito de comando de gate. Uma vantagem do IGBT em relao ao MOSFET, para uma mesma capacidade de corrente nominal, a baixa capacitncia de entrada determinando um baixo consumo de energia [10]. O circuito de comando de gate deve permitir uma operao adequada do interruptor IGBT nos estados de conduo, comutao na entrada em conduo e no bloqueio, proporcionando tambm o isolamento entre o circuito de controle e o circuito de potncia, evitando sua possvel destruio devido aos diferentes potenciais de tenso de coletor e emissor. Com um circuito bem projetado as perdas de conduo e comutao so mnimas com moderados esforos de tenso e corrente, protegendo o dispositivo da destruio. 2.1 PERDAS E ESFOROS RELACIONADOS AO COMANDO 2.1.1 - Comutao na Entrada em Conduo Para analisar as perdas e esforos e relacion-las ao circuito de comando, considerado o circuito de potncia em meia ponte (half-bridge) com carga indutiva mostrado na Fig. 6. Este circuito apresenta dois interruptores no brao operando complementarmente com comutao dissipativa. Neste tipo de configurao os dispositivos suportam os maiores esforos de sobretenso e sobrecorrente, cujos fenmenos sero explicados a seguir. Aplicando um pulso positivo de tenso entre os terminais gate-emissor VGE de valor acima do limiar (5V), o IGBT entra em conduo. Para minimizar a perda de comutao na entrada em conduo (turn-on) o tempo de subida (rise time) da corrente de coletor (iC) deve ser o menor possvel. Para alcanar esta caracterstica, o tempo de subida da tenso entre os terminais gate-emissor VGE deve ser tambm o menor possvel, j que este tempo reflete-se no tempo de subida da corrente de coletor. Isto pode ser conseguido carregando-se rapidamente a capacitncia de entrada Cies do dispositivo (que constitui-se das capacitncias gate-emissor CGE e gate-coletor CGC, ou capacitncia Miller) por meio de uma fonte de tenso de baixa impedncia durante a aplicao do pulso. Uma elevada tenso de gate ajuda a transferir rapidamente a carga necessria, vencendo os efeitos das resistncias e indutncias parasitas do circuito de comando de gate.
VG1
0

RG(on) RG(off)

IGBT1
D1

Ls1

E1

tm

t m= tempo morto
RG(on) RG(off)

VG2
0

IGBT2
D2

Carga Indutiva E2 L s2 brao

Fig. 6 - Circuito em meia ponte para a anlise dos tempos de comutao.

Por outro lado, diminuindo-se o tempo de subida da corrente de coletor, provoca-se um crescimento abrupto da mesma, aumentando a magnitude da corrente de recuperao reversa do diodo em antiparalelo com o IGBT complementar. Alm disso, provoca elevadas interferncias de rdio freqncia (RFI) e eletromagnticas (EMI), bem como sobretenso no interruptor complementar devido presena de indutncias parasitas (Ls1 e Ls2) que existem no circuito de potncia e que podem ser diminudas atravs de um layout apropriado (v=Ls.dic/dt). Aconselha-se portanto, a colocao de uma resistncia RG(on) de baixo valor em srie com o gate do dispositivo, como mostrado na Fig. 5. Deste modo, possvel controlar o tempo de subida da corrente de coletor do IGBT, ou seja, o valor de diC/dt. Observa-se que deve existir um compromisso de otimizao de perdas e esforos de sobretenso, pois ambas grandezas se relacionam. No caso de persistir a sobretenso, pode-se limit-la em um valor dentro da rea RBSOA, com a utilizao de um circuito externo (circuito snubber, circuito grampeador, etc.). A resistncia de gate, portanto, apresenta importncia fundamental no rendimento e custo do conversor. Para o caso de cargas resistivas, quando o sinal de tenso gate-emissor sobe rapidamente na entrada em conduo, a tenso coletor-emissor VCE desce rapidamente. Esta descida rpida provoca uma dvCE/dt que injeta correntes dentro do circuito de comando atravs da capacitncia coletor-gate CCG. Estas derivadas de tenso podem causar oscilaes de tenso de gate, permitindo o aumento de perdas na entrada em conduo. A pequena resistncia RG(on) indicada anteriormente em srie com o gate do dispositivo, tambm permite reduzir estas derivadas de tenso, embora as indutncias parasitas do circuito de comando possam ser minimizadas colocando-se o circuito de comando o mais prximo possvel do dispositivo. Quando a comutao finaliza, a tenso sobre o dispositivo, tenso coletor-emissor, encontra-se num valor muito baixo (tenso de saturao) e este valor depende da tenso gate-emissor VGE. 2.1.2 - Em Estado de Conduo O valor da tenso de saturao coletor-emissor VCEsat deve ser o menor possvel, desta maneira minimiza-se as perdas em estado de conduo, sendo portanto conveniente aplicar uma tenso gate-emissor elevada (na faixa de 12V a

15V). Na prtica, muitos dos fabricantes de IGBTs recomendam aplicar-se uma tenso de 15V e uma resistncia RG(on) em srie com o gate menor que 50 [11]. O valor da resistncia em srie com o gate normalmente dimensionado conforme as correntes mximas que podem suportar os dispositivos do circuito de comando (transistores de sinal, portas lgicas, etc.) e analisando os efeitos de diC/dt e dvCE/dt. Quando a tenso de saturao bem baixa devida aplicao de uma tenso elevada entre gate-emissor VGE, a magnitude da corrente de cauda maior. Portanto, existe uma dependncia entre estes dois parmetros. 2.1.3 - Comutao no Bloqueio Durante a comutao de bloqueio os IGBTs, apesar do tempo de retardo, no apresentam tempos de estocagem como normalmente acontece com os transistores bipolares. O tempo de descida da corrente de coletor do IGBT compem-se basicamente do tempo de descida da corrente de base do transistor bipolar pnp (circuito equivalente da Fig. 3, corrente que flui pelo canal MOS), controlada por meio do gate e do tempo de descida da corrente de cauda (devido parcela de corrente de coletor do mesmo transistor). A corrente de cauda provocada pela recombinao de portadores minoritrios no transistor pnp do circuito equivalente, no podendo ser reduzida por meios externos (atravs do circuito de comando). As perdas de comutao de bloqueio em um IGBT com comutao dissipativa, no mudam significativamente atravs do circuito de comando de gate variando a resistncia RG(off), j que a maior perda de potncia devida parcela de corrente de cauda. No IGBT no necessrio um sinal de tenso negativo entre os terminais gate-emissor VGE; sua aplicao depender do tipo de topologia e dos efeitos que provoca (diC/dt, dvCE/dt) sobre os dispositivos. Uma resistncia de bloqueio RG(off), de baixo valor, entre gate-emissor suficiente para proporcionar um caminho de descarga da capacitncia gateemissor, permitindo o bloqueio do IGBT. Para operar o IGBT em alta freqncia (acima de 10kHz) num brao (halfbridge), a presena de um pulso negativo de tenso gate-emissor VGE importante durante o bloqueio para reduzir os efeitos de dvCE/dt que injetam correntes atravs do capacitor gate-coletor CGC no capacitor gate-emissor CGE, provocando picos de tenso gate-emissor acima do valor de limiar. Este picos de tenso podem provocar uma conduo indevida do dispositivo complementar. Com relao ao tempo de subida (rise time) da tenso coletor-emissor VCE durante o bloqueio, quanto menor for este tempo, maiores sero os valores de dvCE/dt entre os terminais coletor-emissor do dispositivo. Uma das maneiras de reduzir os efeitos devido s elevadas derivadas de tenso, dimensionando adequadamente a resistncia RG(off) em srie com o gate. Um outro problema que pode provocar um elevado dvCE/dt no bloqueio o fenmeno de latch-up - entrada em conduo do tiristor parasita devido ao fluxo de corrente capacitivo interno [10]. A presena da resistncia de bloqueio de gate RG(off) durante a comutao de bloqueio, tem uma influncia direta sobre o tempo de retardo do bloqueio do IGBT; este fenmeno ilustrado na Fig. 7.a e Fig. 7.b para dois valores de resistncias diferentes. Como pode-se observar, quanto maior for o valor desta resistncia, maior ser o tempo de retardo.
VCE

IC 0 V GE R G(off) = 0 VGE(off) = -15V

Fig. 7.a - Formas de onda de: tenso coletor-emissor, tenso gate-emissor e corrente de coletor. Mdulo IRGTA090F06, testado em: 380V, 100A; Ls = 100nH. VCE: 100V/div, IC: 50A/div, VGE: 10V/div, tempo: 200ns/div [10].

VCE

IC 0 V GE R G(off) = 33 VGE(off) = -15V

A tenso negativa de gate durante o bloqueio reduz o tempo de retardo de bloqueio, pois permite uma rpida descarga da capacitncia de entrada do IGBT. 2.1.4 - Em Estado Bloqueado Como j foi dito anteriormente, durante a comutao de bloqueio e estado bloqueado, suficiente manter conectado o terminal de gate ao terminal de emissor atravs de uma resistncia de bloqueio RG(off) de baixo valor. Porm, no caso dos interruptores estarem em um brao de um conversor e atuando de modo complementar, importante aplicar uma

Fig. 7.b - Formas de onda de: tenso coletor-emissor, tenso gate-emissor e corrente de coletor. Mdulo IRGTA090F06, testado em: 380V, 100A; Ls = 100nH. VCE: 100V/div, IC: 50A/div, VGE: 10V/div, tempo: 200ns/div [10].

tenso negativa durante todo o intervalo de tempo que se quer manter o IGBT bloqueado, para evitar que sinais esprios de tenso positiva provoquem a entrada em conduo indevida. No caso de um conversor em meia ponte (Fig. 6) os sinais esprios de tenso gate-emissor podem provocar um curto-circuito de brao, destruindo os IGBTs. Para obter caractersticas de operao favorveis, possvel aplicar-se uma tenso negativa na faixa de 5V a 15V. Segundo [10] recomendado aplicar-se uma tenso negativa de 5V e uma resistncia RG(off) srie de gate de bloqueio menor que 47. O valor do pulso negativo pode ser maior que 5V, sem restries quanto aos nveis da tenso e potncia do conversor. Em algumas aplicaes, normalmente costuma-se utilizar uma resistncia nica para ambos os estados de operao do dispositivo. Tambm existem critrios de utilizao de resistncias com valores diferentes, sendo uma para cada estado de operao, ou combinao em paralelo de ambas utilizando diodos de sinal em srie. Toda escolha depende do critrio do projetista do circuito de comando. Convm lembrar que durante a operao do dispositivo, podem acontecer transitrios destrutivos de tenso entre os terminais gate-emissor. Para proteger o dispositivo de tais condies indesejveis, devem ser utilizados diodos zener diretamente conectados entre os terminais gate-emissor, tanto para o pulso positivo como para o pulso negativo. 2.2 NECESSIDADE DE CIRCUITOS DE COMANDO ISOLADOS Em circuitos de potncia em ponte, os IGBTs inferiores tm os emissores conectados a um ponto comum considerado normalmente como n de referncia, onde o potencial de tenso relativo nulo, portanto, para estes interruptores pode no ser necessrio utilizar circuitos de comando de gate isolados. Quando no utilizado isolamento existe o perigo de destruio do circuito de controle devido ao potencial de tenso de coletor do IGBT por destruio de algum dispositivo do circuito de comando conectado ao coletor do IGBT (caso de circuitos com proteo de curtocircuito por deteco de dessaturao). Por este motivo, em conversores com circuitos de controle complexos e com circuitos de proteo, recomenda-se utilizar circuitos de comando de gate isolados para todos os interruptores de potncia. Os IGBTs superiores, porm, tm seus emissores conectados a diferentes potenciais de tenso em relao ao potencial de referncia, o que torna necessrio utilizar circuitos de comando de gate isolados. Para realizar o isolamento podem ser utilizados transformadores de pulso, optoacopladores e circuitos de comando de gate integrados dedicados. O projeto do circuito de comando de gate isolado deve levar em considerao o custo, imunidade a rudos, complexidade, rapidez de resposta, etc.. 2.2.1 - Transformadores de Pulso O transformador de pulso um dispositivo magntico do circuito de comando de gate que opera em elevada freqncia e que proporciona isolamento galvnico entre os circuitos de potncia e circuito de controle, com o emprego de um enrolamento primrio e um ou mais enrolamentos secundrios. Este dispositivo pode transmitir pulsos de tenso do primrio para o secundrio sem distoro e com atrasos quase desprezveis. Quando aplicado um transformador de pulso em um circuito de comando, no se faz necessrio utilizar uma fonte de tenso isolada no lado do secundrio, podendo, ainda, operar favoravelmente em freqncias de comutao elevadas (acima de 100kHz). Outra vantagem de sua aplicao, a imunidade interferncias por rudo, no apresentando tambm, problemas por elevados valores de dvCE/dt. Para que o transformador apresente um desempenho adequado no circuito de comando, devem ser levados em considerao os seguintes tpicos: Tenso de isolamento do transformador (> 4kV); Mnima indutncia de disperso; Freqncia de operao; Dimensionamento adequado do ncleo e nmero de espiras do primrio e secundrio; Capacidade de transferncia de energia para dispensar o uso de fonte auxiliar no lado secundrio; Limitao da variao da razo cclica prevenindo a saturao do ncleo (desmagnetizao do ncleo). Normalmente quando aplicado o mtodo comum de transmisso de pulsos, ao primrio no devem ser aplicados pulsos com razo cclica acima de 50% por motivo de saturao do ncleo. Neste mtodo, a razo cclica dos pulsos podem variar desde valores prximos a zero at 0,5. Para conseguir a transmisso de pulsos com razo cclica acima de 50%, tcnicas convenientes de desmagnetizao do ncleo devem ser utilizadas, onde a razo cclica dos pulsos pode variar de 0 a 100%. 2.2.2 - Optoacopladores Os optoacopladores so dispositivos do circuito de comando de gate que proporcionam isolamento eltrico entre os circuitos de controle e potncia. Possuem a vantagem de transmitir pulsos com freqncia varivel e com qualquer razo cclica, sem apresentar problemas de saturao como no caso do transformador de pulso. Porm, apresentam desvantagens quando comparados a estes: necessitam uma fonte auxiliar isolada na sua sada, circuitos para amplificar a corrente de sada (que da ordem de 20mA), apresentam pouca imunidade a interferncias por rudos, bem como problemas devido elevados dvCE/dt (estes problemas esto sendo superados com as ltimas geraes de optoacopladores). Em relao freqncia de operao, os mesmos limitam-se a, no mximo, 100 kHz. Alguns detalhes devem ser observados para otimizar o uso de optoacopladores: Devem apresentar imunidade rudos e derivadas de tenso; Os sensores de sinal devem ser fotodiodos (os fototransistores so lentos); As capacitncias entre a entrada e a sada devem ser pequenas;

 Aplicar aproximadamente a corrente nominal na entrada para a polarizao do fotodiodo; Optar por dispositivos com elevada tenso de isolamento entre a entrada e a sada (> 4kV); Levar em considerao possveis recomendaes adicionais do fabricante indicadas no catlogo, como por exemplo: capacitores de desacoplamento, distncia das trilhas de circuito impresso, etc. 2.2.3 - Circuitos de Comando Integrados Dedicados Atualmente muitos fabricantes de IGBTs tem desenvolvido circuitos de comando de gate integrados dedicados para seus dispositivos. Existem circuitos com isolamento e sem isolamento. Alguns destes circuitos necessitam de uma fonte de tenso isolada na sada. Os circuitos com isolamento utilizam fotosensores de sinal ou transformadores de pulso para transmitir os pulsos da entrada para a sada (circuitos de comando da Mitsubishi, Fuji, Semikron, etc.) e, os circuitos sem isolamento utilizam a tcnica do Bootstrap (circuitos da International Rectifier) que normalmente so utilizados em conversores de baixa potncia (< 2kW ) e baixa tenso (< 600V). Alguns circuitos ainda podem apresentar proteo contra curto-circuito. Mais adiante sero mostrados alguns deles. 2.3 EXEMPLOS DE CIRCUITOS DE COMANDO ISOLADOS O circuito de potncia (chopper) mostrado na Fig. 8 foi utilizado para testar os circuitos de comando para um nico transistor. O tiristor neste circuito utilizado para simular um curto-circuito na carga. Por outro lado, o circuito de potncia em meia ponte da Fig. 9, foi utilizado para testar os circuitos de comando integrados para um brao de interruptores.
Tiristor para simular curto-circuito R3 C3 C G E IRGPH40F SCR R1 D1 100V C2 D2 R2

E2

C1

Fig. 8 - Circuito a IGBT para teste dos circuitos de comando de gate.

O IGBT do conversor da Fig. 8 apresenta as seguintes especificaes: VCE = 1200V, VCEsat = 3V @ IC = 17A, TJ = 150oC. VGE = +/- 20V, ICN = 17A @ TC = 100oC, ICM = 58A,
C1 G1 E1 C2 G2 E2 D1 R1=10 C1

100V

R2

C2

C3

MDULO : CM15TF - 12E

Fig. 9 - Circuito em meia ponte para teste dos circuitos de comando de gate.

Por outro lado, o mdulo IGBT em meia ponte do conversor da Fig. 9 apresenta as seguintes especificaes: VCE = 600V, VCEsat = 2,7V @ IC = 15A, TJ = 150oC, VGE = +/- 20V, ICN = 15A @ TJ = 25oC, ICM = 30A @ TJ = 25oC, Um circuito de comando de gate (isolado ou no) considerado adequado para acionar um IGBT, quando tm as seguintes caractersticas: mantm aproximadamente igual a razo cclica do pulso da tenso de entrada ao circuito Vcon no pulso da tenso positiva na sada do circuito VGE; o pulso da tenso de sada no sofre distoro em relao ao pulso da tenso de entrada; capaz de aplicar nveis adequados de tenso gate-emissor e corrente de gate. Os pulsos de tenso podem apresentar atrasos na subida e na descida como mostrado na Fig. 10, porm, as magnitudes de tais atrasos devem ser aproximadamente iguais {td(on) td(off) }, para manter quase inalterado o valor da razo cclica. 2.3.1 Circuitos de comando isolados por transformador de pulso Estes circuitos so capazes de aplicar pulsos de tenso gate-emissor positivos de 15V e negativos de 5V. Dois circuitos no realizam proteo de curto-circuito do IGBT mas outros dois circuitos realizam proteo de curto-circuito do IGBT por deteco de dessaturao atravs da tenso coletor-emissor VCE.

v con
50% 50% 50% 50% 0 50% 0

v GE

t
t d(on) t d(off)

Fig. 10 - Pulsos de tenso de entrada e de sada de um circuito de comando.

CIRCUITO A1 :
Vcc1 R1 vcon
15V

Z1 Tr

D1 R5

R6 Z5 R7

IGpk

G V GE

C1 t vcon R3

R2

Z2 R4 Q1

Q2 Z3

D3 C2

D2 Z4

A seguir dada uma metodologia para determinar algumas grandezas importantes para o dimensionamento do circuito de comando, tais como: corrente de pico de gate para entrada em conduo do IGBT, energia necessria para garantir a polarizao do IGBT, etc. [11]. A corrente de pico (Igpk) fornecida pelo circuito de comando para carregar a capacitncia de entrada (Cies) do IGBT durante a entrada em conduo, que limitada pela resistncia de gate, pode ser calculada de maneira aproximada utilizando-se a seguinte equao:
I Gpk VGE (on ) VGE ( off ) RG

Fig. 11 - Circuito de comando de gate isolado com transformador de pulso e sem proteo de curto-circuito para 0 < D 0,5.

(1)

Onde: VGE(on) : tenso positiva gate-emissor; VGE(off) : tenso negativa gate-emissor; RG : resistncia de gate. No circuito de comando da Fig. 11, a resistncia R6 a resistncia de gate (RG). Tomando os seguintes valores de tenses de gate-emissor e a resistncia de gate: VGE(on) = 15V VGE(off) = -5V RG = R6 = 27 e substituindo na Eq. 1, tem-se o valor da corrente de pico.
I Gpk 15 ( 5) = 0,74A 27

A energia absorvida pelo IGBT do circuito de comando para a entrada em conduo, pode ser determinada atravs da seguinte equao: (2) E IGBT ( on ) = Q V Onde: Q : Variao de carga da capacitncia de entrada [Cies]; V : Variao da tenso gate-emissor [V]. Estas grandezas podem ser obtidas a partir da caracterstica de carga de gate mostrada no catlogo do dispositivo (IGBT). Para ter maiores detalhes ver a literatura [12]. No circuito da Fig. 8 utilizou-se o IGBT da International Rectifier ( IRGPH40F ) como dispositivo de teste. Da caracterstica de carga de gate mostrada no catlogo foram obtidos os seguintes dados. Q [50 - (-10)] = 60 C V [15-(-5)] = 20 V importante esclarecer que na figura de caracterstica de carga de gate deste dispositivo, no mostrada a curva de carga para a tenso negativa gate-emissor, que necessria para o clculo da energia. Para solucionar esta situao foi realizada uma interpolao aproximada e determinada a carga para tenso negativa. Substituindo os valores obtidos da curva na Eq. 2, a energia igual a: EIGBT(on) = 1,2 J A potncia da fonte de tenso do circuito de comando absorvida pelo IGBT durante a entrada em conduo, que dissipada no resistor de gate (R6), pode ser determinada com a seguinte equao: (3) PIGBT(on) = E IGBT(on ) f S

Onde: fS : Freqncia de comutao do IGBT Para as freqncias de comutao de 10kHz e 50kHz as potncias so iguais a 12mW e 60mW. A energia necessria para bloquear o IGBT (energia para descarregar a capacitncia de entrada) igual energia necessria para a entrada em conduo (energia para carregar a capacitncia de entrada). Portanto, EIGBT(on) = EIGBT(off). Em um perodo de comutao, a potncia fornecida ao IGBT pela fonte de tenso (VCC1) do circuito de comando, dissipada no resistor de gate sem considerar as perdas devido aos outros componentes do circuito de comando, determinada pela seguinte equao: (4) PVcc1 = 2 E IGBT( on ) f S As perdas provocadas pelos outros componentes do circuito de comando, podem ser determinadas com simplicidade. Por exemplo, nos resistores so conhecidos os valores das resistncias e as tenses sobre eles e nos diodos zener as correntes de polarizao e suas tenses de operao indicadas no catlogo. A seguir so explicados alguns detalhes para dimensionar os componentes do circuito da Fig. 8. Capacitor C1: um capacitor cermico que permite uma rpida entrada em conduo e bloqueio do transistor Q1, que opera na regio de saturao. O valor de sua capacitncia pode ser escolhida entre 3,3nF para uma freqncia de comutao de 10kHz a 680pF para uma freqncia de comutao de 50kHz. Este capacitor no deve provocar uma distoro do sinal de comando gerado pelo circuito de controle; portanto, conforme este critrio deve ser escolhido o seu valor. Capacitor C2: um capacitor eletroltico que armazena energia durante a transmisso do pulso de tenso atravs do transformador de pulso. A tenso sobre ele grampeada no valor da tenso de operao do zener Z3. Sua energia deve ser suficiente para garantir a descarga da capacitncia de entrada do IGBT. Este capacitor comporta-se como uma fonte de tenso negativa durante todo o bloqueio do dispositivo (IGBT). O valor de sua capacitncia pode ser determinada utilizando-se a seguinte equao:
C2 > 2 E IGBT( on ) VZ3
2

(5)

Para evitar sua descarga pela presena de outros dispositivos no circuito de comando e garantir o bloqueio do IGBT, deve ser escolhido um capacitor com capacitncia maior que 10F / 25V. Diodo D1: um diodo de sinal utilizado simplesmente para polarizar o transistor de sinal Q2. A operao do transistor como segue: quando o diodo conduz, o transistor bloqueado e quando o diodo bloqueado, o transistor conduz. Diodos D2 e D3: so diodos de sinal colocados em srie com as resistncias R5 e R7 para evitar perdas e descarga da energia do capacitor C2 durante o estado bloqueado do IGBT. Resistor R1: utilizado para limitar a corrente de curto-circuito da fonte de tenso VCC1 no caso de eventual destruio do transistor Q1. O valor no deve ser elevado, pois, pode provocar limitao do pulso de corrente de gate durante a entrada em conduo do IGBT. Na prtica recomenda-se escolher de 10 a 27. Resistor R2 : utilizado para desmagnetizar a indutncia de disperso do transformador de pulso e amortecer oscilaes. O valor pode ser escolhido de 1k a 2k. Resistor R3: limita a corrente de base do transistor de sinal Q1. Ele deve ser dimensionado para permitir a operao do transistor na regio de saturao. O valor de sua resistncia pode ser determinada com o conhecimento da corrente do secundrio do transformador aps o IGBT ter entrado em conduo e que circula atravs do paralelo das resistncias de R6 + R7 com R4, que aproximadamente a mesma corrente que circula atravs do coletor do transistor Q1, quando a relao de transformao do transformador de pulso unitria. O excesso de corrente de base neste transistor faz com que ele fique muito saturado aumentando o tempo de estocagem, tornando lento o seu bloqueio. Na prtica pode-se utilizar a eq. 7.6 para o dimensionamento aproximado de R3.
R3 Vcon 0,03 I Gpk

(6)

Resistor R4 : limita a corrente de base do transistor de sinal Q2. O valor pode ser escolhido entre 1k a 2k. Resistor R5: o valor de sua resistncia pode ser determinada com o conhecimento da corrente de polarizao do zener Z3 e a energia no capacitor C2 . Resistor R6: o resistor de gate (RG) que utilizado para controlar dic/dt e dvCE/dt sobre o IGBT. Por outro lado, limita a corrente atravs dos dispositivos do circuito de comando de gate. O valor de sua resistncia deve ser escolhido analisando os esforos de tenso e da corrente do IGBT. Para o circuito da Fig. 8 foi escolhido uma resistncia de gate de 27 para o estado de conduo, que a mesma utilizada para o estado de bloqueio [RG(on) = RG(off)]. Resistor R7: permite a descarga da capacitncia gate-emissor CGE do IGBT, quando na ausncia do sinal de comando e/ou destruio do transistor Q2 aplicada abruptamente uma tenso entre coletor-emissor VCE. O sbito crescimento da tenso provoca uma derivada que induz uma corrente na capacitncia gate-emissor CGE atravs da capacitncia coletor-gate e, como conseqncia, a tenso gate-emissor pode superar o valor de limiar permitindo a entrada em conduo do IGBT. Por este motivo, sua aplicao recomendada principalmente quando o circuito de comando for utilizado em um brao, para evitar problemas de curto-circuito. O valor desta resistncia pode ser escolhida de 470 a 2k. Os diodos zener conectados entre gate e emissor, somente protegem o gate para tenses gate-

emissor acima de seu valor de operao. Transistores Q1 e Q2: devem ser dimensionados com o prvio conhecimento da corrente de pico de coletor e mxima tenso coletor-emissor. Transformador de pulso Tr: o transformador pode ser projetado utilizando-se as equaes dadas a seguir [13]:
i ef I Gpk Ae Aw
Np
Sf

D max [A] 3 Vcc1 D max i ef 10 4 [cm4] K p K w J B f s

(7) (8) (9) (10)

D max Vcc1 10 4 [espiras] A e B f s

i ef J

[cm2]

Onde: Ae : rea da seo transversal do ncleo [cm2]; Aw : rea da janela do ncleo [cm2]; B : Excurso do fluxo magntico [T]; Dmax : Razo cclica mxima; fs : Freqncia de comutao [Hz]; ief : Corrente eficaz no primrio do transformador [A]; J : Densidade de corrente [A/cm2]; Kp : Fator de utilizao do primrio; Kw : Fator de utilizao da janela; NP : Nmero de espiras do primrio; Sf : Seo do fio [cm2]. Nota: estas equaes so vlidas para um ncleo de ferrite do tipo EE. Zener Z1 e Z2: so utilizados para desmagnetizar o transformador de pulso. O zener Z1 limita a tenso coletoremissor reversa do transistor Q1 em seu valor de operao (quando a relao de transformao unitria). Este zener pode ser dimensionado com uma tenso de operao de 1,5 vezes a tenso no secundrio do transformador de pulso. Quanto maior a tenso de operao de Z1, maior poder ser a razo cclica do pulso de tenso. Por outro lado, o zener Z2 pode ser dimensionado com valor de tenso igual tenso do secundrio do transformador de pulso. O zener Z2, tambm pode ser substitudo por um diodo de sinal rpido. Zener Z4 e Z5: so utilizados para evitar a destruio do IGBT pela presena de sobretenses entre gate e emissor, para pulsos de tenso positivos e negativos. Os valores de tenso de operao devem ser menores que a tenso de destruio gate-emissor indicados pelos fabricantes ( 20V). Os transformadores dos circuitos de comando foram dimensionados para operar em uma freqncia de comutao (fs) de 10kHz. Para operar o circuito em freqncias na ordem de 25kHz, foi reduzido o valor da capacitncia do capacitor C1. Embora no se tenha efetuado, deve-se tambm reduzir o nmero de espiras do primrio e do secundrio do transformador de pulso e o ncleo do transformador de pulso. Para a aquisio das formas de onda mostradas na Fig. 12 foi utilizado o circuito de potncia da Fig. 8, cujo interruptor IGBT foi acionado com o circuito de comando de gate da Fig. 11. Todas as aquisies foram efetuadas para uma freqncia de operao do interruptor igual a 25kHz. Nas Figs. 12 (a) e (b) so mostradas as formas de onda dos sinais da tenso de entrada do circuito de comando (Vcon) e da tenso de sada gate-emissor (VGE) para as razes cclicas 0,5 e 0,1. Em relao ao sinal de entrada (Vcon), na Fig. 12 (a) o sinal de sada (VGE) apresenta um atraso na subida de 100ns e um atraso na descida de 200ns. Por outro lado, na Fig. 12 (b) o sinal de sada (VGE) tem um atraso na subida de 100ns e um atraso na descida de 400ns. Os atrasos na descida so maiores em relao subida e aumentam com a diminuio da razo cclica, por causa da demora (tempo de estocagem) no bloqueio do transistor bipolar Q1 do circuito de comando (Fig. 11). Este problema pode ser superado utilizando-se um transistor MOSFET de sinal. Na Fig. 12 (c) so mostradas as formas de onda dos pulsos da tenso gate-emissor VGE e da corrente de gate IG, durante a carga e a descarga da capacitncia de entrada do IGBT. Na Fig. 12 (d) so mostradas as formas de onda da tenso coletor-emissor VCE e da corrente de coletor IC. Os testes do circuito de comando foram realizados com estes nveis de tenso e de corrente. As formas de onda das Figs. 12 (e) e (f), mostram os detalhes da comutao do interruptor do conversor da Fig. 11. Como pode-se perceber, o IGBT entra em conduo sob condies de corrente nula devido s caractersticas indutivas da carga e bloqueia sob condies de tenso e corrente no nulas. Observando a ltima figura, a derivada da corrente de coletor provoca uma sobretenso sobre o IGBT devido presena de indutncias parasitas no circuito de potncia. Por este motivo, recomendado desenvolver o circuito de potncia com um timo layout. CIRCUITO A2 : O circuito da Fig. 13 possui uma proteo de sobrecorrente, devido sobrecarga ou curto-circuito, baseada na

observao da tenso entre coletor e emissor. Sabe-se que, para uma determinada tenso de gate, se ocorrer um aumento da corrente de coletor, aumenta tambm a tenso VCE. Deste modo, observando-se VCE pode-se detectar a existncia de sobrecorrente, devido a sobrecargas ou curtos-circuitos. A seguir so descritos os componentes que foram introduzidos para a proteo de sobrecorrente.
V GE Vcon V con V GE

(a) Vcon e VGE [5V/div.; 5s/div.] (b) Vcon e VGE [5V/div.; 5s/div.]
VGE

V CE IC

IG

(c) VGE [10V/div.; 5s/div.] iG [200mA/div.; 5s/div.]

V CE IC

(d) VCE [20V/div.;10s/div.] IC [2A/div.;10s/div.]

V CE IC

(e) VCE [20V/div.; 500ns/div.] (f) VCE [20V/div.; 500ns/div.] IC [2A/div.; 500ns/div.] IC [2A/div.; 500ns/div.] Fig. 12 - Formas de onda obtidas com os circuitos das Figs. 8 e 12.
Vcc1 R1 Tr vcon
15V

R5 Z1 Q2 Z2 R4 Q1

D2 D1

R6 R8 R7 Q3 D4 Z3 C2 C3

Z6

D3

C G R9 Z5 D5 Z4 E VGE

R2 C1 t

vcon R3

Capacitor C3 : permite a polarizao do transistor bipolar Q2 para que o sinal de comando transmitido pelo transformador de pulso chegue ao gate do IGBT. O IGBT, que inicialmente encontra-se com tenso coletor-emissor VCE igual ou maior que o valor da fonte de tenso do circuito de potncia, deve alcanar a tenso coletor-emissor de saturao VCEsat antes que a tenso sobre o capacitor C3 alcance o valor de VGE(on) . O valor de C3 determinado considerando a corrente de coletor do transistor Q2 igual corrente de pico de gate IGpk e de valor constante durante a comutao. Para este nvel de corrente, observando a curva de caracterstica de sada de transistor Q2 (catlogo) determinada a corrente de base IBQ2, que tambm aproximadamente constante. Portanto, com estas consideraes, o capacitor C3 carrega-se com corrente aproximadamente constante. O circuito equivalente mostrado na Fig. 14.
R6

Fig. 13 - Circuito de comando de gate isolado com transformador de pulso e com proteo de curto-circuito para 0 < D 0,5.

I BQ2

C3

vC3

Fig. 14 - Circuito equivalente durante a carga do capacitor C3 que ocorre na entrada em conduo do IGBT.

A tenso inicial sobre o capacitor C3, antes da entrada em conduo do IGBT, aproximadamente igual a: (11) v C3 (0) VZ6 + VD3 onde: VZ6 = 6,8 V : Tenso de operao do zener Z6;

VD3 = 0,7 V : Queda de tenso sobre o diodo D3 durante a conduo. A variao linear de tenso sobre o capacitor dada pela seguinte equao:
v C 3 ( t ) = v C 3 (0 ) + ( 1 I BQ 2 ) t C3

(12)

Considerando a tenso final sobre o capacitor C3 de 0,8VGE(on) para um tempo de durao do pulso de corrente de gate (tcom) de 400ns e substituindo na Eq. 12, obtm-se o valor da capacitncia C3. Com esta considerao, a tenso coletor-emissor (VCE) deve cair do valor mximo ao valor de saturao VCEsat antes que C3 possa carregar completamente. Quando a tenso coletor-emissor no atinge o valor de saturao durante este tempo previsto, o sinal de comando inibido e como conseqncia o IGBT bloqueado novamente. No caso da ocorrncia desta situao o valor da capacitncia deve ser aumentado experimentalmente. Utilizando a Eq. 13, obtida a partir de Eq. 12, pode ser determinado o valor de C3:
C3 I BQ2 t com [0,8 VGE(on ) ] v C3 (0)

(13)

Das curvas de caracterstica de sada do transistor Q2 (2N2907) para a corrente de coletor ICQ2 = Igpk, a corrente de base IBQ2 aproximadamente igual a 20 mA. Substituindo valores na Eq. 13, o valor da capacitncia igual a: C 3 1,8 F Quando ocorre o curto-circuito de carga em estado de conduo do IGBT, a tenso coletor emissor VCE cresce e o diodo D3 bloqueado. A tenso sobre o capacitor C3 comea a crescer desde o valor inicial VC3(0) devido corrente de base do transistor Q2. Quando a tenso sobre ele atinge o valor do potencial da base do transistor Q2, este transistor bloqueado inibindo o sinal de comando de gate. A corrente de base que carrega o capacitor C3 depende da corrente de coletor. Portanto, para diminuir o tempo de bloqueio, o resistor R9 entre gate-emissor ajustado para um baixo valor. A corrente de base determinada a partir das curvas de caracterstica de sada do transistor Q2 (catlogo) como uma funo da corrente de coletor no instante do curto-circuito. O tempo que demora para atuar a proteo pode ser estimado com a seguinte equao:
t blo = C 3 VGE (on ) v C3 (0) I BQ 2( curto )

(14)

A corrente de coletor (ICQ2) durante o curto-circuito igual corrente que flui pelos resistores R4, R7 e R9, (IGpk 0), e seu valor igual a ICQ2 = 35 mA. Uma vez conhecida a corrente de coletor, das curvas de caracterstica de sada do transistor Q2 (2N2907) a corrente de base aproximadamente igual a : IBQ2(curto) = 2,5 mA. Logo, substituindo os valores na Eq. 14, o tempo de bloqueio, aps ocorrido o curto-circuito, aproximadamente igual a: t blo 5,4 s Ou seja, o IGBT poder suportar correntes superiores a 6 vezes a corrente nominal at atuar a proteo, pois este tempo ser inferior a 10s. Diodo D3 : detecta a dessaturao da tenso coletor-emissor do IGBT. Este diodo deve ser ultra-rpido e com tenso reversa de operao maior que a mxima tenso coletor-emissor do IGBT. Sua corrente mdia muito pequena, menor que 100mA. Zener Z6: Permite detectar o curto-circuito com baixos valores da tenso coletor-emissor (VCE). Tambm evita a descarga do capacitor C3. Para obter as aquisies das formas de onda mostradas na Fig. 15 foi utilizado o circuito de potncia da Fig. 8, cujo interruptor IGBT foi acionado com o circuito de comando de gate da Fig. 13. Todas as aquisies foram obtidas para uma freqncia de operao do interruptor de 25kHz. Nas Figs. 15 (a) e (b) so mostradas as formas de onda dos sinais da tenso de entrada do circuito de comando Vcon e da tenso de sada, gate-emissor VGE, para as razes cclicas 0,5 e 0,1. Em relao ao sinal de entrada Vcon, na Fig. 15 (a) o sinal de sada (VGE) apresenta um atraso na subida de 125ns e um atraso na descida de 225ns. Por outro lado, na Fig. 15 (b), o sinal de sada VGE tem um atraso na subida de 125ns e um atraso na descida de 430ns. Do mesmo modo que no caso anterior, os atrasos na descida so maiores em relao subida e aumentam com a diminuio da razo cclica e isto ocorre por causa da demora do bloqueio do transistor bipolar Q1. Na Fig. 15 (c) so mostradas as formas de onda da tenso gate-emissor (VGE) e da corrente de coletor durante o teste de curto-circuito do IGBT. Observa-se na figura que o circuito de comando garante a proteo em aproximadamente 5s aps detectada a falha. O tempo de durao do curto-circuito est abaixo do valor permitido, que de 10s. Por outro lado, na Fig. 15 (d) so mostradas as formas de onda da tenso coletor-emissor VCE e da corrente de coletor durante o teste de curto-circuito do IGBT. Ressalta-se que ocorre uma sobretenso no bloqueio do IGBT devido elevada derivada de corrente sobre indutncias parasitas da malha formada por C2, D1 e IGBT1 da Fig. 8. CIRCUITO A3 : Os circuitos das Figs. 16 e 18 permitem operar os interruptores de potncia com razo cclica e freqncia variveis, dentro de uma faixa de variao no muito elevada. Estes circuitos normalmente so aplicados em conversores com modulao PWM senoidal [14].

VGE

VGE V con
Vcon

(a) Vcon e VGE [5Vdiv.;5s/div.] b) Vcon e VGE [5Vdiv.; 5s/div.]

VGE
V CE

IC

IC

(c) VGE [10V/div.; 10s/div.]; IC [50A/div.; 10s/div.]

(d) VCE [50V/div.; 10s/div.] IC [50A/div.; 10s/div.]

Fig. 15 - Formas de onda obtidas com os circuitos das Figs. 8 e 12.

Capacitores C2 e C3: permitem uma corrente mdia nula nos enrolamentos primrio e secundrio para evitar a saturao do transformador de pulso. Os valores das capacitncias podem ser obtidos realizando a medio da indutncia magnetizante do transformador e considerando a freqncia de ressonncia (fr ) igual a 1/10 da freqncia de comutao (fs). A seguir so dadas as equaes para determinar os valores de suas capacitncias: C2 1 Lm 10 2f s
2

(15)

N1 C3 = (16) N C2 2 onde: Lm : Indutncia magnetizante do primrio do transformador; fs : Freqncia de comutao do IGBT; N1 : Nmero de espiras do primrio do transformador; N2 : Nmero de espiras do secundrio do transformador. Capacitor C5 : permite um rpido bloqueio do transistor de sinal Q2 evitando o atraso na subida do sinal de comando. Seu valor deve ser maior ou igual a 5,6nF.
Vcc1 Q3 C2 Q2 Q1 C1 Q4 Tr D1 R4 Q5 C3 D2 R5 D3 C4 Z1 R6 R7 D4 Z2 Z3 VGE E G
vcon 15V t

R1 R3 vcon

R2 C5

Transformador de Pulso Tr : deve ser projetado de maneira similar ao do circuito da Fig. 11. Dispositivos R1, R2, C5, Q1 e Q2 : so utilizados para polarizar os transistores de sinal Q3 e Q4. Se o nvel de tenso dos pulsos do circuito de controle (vcon) for maior ou igual ao valor de VCC1, estes dispositivos no so necessrios. Para a aquisio das formas de onda mostradas na Fig. 17 foi utilizado o circuito de potncia da Fig. 8, onde o interruptor IGBT foi acionado com o circuito de comando de gate da Fig. 16.
V GE V con

Fig. 16 - Circuito de comando de gate isolado com transformador de pulso e sem proteo de Curto-circuito para 0 < D < 1.

V GE V con

Nas Figs. 17 (a) e (b) so mostradas as formas de onda dos sinais da tenso de entrada do circuito de comando Vcon e

(a)Vcon e VGE [5V/div.;5s/div.] (b)Vcon e VGE [5V/div.;5s/div.] Fig. 17 - Formas de onda obtidas com os circuitos das Figs. 8 e 16.

da tenso de sada gate-emissor VGE para as razes cclicas 0,9 e 0,1. Em relao ao sinal de entrada Vcon, na Fig. 17 (a) o sinal de sada VGE apresenta um atraso na subida de 350ns e um atraso na descida de 170ns. Por outro lado, na Fig. 17 (b) o sinal de sada VGE tem um atraso na subida de 80ns e um atraso na descida de 150ns. O sinal de sada gate-emissor tem um atraso na subida maior, em comparao com o atraso na descida, por causa do bloqueio lento do transistor bipolar Q2 do circuito da Fig. 17. O capacitor C5 que cumpre a funo de permitir um bloqueio rpido deste transistor tem menor energia quando aumenta a razo cclica. Portanto, o atraso na subida diminui quando diminui a razo cclica, devido a uma maior saturao do transistor Q4. Esta concluso confirmada com os resultados dos valores dos atrasos para a razo cclica 0,1. Estes atrasos podem ser alterados modificando as correntes de base de Q3 e Q4 ou adicionandose circuitos de anti-saturao. CIRCUITO A4 O circuito da Fig. 18 possui caracterstica de proteo de sobrecorrente, alm das caractersticas do circuito anteriormente apresentado na Fig. 16. Para a aquisio das formas de onda mostradas na Fig. 19 foi utilizado o circuito de potncia da Fig. 8, onde o interruptor IGBT foi acionado com o circuito de comando de gate da Fig. 18. Todas as aquisies foram efetuadas para uma freqncia de operao do interruptor de 25kHz.
Vcc1 Q3 C2 Q2 Q4 Tr D1 R4 C3 Q6 Q5 R5 D3 D2 R6 D5 Z1 C6 R7 R8 R9 D6 Z2 E Z3 Z4 D4 C G VGE C4
vcon 15V t

R1 R3 vcon C1

R2 C5 Q1

Nas Figs. 19 (a) e (b) so mostradas as formas de onda dos sinais da tenso de entrada do circuito de comando Vcon e da tenso de sada gate-emissor VGE para as razes cclicas 0,9 e 0,1. Em relao ao sinal de entrada, na Fig. 19 (a), o sinal de sada VGE apresenta um atraso na subida de 380ns e um atraso na descida de 180ns. Por outro lado, na Fig. 19 (b), o sinal de sada VGE tem um atraso na subida de 80ns e um atraso na descida de 170ns. Neste circuito, as diferenas dos tempos de atrasos ocorrem pelos mesmos motivos indicados no circuito da Fig. 16.
Vcon VGE

Fig. 18 - Circuito de comando de gate isolado com transformador de pulso e com proteo de curto-circuito para 0 < D < 1.

VGE Vcon

(a)Vcon e VGE [5V/div.;5s/div.] (b)Vcon e VGE[5V/div.; 5s/div.]

V GE VCE

IC

IC

(c) VGE [10V/div.; 10s/div.] (d) VCE [50V/div.; 10s/div.] IC [50A/div.; 10s/div.] IC [50A/div.; 10s/div.] Fig. 19 - Formas de onda obtidas com os circuitos das Figs. 8 e 18.

Na Fig. 19 (c) so mostradas as formas de onda da tenso gate-emissor VGE e da corrente de coletor IC durante o teste de curto-circuito do IGBT. Observa-se que o circuito de comando de gate garante a proteo do IGBT em aproximadamente 5,5s aps detectada a falha. O tempo de durao do curto-circuito menor que o valor permitido, que normalmente de 10s no mximo. Na Fig. 19 (d) so mostradas as formas de onda da tenso coletor-emissor (VCE) e da corrente de coletor durante a ocorrncia do curto-circuito do IGBT. Verifica-se que a rpida descida da corrente de curto-circuito provoca uma sobretenso entre o coletor e o emissor do IGBT. Esta sobretenso em alguns casos pode provocar a destruio do dispositivo. Esta derivada de corrente de coletor pode ser diminuda aumentando o valor da resistncia de gate. No caso de no ser aumentado o valor da resistncia de gate, a sobretenso pode ser limitada colocando-se um grampeador de tenso entre coletor e emissor, projetado segundo a rea de operao segura de bloqueio (RBSOA). A sobretenso originada pelas indutncias parasitas na malha formada por C2, D1 e IGBT1 da Fig. 8. 2.3.1 Circuitos de comando isolados por optoacoplador Nas Figs. 20 e 22 so apresentados os circuitos de comando isolados por optoacoplador para acionar interruptores IGBTs. Estes circuitos permitem aplicar pulsos de tenso gate-emissor positivos de 15V e negativos de 7,5V. A diferena entre os dois circuitos proteo de curto-circuito por deteco de saturao da tenso coletor-emissor do

IGBT realizada pelo circuito da Fig. 22. Todos os dispositivos destes circuitos so dimensionados de acordo com as limitaes de tenso e corrente do optoacoplador da Hewlett Packard (HCPL 2200) e exigncias de corrente de gate para entrada em conduo e bloqueio do IGBT. CIRCUITO B1: Para a aquisio das formas de onda mostradas na Fig. 21 foi utilizado o circuito de potncia da Fig. 8, onde o interruptor IGBT foi acionado com o circuito de comando de gate da Fig. 20. Todas as aquisies foram feitas para uma freqncia de operao do interruptor de 25kHz.
Vcc1 C4 R2 R4 C3 Q1 R5 R6 Q2 Q3 Q4 R7 Z3 R8 D1 C5 Z2 E

G VGE

R3 C1
vcon 15V t

1 2

8 CI1 7 6
HCPL2200

R1

3 4

5 Z1 C2

Fig. 20 - Circuito de comando de gate isolado com optoacoplador e sem proteo de curto-circuito.
VGE V con
Vcon VGE

Nas Figs. 21 (a) e (b) so mostradas a formas de ondas dos sinais da tenso de entrada do circuito de comando Vcon e da tenso de sada gate-emissor VGE para as razes cclicas 0,9 e 0,1. Em relao ao sinal de entrada, na Fig. 21 (a), o sinal de sada VGE apresenta um atraso na subida de 450ns e um atraso na descida de 400ns Por outro lado, na Fig. 21 (b) o sinal de sada VGE tem um atraso na subida de 425ns e um atraso na descida de 400ns. Neste circuito os tempos de atraso na subida e na descida e em toda a faixa de variao da razo cclica so aproximadamente iguais. Observa-se que, com este circuito, possvel obter-se uma ampla faixa de variao de freqncias dos pulsos de comando que s limitada nas altas freqncias por estes atrasos acima citados. Estes atrasos ainda poderiam ser diminudos melhorando-se os tempos de bloqueio dos transistores Q2 a Q4. CIRCUITO B2:
Vcc1 C4 R2 R4 R3 C1
vcon 15V t

(a) Vcon e VGE[5V/div.;5s/div.] (b) Vcon e VGE[5V/div.;5s/div.] Fig. 21 - Formas de onda obtidas com os circuitos das Figs. 8 e 20.

D2 R7

R9

Z4

D3 C

R5

R6 Q2 Q1

Q3 Q4

Q5 D1

R8 C6 R10 Z3

G VGE

1 2

8 CI1 7 6
HCPL2200

C3

R1

3 4

C5

D4

Z2

5 Z1 C2

Fig. 22 - Circuito de comando de gate isolado com optoacoplador e com proteo de curto-circuito.

Para a aquisio das formas de onda mostradas na Fig. 23 foi utilizado o circuito de potncia da Fig. 8, onde o interruptor IGBT foi acionado com o circuito de comando de gate da Fig. 22. Todas as aquisies foram feitas para uma freqncia de operao do interruptor de 25kHz. Nas Figs. 23 (a) e (b) so mostradas as formas de onda dos sinais de tenso de entrada do circuito de comando Vcon e da tenso de sada gate-emissor VGE para as razes cclicas 0,9 e 0,1. Em relao ao sinal de entrada, na Fig. 23 (a), o sinal de sada VGE apresenta um atraso na subida de 500ns e um atraso na descida de 450ns, por outro lado, na Fig. 23 (b) o sinal de sada VGE tem um atraso na subida de 450ns e um atraso na descida de 425ns. Neste circuito as diferenas dos tempos de atraso na subida e na descida do sinal da tenso de sada, para toda a faixa de variao de razo cclica, so aproximadamente iguais. Na Fig. 23 (c) so mostradas as formas de onda da tenso gate-emissor VGE e da corrente de coletor durante o teste de curto-circuito do IGBT. Observa-se que o circuito de comando de gate garante a proteo do IGBT em aproximadamente 5,5s aps detectada a falha. Na Fig. 23 (d) so mostradas as formas de onda da tenso coletor-emissor VCE e da corrente de coletor durante a ocorrncia de curto-circuito do IGBT. Nesta aquisio mostrado o detalhe do efeito da descida da corrente de curtocircuito que provoca uma sobretenso entre coletor e emissor devido s indutncias parasitas do circuito de potncia, sendo que em muitos casos, esta sobretenso pode ser destrutiva para o dispositivo.

Vcon

Vcon

VGE

VGE

(a) Vcon e VGE[5V/div.;5s/div.] (b) Vcon e VGE[5V/div.;5s/div.]

VGE VCE

IC

IC

(c) VGE [10V/div.; 10s/div.] (d) VCE [50V/div.; 10s/div.] IC [50A/div.; 10s/div.] IC [50A/div.; 10s/div.] Fig. 23 - Formas de onda obtidas com os circuitos das Figs. 8 e 22.

2.3.3 Circuitos de comando integrados Nas Figs. 24 e 26 so mostrados os circuitos de comando integrados com isolamento para acionar interruptores IGBTs. Estes circuitos permitem aplicar pulsos de tenso gate-emissor positivos de 15V e negativos de 7,5V. No circuito da Fig. 24 empregou-se somente dois dos trs circuitos de comando isolados disponveis no circuito integrado. Os sinais de comando utilizados possuem pulsos complementares com tempo morto ajustado atravs do circuito gerador de sinais e empregados nos interruptores do circuito da Fig. 26. CIRCUITO C1 : O circuito integrado (CI1) da Fig. 24 um circuito da Powerex/Mitsubishi que contm internamente trs circuitos de comando isolados por optoacopladores, independentes, capazes de acionar trs IGBTs com diferentes nveis de potencial de emissor. importante mencionar que os circuitos no realizam proteo alguma de curto-circuito do IGBT. Na aplicao do integrado no acionamento de IGBTs com diferentes potenciais de emissor, cada circuito de comando deve possuir uma fonte de tenso isolada na sada. Agora, no caso de ter-se IGBTs com seus emissores conectados a um n comum, necessrio somente uma fonte de tenso na sada para todos os circuitos de comando que acionam estes dispositivos. Para transmitir os pulsos de tenso da entrada para a sada, os circuitos requerem uma fonte de tenso na entrada com valor no maior que 5V (VCC1) como mostra a figura. Uma outra caracterstica do circuito a seguinte: para limitar as correntes de polarizao de entrada, drenadas da fonte de 5V, no so necessrios resistores externos, pois possuem internamente seus resistores.
Vcc1
6 2 vcon1 15V t

R3
7

C1
1

C2
5

R2 Vcc2

Z3 R4 Z2

G1 VGE1 E1

vcon1 R1

Q1

CI1
16 17 11

Z1

C3

12 vcon2 15V t

R3 C2 R2 Vcc2 Z2 Z1 C3 z3 R4

C1 Q1 R1

G2 VGE2 E2

15 18

vcon2

M57919L
26 27 22

R3 C2 R2 Vcc2 Z3 R4 Z4 Z1 C3

G3

25 28

C1
21

Q1 R1

E3

Fig. 24 - Trs circuitos de comando de gate isolados independentes sem proteo de curto-circuito.

Para a aquisio das formas de onda mostradas na Fig. 25 foram utilizados os circuitos de potncia da Fig. 9, onde os interruptores IGBTs foram acionados com os circuitos de comando de gate da Fig. 24. Todas as aquisies foram feitas para uma freqncia de operao do interruptor de 25kHz. Nas Figs. 25 (a) e (b) so mostradas as formas de onda dos sinais da tenso de entrada do circuito de comando Vcon e da tenso de sada gate-emissor VGE para as razes cclicas 0,9 e 0,1. Em relao ao sinal de entrada, na Fig. 25 (a), o

sinal de sada VGE apresenta um atraso na subida de 650ns e um atraso na descida de 550ns. Por outro lado, na Fig. 25 (b) o sinal de sada VGE tem um atraso na subida de 600ns e um atraso na descida de 550ns. Neste circuito as diferenas dos tempos de atrasos na subida e na descida so pequenos (esta afirmao vlida para freqncias menores que 40 kHz) e esto dentro das especificaes dadas no catlogo do componente (M57919L).
Vcon
Vcon VGE

VGE

(a) Vcon e VGE[5V/div.;5s/div.] (b) Vcon e VGE[5V/div.;5s/div.] Fig. 25- Formas de onda obtidas com os circuitos das Figs. 9 e 24.

CIRCUITO C2 O circuito da Fig. 26 foi desenvolvido para acionar dois IGBTs em uma configurao meia ponte. Neste circuito, os circuitos de comando esto dados pelos circuitos integrados CI1 e CI3 da Powerex/Mitsubishi, ambos isolados por optoacoplador. No circuito de comando da figura o circuito integrado CI1 aciona o interruptor superior e o circuito integrado CI3 aciona o interruptor inferior. Estes circuitos integrados no realizam ajuste do tempo morto dos sinais de comando - que previne curto-circuito de brao. Portanto, o tempo morto deve ser ajustado no circuito de controle. Na ocorrncia de curto-circuito em qualquer interruptor do brao, os circuitos integrados CI1 e CI3 detectam a dessaturao da tenso coletor-emissor VCE por meio do diodo conectado ao coletor D1 e inibem o sinal de comando de gate em aproximadamente 6,5s. Este valor de tempo menor do que o tempo permitido para no destruir o IGBT. Os integrados tambm so capazes de gerar sinais de ocorrncia de curto-circuito que podem ser transmitidos ao circuito de controle atravs de optoacopladores. No circuito da Fig. 26, o sinal de ocorrncia de curto circuito transmitido para o circuito de controle por meio dos optoacopladores CI2 e CI4. Neste circuito, o sinal de ocorrncia permite a entrada em conduo do tiristor de sinal SCR1 e coloca o pino 10 ( pino shutdown ) do circuito integrado CI-3524 (que no exemplo utilizado para gerar os pulsos de comando) no potencial de tenso de VCC3, desta maneira inibindo completamente os sinais de sada do circuito integrado. No caso de no serem inibidos os sinais gerados pelo CI-3524, os circuitos integrados CI1 e CI3 inibem os sinais de comando de gate por 1,2ms aps detectada a falha e, logo aps este intervalo de tempo, liberam novamente o sinal de comando de gate e assim sucessivamente. Como os integrados CI1 e CI3 apresentam um tempo de reset, os optoacopladores CI2 e CI4 podem ser lentos.
Vcc3 8

CI2
R9 Q3 Q2 R10 C4 R7 R8 7 6 5

2 3

R5 D1

C1
8 1 5 R3

6N136
Vcc3 Pino Shutdown R12 SCR1 P1 R11 t vcon1 15V C5 C1 Vcc1 R6

CI1
14

G1
Z4

4 13 Q1 C2 C3 R2 Z1 Z2 R4 Vcc2

VGE1
Z3

vcon1
R1 Vcc3

M57962L
6

E1
8

CI4
R9 Q3 Q2 C4 R7 5 R8 7 6

2 3

R5 D1

R10

C2

6N136
Vcc1 vcon2 15V t C1 R6

1 5 R3

CI3
14 4 13 Q1 C2 C3 R2 Z2 Z1

G2
Z4 R4

VGE2
Z3

vcon2
R1

M57962L
6

Vcc2

E2 . Fig. 26 - Circuito de comando para brao utilizando dois circuitos integrados (CI1 e CI3) isolados com proteo de curto-circuito.

Para a aquisio das formas de onda mostradas na Fig. 27 foi utilizado o circuito de potncia da Fig. 9, onde os interruptores IGBTs foram acionados com o circuito de comando para brao da Fig. 26. Todas as aquisies foram feitas para uma freqncia de operao do interruptor igual a 25kHz. Na Fig. 27 (a), so mostradas as formas de onda dos sinais da tenso de entrada Vcon e da tenso gate-emissor VGE. Esta figura foi adquirida para explicar o ajuste da desigualdade dos tempos de atraso do sinal de tenso gate-emissor VGE em relao ao sinal de tenso de entrada Vcon na subida e na descida. Neste caso, o tempo de atraso na subida de 650ns e na descida de 1,2s. Esta desigualdade foi diminuda colocando-se um resistor de 270 em srie com o fotodiodo na entrada do CI1 e CI2 (resistor R6 do circuito da Fig. 26). O excesso de corrente no fotodiodo faz com que o fototransistor fique excessivamente saturado aumentando o seu tempo de estocagem no bloqueio Nas Figs. 27 (b) e (c) so mostradas as formas de onda dos sinais da tenso de entrada do circuito de comando Vcon e da tenso de sada gateemissor VGE com os ajustes necessrios, para as razes cclicas 0,9 e 0,1. Em relao ao sinal de entrada, na Fig. 27 (b),

o sinal de sada VGE apresenta um atraso na subida de 700ns e um atraso na descida de 700ns. Por outro lado, na Fig. 27 (c) o sinal de sada VGE tem um atraso na subida de 650ns e um atraso na descida de 700ns. Com a modificao introduzida, neste circuito, as diferenas dos tempos de atrasos na subida e na descida para toda a faixa de variao de razo cclica esto dentro das especificaes indicadas no catlogo do componente (M57962L).
Vcon
V GE V con

VGE

(a)Vcon e VGE[5V/div.;5s/div.] b) Vcon e VGE [5V/div.;5s/div.]

Vcon
VGE

VGE
IC

(c) Vcon e VGE [5V/div.; 5s/div.] (d) VGE [10V/div.; 10s/div.] IC [50A/div.; 10s/div.]
V CE

IC

(e) VCE [50V/div.; 10s/div.] IC [50A/div.; 10s/div.] Fig. 27 - Formas de onda obtidos com os circuitos das Figs. 9 e 26.

Na Fig. 27 (d) so mostradas as formas de onda da tenso gate-emissor VGE e da corrente de coletor durante o teste de curto-circuito do IGBT. Por outro lado, na Fig. 27 (e) so mostradas as formas de onda da tenso coletor-emissor VCE e da corrente de coletor durante o curto-circuito. CIRCUITO C3 Na Fig. 28 apresentado o circuito de comando utilizando o integrado TLP250 da Toshiba para acionar IGBTs e MOSFETs. Este circuito isolado por meio de um optoacoplador interno composto de um diodo emissor de luz e um fotodetector integrado. O circuito permite aplicar pulso de tenso gate-emissor positivo de 15V e negativo de 5,1V. O circuito tambm realiza proteo de curto-circuito por deteco da tenso de dessaturao coletor-emissor, inibindo os pulsos de gate antes da destruio do IGBT. Uma outra caracterstica do circuito que permite a limitao da corrente de curto-circuito por meio de reduo da tenso gate-emissor aps ocorrida a falha. Os dispositivos externos ao circuito integrado so dimensionados de acordo com as limitaes do circuito integrado TLP250. O circuito integrado TLP250 recomendado para operar at freqncias de 25kHz pelo fato das diferenas dos tempos de atraso na subida e na descida. Estas diferenas sero observadas nas Fig. 29.
R9 D6 D4 R7 D1 C1
vcon 15V t

D7 R8 Z6 C Z5 R4 D2 Z4 R6 Q3 C5 R5 D3 Z3 C4 Z2 D5 G VGE E

1 2

8 CI1 7 6 TLP250 5 C2 Z1 C3 R2 Vcc1

Q1 Q2 R3

R1

3 4

Nas Figs. 29 (a) e (b) so mostradas as formas de onda dos sinais de tenso de entrada do circuito de comando Vcon e da tenso de sada gate-emissor VGE para as razes cclicas 0,9 e 0,1. Em relao ao sinal de entrada, na Fig. 29 (a), o sinal de sada VGE apresenta um atraso na subida de 400ns e um atraso na descida de 200ns, por outro lado, na Fig. 29 (b) o sinal de sada VGE tem um atraso na subida de 400ns e um atraso na descida de 200ns. Este circuito apresenta diferenas nos tempos de atrasos da subida e da descida do sinal da tenso de sada. Para toda a faixa de variao de

Fig. 28 - Circuito de comando de gate isolado com proteo e limitao da corrente de curto-circuito.

razo cclica, so iguais os atrasos. Na Fig. 29 (c) so mostradas as formas de onda da tenso gate-emissor VGE e da corrente de coletor durante o teste de curto-circuito do IGBT. Nesta figura, observa-se que quando ocorre o curto-circuito a tenso gate-emissor VGE reduzida ao valor da tenso de operao do zener Z2 e, como conseqncia, a corrente de curto-circuito de coletor mantida em um valor de aproximadamente duas vezes o valor nominal. Desta maneira o interruptor capaz de suportar a situao de curto-circuito por um tempo muito maior que o tempo recomendado (10s). Como pode-se observar, o interruptor suporta 18s sem ser destrudo. Na Fig. 7.29 (d) so mostradas as formas de onda da tenso coletor-emissor VCE e da corrente de coletor durante a ocorrncia de curto-circuito do IGBT. Nesta aquisio mostrado o detalhe do efeito da descida da corrente de curtocircuito que provoca uma sobretenso entre coletor e emissor devido s indutncias parasitas do circuito de potncia. Como a magnitude da corrente de curto-circuito pequena em relao magnitude de corrente em operao normal (sem limitao de corrente de curto-circuito), as sobretenses entre os terminais de coletor-emissor so muito pequenas.
V con V con

V GE V GE

(a) Vcon e VGE 5V/div.; s/div.] (b) Vcon e VGE [5V/div.; s/div.]

VGE

VCE

IC

IC

(c) VGE [5V/div.; 10s/div.] IC [50A/div.; 10s/div.]

(d) VCE [50V/div.; 10s/div.] IC [50A/div.; 10s/div.]

Fig. 29 - Formas de onda obtidas com os circuitos das Figs. 8 e 28.

CIRCUITO C4 Na Fig. 30 apresentado o circuito de comando dedicado SKHI22 da Semikron para acionar dois IGBTs em meia ponte. Este circuito isolado por meio de transformador de pulso. O circuito no necessita fonte de tenso no lado da sada pois possui internamente um conversor cc/cc que gera as tenses complementares 15V para os pulsos de comando do gate. Alm disto, realiza ajuste de tempo morto atravs de sua lgica interna quando so aplicados pulsos de entrada sem tempo morto. O valor mnimo do tempo morto de 2,7s com possibilidade de ajuste acima do valor indicado. Os tempos de retardo dos sinais em torno de 1s na subida e 1s na descida. O circuito apresenta proteo de curto-circuito por deteco da tenso de saturao coletor-emissor VCEsat. O tempo de retardo de deteco de curto circuito 1,75s para RCE = 24k e CCE = 330pF (RCE e CCE so componentes externos ao integrado com os quais possvel ajustar este retardo, C1 e C2 , R4 e R9 da Fig. 30). Aps este tempo de retardo o sinal de sada inibido por 1s. Em operao normal o pino de erro do circuito integrado encontra-se em nvel alto (15V) e quando ocorre a falha em nvel baixo (<0,7V). Quando ocorre a falha, os pulsos de entrada do circuito integrado devem ser inibidos completamente, pois se isto no ocorrer tem-se pulsos de curta durao na sada do circuito integrado que podem provocar curtos-circuitos sucessivos do IGBT at destru-lo. Os dispositivos externos ao circuito integrado so dimensionados de acordo com as recomendaes dadas no catlogo do fabricante do circuito de comando integrado. O circuito integrado SKHI22 recomendado para operar na faixa de freqncias de 5kHz a 100kHz. Ele apresenta um tempo morto de 2,7s; por este fato pode no ser conveniente em algumas aplicaes de freqncias elevadas. Quando o circuito de comando aplicado em mdulos de IGBTs de elevada capacidade de corrente de coletor IC, sua freqncia de operao limitada pela carga da capacitncia de entrada dos mdulos. Nas Figs. 31 (a) e (b) so mostradas as formas de onda dos sinais de tenso de entrada do circuito de comando VIN1 e da tenso de sada gate-emissor VGE1 para as razes cclicas 0,9 e 0,1. Em relao ao sinal de entrada VIN1, na Fig. 31 (a), o sinal de sada VGE1 apresenta um atraso na subida de 1s e um atraso na descida de 1s, por outro lado, na Fig. 31 (b) o sinal de sada VGE tambm tem um atraso de 1s na subida e na descida. Neste circuito de comando os valores dos atrasos so praticamente iguais na subida e na descida, tal como indica no catlogo, para qualquer variao de razo cclica. Nas Figs. 31 (c) e 31 (d) so mostradas as duas formas de onda de sada do circuito de comando. As mesmas so complementares para acionar dois interruptores IGBTs de um mesmo brao de um conversor em ponte. O tempo morto ajustado acima do valor de 2,7s atravs dos resistores R1 e R2 da Fig. 31.

Vcc1 VCE1 CCE1 VS V IN1 R1 R TD1 CI1 GON1 R3 R4 C1 R5 R6 Z1 R11 Z2

GND/0V C3

C1 G1

SKHI22

GOFF1 E1 E2

E1 E2

ERROR

R2

GOFF2 RTD2 V IN2 GND/0V GON2 CCE2 VCE2

R7 R8 C2 R9 R10

R12

Z3 Z4

G2 C2

Fig. 30 - Circuito de comando de gate isolado com proteo de curto-circuito.

VIN1 V GE1

V IN1

V GE1

(a)VIN1 e VGE1[5V/div;5s/div.] (b)VIN1 e VGE1 [5V/div;5s/div]

VGE1 VGE1 VGE2 VGE1

(c)VGE1 e VGE2[5V/div;5s/div] (d)VGE1 e VGE2[5V/div;5s/div] Fig. 31 - Formas de onda obtidas com os circuitos das Figs. 9 e 30.

CIRCUITO C4 Na Fig. 32 apresentado um circuito de comando muito simples para inversores, com uma utilizao mnima de componentes, utilizando transformadores de isolamento. Embora o circuito no tenha proteo de curto-circuito, permite aplicar uma tenso negativa durante o bloqueio e no necessita de gerao de tempo morto.
+Vcc +15V Tr1 D1 T2 R2=47R Dz2 Dz3 R1=2k2 T1 D2 T3 Dz4 Dz5 D3 Lr Cs

D4

R3=47R

Fig. 32 - Circuito de comando de gate isolado com transformador.

O transformador de isolamento foi projetado para utilizao com uma freqncia de comutao de 35kHz, utilizando um ncleo da Thornton tipo E20, com 37 espiras de fio 28 AWG no primrio e 40 espiras do mesmo fio em cada secundrio. O maior nmero de espiras no secundrio (relao de transformao ligeiramente maior do que 1) permite compensar as quedas de tenso do transistor T1 e do prprio transformador. Para a aquisio das formas de onda mostradas na Fig. 33 os interruptores IGBTs foram acionados com o circuito de comando e de potncia da Fig. 32. Todas as aquisies foram feitas para uma freqncia de operao do interruptor igual a 30kHz. Na Fig. 33.a pode-se observar as tenses no enrolamento do primrio e em um dos enrolamentos do secundrio do transformador. Na Fig. 33.b mostra-se as tenses de gate dos transistores T2 e T3 onde pode-se observar o efeito da capacitncia Miller, que varia com a variao da tenso VCE do IGBT.

a) Tenso nos enrolamentos b) detalhe da tenso de gate primrio e secundrio dos interruptores na comutao

c) VCE1. [100V/div.; 2,5s/div.] e IC1 [0,5A/div.; 2,5s/div.] Fig. 33 - Formas de onda obtidas com o circuito da Fig. 32.

3 - CONCLUSES
Depois dos testes realizados com os diferentes circuitos de comando mostrados anteriormente, chega-se seguintes concluses: Os transformadores de pulso dos circuitos de comando de gate foram projetados para operar em uma freqncia de comutao de 10kHz. Embora projetados para esta freqncia, ainda assim funcionam sem problema at freqncias de aproximadamente 40kHz. Porm, quanto maior for a freqncia, mais difcil ser desmagnetizar o ncleo, devido ao elevado nmero de espiras (maior corrente magnetizante), aumentando os atrasos entre os pulsos de entrada e de sada do circuito de comando de gate. Recomenda-se projetar os transformadores de pulso, exatamente para a freqncia de operao do conversor. Em quase todos os circuitos de comando de gate projetados, os dispositivos que provocam maior atraso so os transistores bipolares de sinal, pois o tempo de bloqueio destes transistores elevado. Eles, para serem rpidos, necessitam da aplicao de uma corrente de base negativa (transistores npn). Por este motivo, para poder diminuir os tempos de atraso na subida e na descida dos circuitos de comando de gate, recomenda-se, se for possvel, a utilizao de MOSFETs de sinal. Na prtica todos os circuitos de comando de gate testados podem ser utilizados, pois eles apresentam boas caractersticas de operao e confiabilidade. A escolha depender do critrio do projetista do conversor, pois ele deve analisar o tipo de isolamento necessrio, em funo da freqncia e da variao da razo cclica. Algumas vezes o critrio de escolha tambm depende do custo dos componentes, volume e peso. As caractersticas de custo e confiabilidade no foram analisadas neste trabalho.

4 - REFERNCIAS BIBLIOGRFICAS
[1] - FUJI ELECTRIC; "IGBT data book"; Catlogo; 1994. [2] - SEMIKRON; "Semicondutores de potncia"; Catlogo, 1993; pp. A-67 A-73. [3] - REINMUTH, K.; LORENZ, L.; "A new generation of IGBTs and concepts for their protection"; PCIM'94, June 28-30, 1994, NrnbergGermany; pp. 139-147. [4] - ELASSER, Ahmed et al; Switching losses of IGBTs under zero-voltage and zero-current switching; IAS96, San Diego, California, U.S.A.; 1996; pp. 600-607. [5] - BALIGA, B. J.; "Modern power devices"; Ed: John Wiley & Sons, Inc., 1987; pp. 350-401. [6] - MARTINS FERNANDEZ, D. J.; "Conversor DC-DC quase-ressonante para altas potncias utilizando IGBT"; Dissertao de Mestrado em Engenharia Eltrica; Florianpolis, UFSC-Brasil; 1991. [7] - ELASSER, Ahmed et al; Switching losses of IGBTs under zero-voltage and zero-current switching; IAS96, San Diego, California, U.S.A.; 1996; pp. 600-607. [8] - CLEMENTE, S.; DUBHASHI, A.; PELLY, B.; " IGBT characteristic and application"; Application Note, AN-983A; 1994; pp. 93-106. [9] BASCOP, Ren Pastor Torrico; PERIN, Arnaldo Jos; "O transistor IGBT aplicado em eletrnica de Potncia"; Editora Sagra Luzzatto, Porto Alegre RS, 1997. [10] - BISWAS, S. K.; BASAK, B.; RAJASHEKARA, K. S.; Gate drive methods for IGBTs in bridge configurations; IAS94; 1994; pp. 13101316. [11] - LETOR, R.; MELITO, M.; "Safe behavior of IGBTs subjected to dv/dt"; SGS-Thomson, Application Note, AN476/0492, 1994; pp. 715-723. [12] - SANTOS, A.; Driving high current IGBTs in high-power circuits, COBEP95, 3rd Brazilian Power Electronics Conference, December 4 to 7, So Paulo-Brazil, 1995; pp. 621-625. [13] - BARBI, I.; Projeto de fontes chaveadas; Publicao Interna, Florianpolis - UFSC - Brasil; pp. 31-58, 1990. [14] - BARBI, I.; ANDRADE, E. ;Projeto e implementao de um inversor para cargas no lineares; Relatrio Interno, UFSC- Brasil, Maro 1996.

MOTOROLA

SEMICONDUCTOR APPLICATION NOTE

Order this document by AN1540/D

AN1540 Application Considerations Using Insulated Gate Bipolar Transistors (IGBTs)

Prepared by: C.S. Mitter Motorola Inc.

DEVICE CHARACTERISTICS
The recently introduced Insulated Gate Bipolar Transistor (IGBT) has been undergoing considerable improvement and maturation due to improvement in process technology. This device has become the most popular new device used by the power electronics design engineers. It is quickly replacing most of the power BJTs because of its speed and ease of gate drive. In this section, a brief overview of the device and its characteristics will be presented. reduce this resistance and thus modulates its conductivity. The injected minority carrier density is typically 100 to 1000 times higher than the doping level of the ntype epitaxial drift region.
GATE EMITTER KEY METAL SiO2

POLYSILICON GATE

INTRODUCTION
P

In the power electronics arena there is a constant demand for compact, lightweight, and efficient power supplies. However, the demands for the power converters are not fully satisfied by power bipolar transistors (BJTs) and power MOSFETs. High current and high voltage BJTs are available, but their switching speeds are not satisfactory. Power MOSFETs have high speed switching, but high voltage and high current modules are not available. The Insulated Gate Bipolar Transistor (IGBT) device is a power semiconductor device introduced to overcome the limitations of the power BJTs and power MOSFETs. This device eliminates the high onstate losses of the MOSFET while maintaining the simple gate drive requirements of that device. This device is controlled by the gate voltage as is the power MOSFET, but the output current is that of a bipolar transistor. These devices combine the best features of both the bipolar transistors and of the MOSFET. In order to optimally implement all of the advantages of the IGBT device, it is essential that the designer understand the general operating characteristics of the device.

N+ rb

N+ P+

NPN

MOSFET
Rmod

P+

body

PNP

N EPI N+ BUFFER P+ SUBSTRATE bipolar emitter

COLLECTOR

Figure 1. Basic Structure of IGBT

GATE SOURCE KEY METAL SiO2

POLYSILICON GATE P N+

DEVICE STRUCTURE
A schematic structure of an Nchannel IGBT device is shown in Figure 1. The structure is similar to that of a Vertical Double Diffused MOSFET (VDMOSFET) with the exception that a ptype heavily doped substrate replaces the ntype drain contact of the conventional VDMOSFET (see Figure 2). The ptype substrate is the emitter of the bipolar transistor and is the anode terminal of the device. When sufficient gate voltage is applied, the current that flows at the surface of the MOSFET channel enters the low doped epitaxial layer and appears as a drain current at the substrate. In turn, the heavily doped p+ substrate injects minority carriers into the low doped n epitaxial layer. The large n area is needed in order to block high voltages, but it contributes to a large onstate resistance. But the minority carrier injection by the p+ substrate serves to
NPN
P+

JFET channel

N+ P+

body

DraintoSource Body Diode (Created when NPN baseemitter is properly shorted by source metal)

N EPI

N+ SUBSTRATE

DRAIN

Figure 2. Basic Structure of VDMOSFET

MOTOROLA Motorola, Inc. 1995

AN1540
The minority carriers, which do not recombine as they diffuse towards the body, are collected by the bodyepitaxial layer which is reversebiased in the forward conduction operation. The MOSFET channel is formed under the gate where the body meets the silicon surface, and this MOSFET provides the electrons (majority carrier) for recombination in the epitaxial layer and some are injected into the psubstrate region (bipolar emitter). The n+ buffer layer is introduced for the following reasons (we will not discuss it in detail in this paper): 1. Limit injection of holes into n region. This makes faster devices, but trades off forward drop. 2. Creates low lifetime region for recombination. This only affects speed of nonirradiated devices. 3. Prevents punchthrough of depletion region to p+ substrate. This allows thinner epitaxial to be used which lowers VCE(on). 4. Reduces PNP bipolar transistor gain which improves latching and prevents thermal runaway of leakage current at high temperature 5. Sets breakdown voltage of back junction Much of the discussions presented have been EPI type or punchthrough IGBTs because the basic understanding of the device centers around the EPI type IGBTs. IGBT Equivalent Circuit The simplified equivalent circuit representing the internal structure is shown in Figure 3. The circuit consists of an Nchannel MOSFET, a PNP bipolar transistor, an NPN bipolar transistor, and a JFET. (This is a conceptual model and should not be confused with the actual physical structure of the IGBTs.) The JFET is formed where the MOSFET current flows between two adjacent body diffusions [1]. This JFET supports most of the voltage and is highly modulated giving the MOSFET its low RDS(on). This JFET is represented by the modulated resistor Rmod. As shown in the model, the bipolar PNP and NPN form a four layer npnp structure of an SCR. If the gains of both transistors are significant enough, the BJTs will latch on and behave just like an SCR. But this latching process is avoided by the baseemitter short resistance, r b, in the equivalent circuit. This resistance acts as a shunt to the baseemitter junction of the NPN thereby preventing the NPN bipolar transistor from turning on strongly enough to start the latching process.
COLLECTOR EMITTER COLLECTOR

PNP

NPN GATE r b

Figure 4. IGBT Detailed Equivalent Circuit Showing the Parasitic Components Since the current to the base of the NPN bipolar transistor is bypassed, it can be assumed to be off, and this assumption results in the more simplified equivalent circuit as seen in Figure 4. This equivalent circuit only consists of a PNP bipolar transistor and the Nchannel MOSFET. The simplified equivalent circuit clearly shows that the drain current of the MOSFET (electron current) supplies the base current of the PNP. The sum of electron current and whole currents make up the total collector current of the IGBT device.

ADVANTAGES OF IGBT
Ease of Gate Drive As discussed previously, the IGBT combines the best features of the devices mentioned. It uses the lowpower, voltagedriven gate drive to turn on and turn off, and possesses a gate impedance as high as that of the power MOSFET. The structure of IGBT also reduces the reverse transfer capacitance, Cres, because a smaller chip area is required for a given current rating. This smaller capacitance results in a very low gate drive power requirement, since only a small gatedrain capacitance charging and discharging current is required (this is one of the real benefits of the IGBT). Low Conduction Loss The conductivity modulation of the n layer greatly increases the currenthandling capability of the IGBT for a given die size. This conductivity modulation has been shown to increase the forward conducting current density at given anode voltage up to 20 times that of an equivalent MOSFET and five times that of a BJT [2]. Because this process reduces the onresistance of the device, the conduction loss is minimized. The disadvantage of conductivity modulation is the increase in device switching time compared to the MOSFET due to stored charge in the wide base region. Positive Temperature Coefficient The IGBT also has a favorable temperature coefficient for onresistance. At high currents the onresistance increases with increase in temperature, and thus the device will not experience the thermal runaway which occurs in the power BJTs. (Note that under nominal and lower collector current range, the devices do have negative temperature coefficient.) It was shown that with increasing temperature, the current sharing of the devices in parallel operation is improved [3].

PNP

NPN GATE r b

EMITTER

Figure 3. IGBT Detailed Equivalent Circuit Showing the Parasitic Components

MOTOROLA

AN1540
No Internal Antiparallel Diode This can be advantageous or disadvantageous. With the absence of antiparallel diode which is present in power MOSFETs, IGBT can block reverse voltage (approximately 20 V); and with the use of series diode, reverse blocking capability can be greatly increased. The absence of this antiparallel diode protects the IGBT from reverse conduction problems in the freewheeling diode, which can occur in power MOSFETs. The designer has the freedom of selecting the optimum rectifier if it is needed in a freewheeling application.

CONCLUSION
The IGBT is a new power semiconductor device which possesses the best features of the both the MOSFET and bipolar transistor. The device is controlled by the same lowpower, voltagedriven gate as for the power MOSFETs, and the current handling is similar to that of BJTs. When operating in forward conduction, its conduction loss is reduced by the conductivity modulation achieved by the high level of minority carrier injection from emitter toward the wide base region of the device. It has been shown that the current density is 20 times that of power MOSFETs and five times that of BJTs. One disadvantage is the current tail during turnoff, and this introduces higher switching losses and limits the operating frequency of the device. At present, frequency of 25 kHz is obtainable without any special resonant switching technique.

DISADVANTAGE OF IGBT
Current Tail Even with many favorable qualities, the IGBT device possesses a few unwanted characteristics; one is the slow switching speed as compared to the power MOSFET. When the device operates in forward conduction, the high resistance region n epitaxial layer is highly modulated with injected excess minority carriers (conductivity modulation). When the gate voltage is removed, this excess of minority carriers must be removed before the device stops conducting completely. The turnoff speed of the device is determined by the integral bipolar openbase charge decay, and results in unwanted current tail (see Figure 5). This slow switching contributes to a large switching energy and limited operation frequencies. The turnon time is very fast and is determined by the rate of onvoltage saturation of the integral PNP bipolar transistor.

VCE IC

CURRENT TAIL

Figure 5. IGBT TurnOff Waveform

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IGBT GATE DRIVE CONSIDERATIONS
INTRODUCTION
Devices such as BJTs and thyristors require complicated and very inefficient methods of driving the devices due to their low gain and minority carrier device characteristics. In addition, SCRs become difficult to control due to loss of gate control during turnoff. But it is well known that MOSFETs have the simplest gate drive requirements of all the power devices mentioned. The device can be driven with low power, voltage pulses of required polarity. This simplifies the circuit design, and the switching characteristics can be accurately controlled if all of the circuit parameters are well known. Because IGBTs are much like fast MOSFETs during the switching transitions, and these devices undergo high voltage and high current transitions, its switching characteristics must be understood by the design engineers in order to avoid some of the problems associated with high voltage and high current transitions. In order to give design engineers a thorough overview of the device characteristics, this section reviews some of the switching characteristics within the clamped inductive load circuit. It is shown that the gate drive circuit, circuit layout, and external components play a vital part in controlling the device switching under clamped inductive load. By understanding the device characteristics and the problems associated with rapid di/dt and dv/dt, the designer can avoid some of the common problems. This paper covers some of the fundamental switching characteristics, and shows how critical the gate drive circuit is in determining the switching characteristics of the IGBTs. Some of the problems associated with rapid di/dt and dv/dt are discussed, and suggestions are presented in order to overcome these problems. The parameters that aggravate the problems associated with high di/dt and dv/dt have been shown to be DC bus inductance, common emitter inductance (common to gate drive circuitry), large gate return loop area, the series collector inductance, and the antiparallel diode of the clamped inductive load. All of these parameters contribute significantly to the durability and longevity of the devices, and can affect overall system efficiency. slope is dependent on gate voltage rise time and device forward transconductance. The following expression can be used to express the current slope: dIC dt GE . + gm dVdt (1)

The time rate of change in gateemitter voltage during t1 period is given by: dVGE dt Vplateau) + (VGG , RG @ Cies (2)

If we substitute equation 4 into equation 1, the rate of change of collector current is expressed as: dIC dt Vplateau) + gm (VGG . RG @ Cies (3)

DC SUPPLY

IL

LOAD

Ls

RG

IGBT

VGG Le DC RTN

Figure 1. Clamped Inductive Load

TURNON
Because the IGBT is a MOSgated device, the turnon switching performance is dominated by the MOS structure of the device. Figure 1 shows the clamped inductive load circuit used to analyze the switching characteristics of the IGBT. It is assumed that the inductor initially has a constant steady state current flowing through it, freewheeling through the diode. The inductance Ls is the series parasitic inductance due to the power trace and any wiring between the IGBTs collector and DC bus. The inductance Le is the common emitter inductance seen by both the power return and the gate return. Ideal switching waveforms describing the clamped inductive load circuit are shown in Figure 2. During the time period t0, the gate current charges the constant input capacitance (Cies) with a constant slope, and as is the case with the MOSFET, nothing happens until the gatesource voltage is raised to the threshold voltage Vth of the device. During t1, the collector current is redirected from the diode into the device and increases to its steady state value. The current
VGE t0 t1 t2 t3

t VCE IC

Figure 2. Idealized Turnon Switching of IGBT

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During the plateau region t2, the gateemitter voltage has reached the value which will support the steady state collector current, and the collectoremitter voltage starts to decrease. During this region, gate drive current is discharging the voltagedependent reverse transfer capacitance at a constant gate current that can be expressed as: ig plateau) CG . + Cres dVdt + (VGG RV G Vplateau IC , + Vth ) gm (4) the initial collector current rise because of its gate current limiting while increasing the turnon loss [4]. In order to overcome this problem, a small gate resistance is placed in series with the gate of the device, but remember that the inductance seen by the gate must be minimized. Placing the components as near as possible to the gateemitter terminals, along with good circuit layout, will reduce much of the unwanted inductance. Also, the gateemitter current loop must be short. It is good practice to use twisted wire or parallel power paths. Overlapping the power and return paths of the gate drive has the advantage of nullifying magnetic field induced by power trace with the magnetic field induced by the return trace and the effective loop inductance is minimized.

where,

(5)

and gm is the forward transconductance of the device at the given steady state collector current IC and can be obtained using the transfer curve provided by the data sheets. Transconductance is determined by steady state collector current divided by the intercepting gate voltage (IC/VGE, see Figure 3). It should be noted here that the above analysis ignores the change in bipolar current gain as base charge is supplied. The parameter for input capacitance Cies can be obtained using the capacitance curve provided by the device vendors. Figure 4 is a sample curve indicating the capacitance values for input, output, and reverse transfer capacitance Cres. A better method of obtaining the capacitance would be to use the gate charge transfer curve. By using the amount of charge needed to turn the device on at a certain operating point, more accurate assessment of gate drive current can be determined. A sample of a gate charge curve for an IGBT is shown in Figure 5, but for qualitative results the curve given by Figure 4 is adequate. All of the above expressions are presented to show the relationship between the series gate resistance and its effect on the rise time of the device current. Using these equations, the designer can control the current and voltage slope during turnon. During region t3 the dynamic switching is completed, and a further increase in gateemitter voltage has no effect on the dynamic characteristics. But, as we will discuss later, the final gateemitter voltage determines how much turnon loss is expended by the circuit and determines the magnitude and duration of short circuit current handled by the device. TurnOn Switching Considerations In order to reduce the dynamic turnon loss, the switching time must be very short. This requires that the gate drive be a low impedance type, and be able to provide a large narrow pulse of current to charge the input capacitance which includes the feedback capacitance and gateemitter capacitance. The turnon switching time is determined by how quickly the input capacitance Cies is charged. However, the fast switching speed will introduce high di/dt (maximum di/dt is a function of load inductance and the gate drive: 1) where initial di/dt = V/L, and once inductance has charged to its maximum load current, 2) the di/dt will be dominated by the gate drive) which will interact with the lead inductance of the emitter. The control of turnon di/dt can be seen by observing equation 5. In this equation it is evident that by changing the gate resistor value, the rate of the rise of the device current can be increased. This large di/dt will induce large enough transient voltage across the common emitter inductance and will reduce the available gate voltage causing linearization of

40 IC, COLLECTOR CURRENT (AMPS)

30

20

10

Transfer Characteristics
VCE = 100 V 5 s PULSE WIDTH TJ = 125C 25C 5 6 7 8 9 10 VGE, GATETOEMITTER VOLTAGE (VOLTS) 11

Figure 3. GateEmitter Voltage Due to Temperature Variation

4000 VCE = 0 V 3200 C, CAPACITANCE (pF) 2400 Cies 1600 800 Coes Cres 0

Capacitance Variation

TJ = 25C

0 5 10 15 20 25 GATETOEMITTER OR COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 4. IGBT Capacitance Curves

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GatetoEmitter and CollectortoEmitter Voltage versus Total Charge

VGE, GATETOEMITTER VOLTAGE (VOLTS) 16

12

Q1 0

QT Q2

VGE TJ = 25C IC = 20 A

collector voltage rises, and its rate of rise can be controlled by the gate resistance RG: dVCE dt plateau + CV . res @ RG (6)

Equation 6 assumes that the gate resistance is large enough that the output capacitance is not the limiting factor.

VGE

tdelay

0 20 40 60 Qg, TOTAL GATE CHARGE (nC) 80 Vth

Figure 5. Gate Charge Transfer Curve

VCE

Rapid di/dt not only limits the available gate voltage, but causes the bus voltage to dip, or decrease due to Ls(di/dt), where Ls is the stray inductance of the power DC bus. During turnoff, the rapid di/dt will cause a large positive voltage to be seen by the device which can exceed the rating of the device. Therefore, it is important to reduce di/dt during turnon and turnoff duration. A local bypass for the DC bus should be provided as near as possible to the device with a high current, low ESR capacitor. Without these precautions the IGBT may encounter avalanche breakdown due to di/dt induced transient during the turnoff time. Effect of the Freewheeling Diode Just as during turnoff, a surge can occur during the recovery of the freewheeling diode. For high di/dt, the reverse recovery of the diode can become very snappy. Because of the stray inductance within the circuit and the device leads, this large di/dt will cause a large dv/dt once the diode is recovered. The high di/dt caused by the snappy recovery of the diode can cause large unwanted voltage transients. Therefore, proper choice of the freewheeling diode is absolutely critical in the performance of the device. A snappy recovery can be controlled or eliminated by increasing the gate resistance RG, but this will increase the turnon time, and the efficiency of the circuit will suffer. Therefore, an ultrafast diode with a soft recovery must be chosen. Otherwise a snubber must be used to control the snappy recovery of the diode.

IC

CURRENT TAIL t4 t5 t6 t7 t

Figure 6. Idealized Turnoff Switching for IGBT At t6, the collector voltage has reached the bus voltage VDD, the freewheeling diode starts to conduct, and collector current starts to decay. Because of the high di/dt, the collector voltage rises beyond the bus voltage due to L(di/dt) overshoot. The region, t6, is the initial fall time, and this is the time required for the gate drive circuit to remove the charge that flows into the gate from the gatetodrain capacitance as VDS increases during turnoff. This period is greatly influenced by the gate drive design and its drive impedance, RG. For small gate resistance, period t6 is determined by the clamp inductance. This period is defined as the time it takes for Ic to drop from 90% of its full current down to approximately the 10% level (this will include the tail). This period is greatly influenced by the gate drive design and its drive impedance, R G, and the effect of RG on the collector current fall time is expressed as: dIC dt plateau + RV . G @ Cies (7)

TURNOFF
The turnoff of the IGBT is initiated by removing the voltage across the gateemitter just as for MOSFETs. Figure 6 shows idealized turnoff waveforms for switched inductive load. The first part of the turnoff process is the delay time (td(off)), which is the effect of the time required for the gate drive to pull VGE from its full value to the level at which the collector voltage begins to increase. Nothing is observed while gate voltage is decreased, until the gate voltage reaches the value required to keep the collector steady state current to flow. During t5, the

The time period t7 shows an abrupt decrease in current slope. This current slope is due to the recombination of the minority carriers in the wide base region of the integral BJT. This recombination process produces what is frequently termed as the current tail. This current tail limits the operation frequency of the IGBTs, and the size and length of this current tail is determined by the device design and process technology.

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TurnOff Considerations Just as with the MOSFETs a negative bias can be applied to the gate in order to speed up the turnoff. This does not mean that the recombination of minority carriers in the wide base region will be increased, but it helps to speed up the turnoff of the MOSFET portion, and thus turns off the base of the integral PNP bipolar transistor quicker. The rapid turnoff will cause a high dv/dt. The problem associated with high dv/dt is that it can introduce current through the capacitance to the base of the internal parasitic NPN bipolar transistor (only in a bad device), thereby causing the device to latch on. Once the device is latched on, the gatecontrol is lost and the device cannot be turned off without removing the power to the collector terminal of the device (see Figure 2). A small gateemitter resistance can be added to the terminals to bypass the dv/dt problem. Also a series resistor should be used when negative gate bias is applied during the turnoff process. The negative bias should be left on while the device is turned off. This will protect the device from the false turnon due to the dv/dt problem. Optimum values of the resistors can be found by trying different values of the resistor in the circuit to be used or by simulation. Effect of the Current Tail The t7 interval, as discussed earlier, is a result of minority carrier recombination in the bipolar PNP structure. IGBT is a minority carrier device during the forward conduction, and as such the highly resistive region (n epitaxial layer) is highly injected with minority carriers. This minority carriers must be removed before the device stops conducting completely. The turnoff speed of the device is therefore determined by the integral bipolar open base turnoff. This tailing effect is the direct result of the internal base of the PNP structure which cannot be accessed by the external means; and as a result, we cannot discharge the excess minority carriers by reverse biasing the gate. The controlled rate at which the minority carriers recombine is a function of device design and process technology. This current tail contributes to limit operational frequency and introduces large switching energy to be dissipated by the device. How fast the minority carriers recombine determines how long the current tail is and the turnoff speed of the device.

CONCLUSION
IGBTs are excellent candidates for high power applications. However, when switching high voltage and high current, care must be taken in the beginning stage of the design to ensure that circuit layout will support the high di/dt and dv/dt. Some equations have been provided so that by using appropriate gate resistors, di/dt and dv/dt can be controlled. It was observed that the gate drive is a vital element in obtaining the maximum performance of the device. Through the correct use of gate drive the designer can overcome some of the common problems associated with high voltage high current switching: 1) accurately control di/dt and dVCE/dt problems, and 2) avoid latching of the parasitic thyristor. Using a negative bias at the gate reduces the chance of false turnon and latching of the device. Not only was the gate drive vital in determining the switching loss, but the freewheeling diode in a clamped inductive load introduces turnon switching losses. It is of utmost importance that an ultrafast diode with soft recovery type be chosen. Layout of the circuit was vital in overcoming some of the switching problems. The ground loop of the gate drive must be separated from the power return so that the common emitter inductance does not interrupt the turnon process. The twisted wires or parallel power tracts should be used for the gate drive. In order to reduce any unwanted supply bus inductance, it was suggested that a bypass capacitor with low inductance and low ESR be connected right at the device level, or just as in gate drive, the supply bus tracks can be paralleled. By following some of these recommendations, many of the common problems associated with high current and high voltage switching can be dramatically reduced.

GATE DRIVE REQUIREMENTS

From the previous discussion of switching characteristics of the IGBT, the following have arisen as the important factors that need to be considered when designing the gate drive: 1. Reduce the gateemitter current loop by separating the power return and gate return 2. Use a twisted wire if possible and overlap the power traces of gate drive if PCB is used 3. Make the gate drive connection as short as possible to the device being used so as to reduce any parasitics 4. Use a series gate resistor, RG to limit di/dt and dv/dt 5. Use a negative bias if possible to reduce any dv/dt problems

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EFFECT OF GATEEMITTER VOLTAGE ON TURNON LOSS AND SHORT CIRCUIT CAPABILITY
INTRODUCTION
Unlike the MOSFETs and BJTs, the magnitude of the gateemitter supply voltage of an IGBT has a significant impact on the performance of the device. The magnitude of the gate voltage impacts the turnon loss and short circuit survival capability of the devices. In this section some of the impacts of the gateemitter voltage on the device performance will be examined. device, while the gate potential is at full operating value (see Figure 2). Because of the high gain characteristic of the IGBTs, the collector current will rise to some undetermined value limited by the gateemitter voltage. During this time the device will have a large amount of energy across the device, and if the energy is beyond the capability of the device it will be destroyed due to thermal breakdown. For the bad devices, the large current can cause parasitic NPN bipolar transistor to turn on and cause the device to latch, wherein the gate control will be lost. One point to note here is that the IGBTs are less sensitive to second breakdown due to hot spot formulation unlike the BJTs. In understanding this, it is clear that the device should be able to survive a short circuit condition if the energy delivered to the device is maintained below some value that is tolerable to the device. There are many different ways to protect the device from the short circuit condition for some duration. Remember that the device does not turn off when a short circuit occurs, but rather limits the amount of the energy dissipated by the device by limiting the collector current. This provides enough time for the external protection circuits to be activated. Therefore it is of utmost importance that the device be able to survive a short circuit fault condition. The most effective way to provide the short circuit survivability would be to inherently build current sensing capability into the device, but as of now, no manufacturer has any device which has builtin current sense for short circuit detection. IGBTs produced by Motorola are capable of short circuit survivability of 10 s minimum. Another method of increasing the short circuit survivability is to decrease the gate voltage when the short circuit across the device is observed. Figure 3 data shows the relationship between the gate voltage, short circuit current, and the short circuit survival time period. As shown in Figure 3, it is clear that the smaller gate voltage limits the current at lower value and increases the short circuit time duration.

TURNON LOSS
As mentioned before, the turnon characteristics of IGBTs are similar to those of a MOSFET. In MOSFETs, once the gatesource voltage has reached the value to support the steadystate drain current, a further increase in VGS has no significant role in the circuit, but it does greatly affect the switching speed of the device. The magnitude of the gateemitter voltage significantly affects the magnitude of the turnon loss during the transition. Figure 1 depicts measured data that shows the relationship between gateemitter voltage and turnon loss with a constant RG, 20 ohms. As shown by the curves, larger gateemitter voltage reduces the turnon loss of the device. This can be explained by the fact that for a given gate resistor, the gate current available increases with the increase in the gate voltage. Therefore, the input capacitance of the device is charged at a faster rate which can account for less loss. The longer it takes the device to turn on, the more energy is dissipated by the device. For given collector currents, increase in gateemitter voltage reduces turnon loss.
50 45 40 Eon , (NORMALIZED) 35 30 25 20 15 10 5 0 0 2 4 6 8 10 12 IC IN AMPS 14 16 18 20 20 V 15 V 17 V RG = 20 OHMS 12 V

SHORT CIRCUIT FAULT VDD

VGG

Figure 1. Turnon Loss with Different GateEmitter Voltage Figure 2. Equivalent Short Circuit Condition

SHORT CIRCUIT FAULT OPERATION

A major concern in inverter applications is the ability to survive a short circuit fault condition. During the short circuit fault, the device is exposed to the supply voltage across the

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SUMMARY
Short Circuit Time & Current versus Gate Voltage
80 ISC 40

60 I SC IN AMPS

30 t SC IN s

40

20

20 tSC 0 10 11 12 13 14 15 16 VG IN VOLTS 17 18 19

10

0 20

IGBTs are high current and high voltage devices. Because of their use in high power applications, it is important that some of the key behavior of the device is understood by the user in order minimize switching losses and to prolong their lifetime. In most cases, the turnon loss of the device in a clamped inductive load is dependent on the performance of the freewheeling diode, and is a function of the diodes reverse recovery time. But as we have discussed, the magnitude of the gateemitter voltage can be optimized in order to reduce the turnon loss of the device. But on the other hand, the designer needs to understand that the high gateemitter voltage reduces the short circuit survivability of the device. Using these two relationships, the designer can choose the best voltage value which will meet their design requirements.

Figure 3. Short Circuit Response of IGBT

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FORWARD CONDUCTION AND TURNOFF BEHAVIOR OF IGBTS AT HIGH TEMPERATURE AND ITS CONTRIBUTIONS TO STATIC AND DYNAMIC TURNOFF LOSS
INTRODUCTION
IGBTs have been introduced to overcome the high onstate voltage of MOSFETs and slow switching frequency of BJTs. But because IGBTs possess dual device characteristics, their behavior is not easily understood. In high current applications, the onstate voltage becomes a major issue, and, in other cases switching losses may be the major concern. In this section the onstate voltage characteristics and dynamic turnoff will be discussed. It is shown that the unique characteristics of the IGBTs allow the designer to operate the device to obtain low conduction loss. But also shown are that dynamic turnoff losses must be taken into consideration with variation in temperature. During the turnoff at high temperatures close attention must be given to: 1) current tail variation, 2) initial current height of the anode current, 3) reduced rate of rise of anode voltage, 4) and increased carrier lifetime. All of these add to the turnoff energy loss and can damage the device if care is not taken. coefficient, and as a result the saturation voltage is decreased with increase in temperature. At some current level, the two curves cross each other and at this crossover point VCE becomes temperature independent. At higher current levels, the device possesses a positive temperature coefficient characteristic and its saturation voltage increases with increase in temperature. At high temperature, there are a few important things that are happening which contribute to the device onvoltage. It was discussed by Hefner [5] that: 1) the base resistance increases with temperature due to decrease in the mobility of the carriers, 2) emitterbase junction diffusion voltage decreases due to increase in base intrinsic carrier concentration, 3) the drainsource voltage increases slightly with temperature because the decrease in MOSFET transconductance dominates the decreasing threshold voltage for the high gate voltage bias condition. The onvoltage of the device decreases with temperature at lower current levels because the base resistance and channel resistance is small compared to the change in emitterbase junction diffusion voltage. The BJT characteristics of the device are dominating at this point. But for higher current levels, the base resistance and channel resistance start to become significant enough and dominate the onvoltage of the device, and as a result, introduce the positive temperature coefficient which is a MOSFET effect of the device. If the operating current is within the negative temperature coefficient region, one can be mistaken in thinking that operating the device at a higher temperature will be much more efficient. This may be true if other factors such as conduction current, thermal environment, circuit layout, and other operating parameters have been considered. But as we will later see, dynamic turnoff must be considered at high temperature operation

FORWARD CONDUCTION
Because IGBTs behave like MOSFETs in switching transitions, it can be misunderstood that the device always possesses a positive temperature coefficient (that is, the onvoltage increases at higher temperature). This perception is partially correct. As we shall see the device actually possesses negative temperature coefficient at low current levels.
60 IC, COLLECTOR CURRENT (AMPS) VGE = 20 V TJ = 25C 40 TJ = 125C

TURNOFF
20

2 4 6 VCE, COLLECTORTOEMITTER VOLTAGE (VOLTS)

Figure 1. IGBT Output Characteristics IGBTs possess aspects of both MOSFET and BJT characteristics. Figure 1 shows the temperature dependence of collector current versus collectoremitter voltage. For low current levels, the device possesses a negative temperature

Unlike the relatively temperature insensitive forward voltage drop of the device, the turnoff energy loss is increased with temperature. Figure 2 shows the dramatic increase in turnoff loss at high temperature. This increase in energy loss is contributed largely by the increase in the current tail. The current tail is a function of the base minority carrier lifetime and is increased with rise in temperature. Not only is current tail length increased, but the storage time, dVC/dt, and initial anode current tail height is also increased. These effects all contribute to higher turnoff energy loss, and attention should be given by the designers using the IGBTs. By understanding how the device behaves with the temperature at turnoff, the design engineer can better assess the best operating parameters for a given application.

10

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Turnoff Losses versus IC

125C 25C 16 18 20

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For nonbuffered devices, the increase in the base charge with temperature is negated by the corresponding decrease in the diffusivity. But in the buffered devices, the increased charge due to the temperature is greater than the decrease in the diffusivity of the device, and as a result, the initial current magnitude varies with temperature. The variation in initial current height and in current tail length is the major contributor to the turnoff energy loss. Figures 4 and 4b show turnoff waveforms at two different temperatures. The data shows that the initial current height and current tail is increased significantly at higher temperatures. This increase in the current tail length and initial current height contributes to a larger turnoff energy loss.

10 12 IC in AMPS

14

Figure 2. Turnoff Energy Loss at Different Temperatures Current Tail With an increase in temperature, the mobility of the minority carriers in the wide base is reduced, and the lifetime is increased which prolongs the current tail during the turnoff of the transistor. The increase in the current tail can account for almost 60% of the turnoff loss. Not only is more energy dissipated by the device, this will reduce the operating frequency of the device. Figure 3 depicts the anode current during the turnoff. The initial current height is denoted by IT(0+) and is the time at which the current tail starts to decay exponentially. For devices which do not have the buffer layer, the initial height of current tail remains relatively constant and with temperature only current tail length is increased. But for devices with the buffer layer, this initial tail height increases with the temperature. Both the increased height and length of tail with temperature means that the device will turn off slower. It was discussed that the IT(0+) is proportional to the base charge Q, and diffusivity of the device [6]: IT (0+) Q D (1)

VCE IC VCE: VGE: IC: TIME: 50 V/div 5 V/div 2 A/div 250 ns/div

VGE CURRENT TAIL

Figure 4a. Turnoff Waveforms at 25C

VCE IC VCE: VGE: IC: TIME: 50 V/div 5 V/div 2 A/div 250 ns/div

VGE IT (0) IT (0+)

Initial Current Tail Increased Due to Increased Temperature

ANODE CURRENT

IF

Figure 4b. Turnoff Waveforms at 120C

TIME

Figure 3. Anode Current During Turnoff

Collector Voltage Transitions In the previous paragraphs it has been discussed how the increase in device temperature decreases the mobility and increases the lifetime of a device. This increase in lifetime also increases the current tail length and its associated initial current height. But as we shall see, the rate of rise of the anode voltage is also affected by the temperature due to increase in the lifetime, and adds to total turnoff loss.

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Figure 5 shows an equivalent schematic of IGBT showing all of the internal circuits associated with the device. During the turnoff, the output capacitance is dominated by the collector emitter redistribution capacitance, Ccer. This capacitance is orders of magnitude larger than the depletion capacitance and dominates the effective output capacitance of the IGBT during turnoff. Because this capacitance is charge dependent, its value is varied with change in temperature (charge is varied with temperature). At high temperature, the increase in charge increases the effective output capacitance and thus decreases the rateofrise of the collectoremitter voltage. The following equation can be expressed as: Ibase Storage Time Other side effects of the decrease in the rateofrise of the voltage is that it prolongs the storage time. In a clamped inductive load, the collector voltage must reach its full supply voltage value before the collector current starts to decay (see Figure 5). The decrease in dVCE/dt causes the collector current to remain at its full steadystate value much longer, and hence increases the turnoff loss.

FURTHER DISCUSSION ON TEMPERATURE EFFECT

Figure 6 shows all of the phenomenon that has been discussed previously. The first thing to note is that the initial current tail magnitude has increased dramatically. But also note that the storage time has been increased due to the decrease in dVCE/dt. As shown in Figure 6, dVCE/dt is decreased by a factor of two, and is independent of gate voltage after t6 region (it is assumed that there is no significant variation in gate drive performance with variation in temperature). Notice the lack of voltage overshoot due to decrease in the slopes. Figures 7 and 8 are measured data showing the effect of temperature variation during the turnoff. All of the phenomenon discussed are apparent during the turnoff transition. One important factor to remember is that the device was operated only at 50% of its rated voltage. If the collector voltage is increased, the turnoff loss encountered can increase much more which will then increase the junction temperature of the device. (See Figure 9.) So special care should be given to the turnoff transition if the device is to operate efficiently under temperature variations.

Q . THL

(2)

Current Ibase is a steady state current level, charge Q is charge present in the base, and tHL is the excess carrier lifetime. With increase in temperature, the whole lifetime is increased due to reduction of mobility of carriers within the base region. The increase in the base lifetime means that the charge must increase in order to provide the unchanged collector current. During the voltage transition, the effective output capacitance and rateofrise of the anode voltage must be able to supply the steadystate collector current. Since the capacitance is proportional to the amount of charge present, its value is increased accordingly. Larger capacitance then decreases the rateofrise of the anode voltage because it takes longer to charge the bigger capacitance. The rateofrise of the collector voltage is an inverse function of the capacitance, and the following expression can be used to describe its dependency on charge and capacitance: dVC dt 1 1 T Ccer TQ (3)

VGE
CATHODE GATE

STORAGE TIME 25C

Cm n+ c Cdsj b n BJT Rb Cebj + Cebd p+ e ANODE Ads Agd d Coxs s MOSFET Coxd Cgdj

125C

Vth

t 25C IC VCE 125C CURRENT TAIL t7 t4 t5 t6 t

p+ Depletion Ccer Region

Figure 6. Turnoff Behavior of IGBT with Temperature Variations

Figure 5. IGBT Equivalent Circuit Superimposed on Onehalf of Symmetric IGBT Cell (Reprinted with permission from NIST)

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CONCLUSION
VCE IC VCE: VGE: IC: TIME: 50 V/div 5 V/div 2 A/div 25 ns/div

Figure 7. Turnoff at 25C (VDD = 300 Vdc)

IGBTs have very unique characteristics which can be utilized to best meet many of the high power switching applications. But unlike BJTs and MOSFETs, it is not straightforward when it comes to designing for temperature variations. One must not only look at the onstate voltage, but one also needs to consider the dynamic behavior of the device with temperature. How well the device temperature is stabilized determines how rugged the device will be. If the environment is such that temperature variation is minimal (and can be guaranteed), the design can be optimized for the onstate voltage because the turnoff energy loss variations will be small. But if the temperature stability is not guaranteed, the designer needs to consider all of the parameters discussed and great care should be given to device junction temperature. The design should be done by derating the part for the worst case condition which the device will confront. If care is not taken, one can be assured of device failure or degraded performance. The following are some of the considerations that should be taken when using IGBTs: 1. 2. 3. 4. 5. 6. 7. 8. Temperature environment of the circuit Device characteristics with temperature variations Increase of storage time Decrease of dVC/dt Increase in initial current tail height Increase in total current tail length Operating current of the device Operating frequency

VCE IC VCE: VGE: IC: TIME: 50 V/div 5 V/div 2 A/div 25 ns/div

VGE

Considering these factors will help the design engineers to better utilize all of the benefits of IGBTs.

Figure 8. Turnoff at 120C (VDD = 300 Vdc)

IC VCE VGE: IC: TIME: 100 V/div 5 V/div 2 A/div 25 ns/div VGE

VCE

Figure 9. Turnoff at 120C (VDD = 500 Vdc)

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IGBT PARALLELING CONSIDERATIONS
INTRODUCTION
Paralleled IGBTs are used extensively in power modules to obtain higher current ratings [3], thermal improvements, and for redundancy. However, the typical process variation of device parameters within a given device type is significant enough to result in uneven static and dynamic current sharing if the paralleled devices are chosen randomly from a given lot of IGBTs of the same type. Design engineers must make sure that the temperature variations do not significantly vary the significant device parameters, and caution must be observed. Aside from the temperature and device parameter variations, it is well known and much has been written about how the circuit layout and its contribution can greatly influence the performance of devices in parallel operation. In this section the characteristics of IGBTs under parallel operation are shown. The effect of device parameter variations under static and dynamic current sharing are studied, and the effect of temperature and circuit layout are discussed. Then some suggestions are presented on how to overcome the common problems associated with paralleling IGBT devices. It is shown that if the designer considers careful circuit layout, thermal considerations, and pays careful attention to process variations within the given lots, many of the problems associated with the paralleling power IGBT devices can be avoided. Many of the papers written about parallel operations of IGBTs concern the effect of temperature variations. It is true that temperature is the key role player in the destruction of IGBT devices. But it is unclear as to what or how the temperature is changing the device characteristics. The IGBTs have the dual device (MOSFET and BJT) characteristics, and in order to truly understand the temperature effect on paralleling, it is necessary to understand how the temperature changes the characteristics of each device type. In this way the designer is better informed and will be able to better design for key parameters.
LOAD RL DC SUPPLY Ls1 RG1 Q1 Q2 Ls2 RG2

VGG

Le1

Le2

DC RTN

Figure 1. Paralleled IGBTs Used in Inductive Load turnon transitions, but the current imbalance during the steadystate region, and turnoff variations are observed. The device with the higher lifetime conducted more current than the device with lower lifetime. Because of this higher lifetime, more charge is stored in the wide base region, and thus decreases the saturation voltage. With its lower VCE(sat), it draws more of the load current. No significant current spike is observed during the turnoff transition, but as expected the device with higher lifetime had a larger current tail because more charge had to be removed.

HIGH LIFETIME IC1 IC2 LOW LIFETIME VCE

PARAMETER VARIATIONS
In order to observe how the dissimilar parameters affect current sharing of the paralleled IGBTs, the parameters lifetime tHL, threshold voltage Vth, and transconductance Kp, were varied between two different devices. These parameters were chosen because the normal process variation of these parameters has the most impact on current sharing for parallel operation [7]. The circuit used to simulate and test the parallel operation of IGBTs is shown in Figure 1. The inductors LS1, LS2, Le1, and Le2 are the inductances due to lead and power traces. The load resistor RL is used to limit the collector current to a safe level. It is shown that these parasitic components have a significant role in the operation of the IGBTs. Variations in Lifetime The effect of lifetime on the IGBT is through the bipolar characteristics of the device. In order to understand how the lifetime variation behaved in parallel operation of IGBTs, two devices with dissimilar lifetimes were observed. Figure 2 shows a waveform of collector voltage and collector current of both device types. The difference in lifetime has no effect on Figure 2. Paralleled Operation of IGBTs with Lifetime Variation

Temperature Effect on the Lifetime Variations. With increase in temperature the lifetime increases. Figure 2 shows that if the static current sharing is within the tolerable region, there is no problem associated due to lifetime variations. During the turnoff sequence, the length of the current tail of the device with higher lifetime is increased. This increase in current tail will increase the turnoff loss of that device but should not have significant effect on the static current sharing if the parameter variation is minimal. But if the devices have wide variation in the lifetime, the device with the higher lifetime can encounter thermal breakdown (for example, paralleling an ultrafast IGBT with a slow IGBT). The thermal effect of the device is overcome by using the same heatsink for both devices and the temperature feedback between the devices will keep the current sharing very constant because the lifetime of both devices will vary together and one will track the other constantly. Because the current tail is the same in a paralleled configuration as for a single device, the destruction
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of the device due to life time variation is the same as for single devices used in a scaled down circuit. If the designer did not consider the temperature effect of the current tail, VCE(on), and the energy loss, the device may fail due to excessive energy dissipated by the device at high temperature. However, in a parallel operation, unless a large quantity of the devices are paralleled for very high current levels, the failure of the device in paralleled operation would be the same as in a single device operation. Threshold Voltage and Transconductance Variation Threshold voltage and transconductance are MOSFET characteristics. Two devices with different MOSFET threshold voltages and transconductance were chosen, and the resultant waveform is shown in Figure 3. The turnon delay occurs for the higher threshold voltage device because it takes longer for the gate voltage to charge up the gateemitter capacitance to its threshold voltage. Not only does the threshold voltage cause the delay, but the lower transconductance will cause delay during the turnon because the device resistance is higher than the other device until its gate voltage becomes large enough so that the onstate resistance of both devices are primarily determined by the bipolar emitterbase voltages. The static portion of the waveform shows a current imbalance, and the device with the higher transconductance conducts more current because its onresistance is lower than the other device. At turnoff, a current spike exists for the device with the larger transconductance and smaller threshold voltage. The turnoff current spike in the higher transconductance device occurs because the resistance of the lower transconductance device becomes larger sooner than for the high transconductance device, and the inductor current is transferred to the lower resistance device. The turnoff current spike introduced by variation in transconductance and threshold voltage can be detrimental to the device if its SOA has been exceeded. amount of current seen by the device will be changed very little or not at all. But if the current level is high enough, the MOSFET effect will dominate and the device VCE(sat) will increase with temperature. This increase in onresistance of the device will cause the other device to take more of the current, and thereby always keep the currentsharing well balanced. Unless the parameters are significantly different, static current sharing is well balanced from device to device. During turnoff, however, the device with higher transconductance will conduct most of the current because the MOSFET channel resistance dominates during switching. If the variation in transconductance is wide enough, one of the devices can be destroyed due to excessive current spike. Just as for the transconductance, the threshold voltage of the IGBT will decrease with the increase in temperature. Just as variation in transconductance will introduce turnoff current spike, large variation in threshold voltage can cause dynamic current imbalance because one device will turn off faster than the other device. During the static operation, the threshold voltage will have no effect. However, the decrease in transconductance counterbalances the effect of the decrease in threshold voltage, and the current spike is independent of the temperature.

USING COMMON HEATSINK

With common heatsink, the parameter variation in both devices will approximately be equal, and as a result, the dynamic turnoff current imbalance will not be improved significantly if the designer did not pay attention to the Vth and Kp. In fact, using a separate heatsink will actually improve the dynamic current sharing for the IGBTs. Static current sharing is greatly improved in IGBTs because the lifetimes of the devices tend to increase proportionally to other devices with temperature. Using a common heatsink will improve the static current sharing, but large dynamic instability can still be introduced if Kp and Vth variation is not minimized.

EFFECT OF CIRCUIT LAYOUT

Just as in normal operation of the single device, the circuit layout is very important in the parallel operation of the devices. Large variation in commonemitter inductance has been shown to be the biggest contributor to the cause of dynamic current imbalance of the devices. If one of the devices emitterground inductance is large while the other device sees low inductance, a large current spike is observed by the lower inductance device because it turns on much faster than the other. It was discussed earlier that the large emitter inductance introduces large voltage drop and results in clamping of the gate current during the turnon. So more of the gate current is diverted to the device with lower commonemitter inductance. With the interaction of parasitic capacitors and nonlinear voltagedependent junction capacitance of the devices, it will oscillate with large commonemitter inductance. This will be sensed by the other device, and they will together oscillate out of phase with each other.

HIGH Kp/LOW Vth IC1 IC2 LOW Kp/HIGH Vth

VCE

Figure 3. Paralleled Operation of IGBTs with Kp and Vth Varied

Temperature Dependency of Vth and Kp. With an increase in temperature, both of the parameters will be decreased. For a highgate voltage, the onstate voltage will tend to increase with temperature, but because the IGBT has dual device characteristics, the BJT emitterbase voltage decreases with temperature due to the increase in intrinsic carrier concentration. The decrease in BJT emitterbase voltage will negate the decrease in transconductance, and as a result, the

EFFECT OF GATE RESISTANCE

If separate gate resistors are used for each device, it will introduce a variation in delay time (or storage time). The device with longer turnoff time will stay on longer, and the lower storage time device will transfer its current to the other

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device. This will introduce more power dissipation in one device and introduce thermal instability if separate heat sinks are used. If careful attention has been given to the circuit layout, and commonemitter inductance has been minimized, using a singlegate resistor for both devices will reduce the turnoff storage time variation because the device with higher storage time will keep the other device conducting to a value which is dependent on the device transconductance.

ACKNOWLEDGMENTS
The author wishes to thank the following people for their inputs and many interesting discussions: Steve Robb, Bill Fragale, Scott Deuty, Kim Gauen, Rahul Chokhawala, Rodrigo Borras, and special thanks to A. R. Hefner for many long and interesting telephone conversations which have been so valuable to the materials in this paper.

SUMMARY
Many of the problems associated with paralleling of power devices can be greatly reduced by using IGBTs. It has been shown that the device characteristics of the IGBT device favors parallel operation as opposed to BJTs. Its dual device characteristics can be utilized to give design engineers very satisfactory performance under static and dynamic current sharing of the devices. Problems associated with paralleling IGBTs can be minimized and deterred if careful attention is given to parameter variations, careful circuit layout (minimizing parasitic inductance), and using common heatsinks. Remember that using a common heatsink does not improve the dynamic current imbalance if parameter variations of Kp and Vth are large. Static current sharing is increased with the use of common heatsink. Most of the failure of the devices in paralleled operation can be contributed to neglect of device temperature effect and not derating the parts as they should have. In summary, the following criteria should be met for paralleling IGBTs: 1. Minimize the spread of lifetime, Kp, and Vth between the devices to be paralleled 2. Minimize the commonemitter inductance difference 3. Take all the precautions just as if the devices were operating as single devices 4. Use single gate resistors to drive the gates to reduce the storage time variations 5. Use a common heatsink for all of the devices 6. Understand which characteristics will dominate the parallel operation (BJT or MOSFET) 7. Calculate the junction temperature using worst case numbers

REFERENCES
[1] Hefner, A. R. Characterization and Modeling of the Power Insulated Gate Bipolar Transistor, PhD. Dissertation (July 23, 1987), pp. 1718. Baliga, B. J. Temperature Behavior of Insulated Gate Transistor Characteristics. Solid State Electronics, Vol. 28, no. 3. (1985), pp. 289297. [2] [3] Letor, Romeo. Static and Dynamic Behavior of Paralleled IGBTs. IEEE Trans. Industry Applications, Vol. 28 (1992), pp. 395402. [4] Rinehart, Larry and Heron, Chuck. Application Advantages Using IGBT Technology, App Note, IXYS Corporation Hefner, A. R. A Dynamic ElectroThermal Model for the IGBT. IEEE Trans., Vol. 30 (1994), pp. 394405. [5] [6] Hefner, A. R. An Improved Understanding for the Transient Operation of the Power Insulated Gate Bipolar Transistor (IGBT). IEEE Power Electronics Specialists Conf. (1989), pp. 303. [7] Mitter, C. S., Hefner, A. R., Chen, D. Y., and Lee, F. C. Insulated Gate Bipolar Transistor (IGBT) Modeling Using IGSpice. IEEE Trans. Industry Applications, Vol. 30 (1993), pp. 2433.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters can and do vary in different applications. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.

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MOTOROLA AN1540/D

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SEMICONDUCTOR APPLICATION NOTE

Order this document by AN1541/D

AN1541 Introduction to Insulated Gate Bipolar Transistors

Prepared by: Jack Takesuye and Scott Deuty Motorola Inc.

INTRODUCTION
As power conversion relies more on switched applications, semiconductor manufacturers need to create products that approach the ideal switch. The ideal switch would have: 1) zero resistance or forward voltage drop in the onstate, 2) infinite resistance in the offstate, 3) switch with infinite speed, and 4) would not require any input power to make it switch. When using existing solidstate switch technologies, the designer must deviate from the ideal switch and choose a device that best suits the application with a minimal loss of efficiency. The choice involves considerations such as voltage, current, switching speed, drive circuitry, load, and temperature effects. There are a variety of solid state switch technologies available to perform switching functions; however, all have strong and weak points. The IGBT is, in fact, a spinoff from power MOSFET technology and the structure of an IGBT closely resembles that of a power MOSFET. The IGBT has high input impedance and fast turnon speed like a MOSFET. IGBTs exhibit an onvoltage and current density comparable to a bipolar transistor while switching much faster. IGBTs are replacing MOSFETs in high voltage applications where conduction losses must be kept low. With zero current switching or resonant switching techniques, the IGBT can be operated in the hundreds of kilohertz range [1]. Although turnon speeds are very fast, turnoff of the IGBT is slower than a MOSFET. The IGBT exhibits a current fall time or tailing. The tailing restricts the devices to operating at moderate frequencies (less than 50 kHz) in traditional square waveform PWM, switching applications. At operating frequencies between 1 and 50 kHz, IGBTs offer an attractive solution over the traditional bipolar transistors, MOSFETs and thyristors. Compared to thyristors, the IGBT is faster, has better dv/dt immunity and, above all, has better gate turnoff capability. While some thyristors such as GTOs are capable of being turned off at the gate, substantial reverse gate current is required, whereas turning off an IGBT only requires that the gate capacitance be discharged. A thyristor has a slightly lower forwardon voltage and higher surge capability than an IGBT. MOSFETs are often used because of their simple gate drive requirements. Since the structure of both devices are so similar, the change to IGBTs can be made without having to redesign the gate drive circuit. IGBTs, like MOSFETs, are transconductance devices and can remain fully on by keeping the gate voltage above a certain threshold. As shown in Figure 1a, using an IGBT in place of a power MOSFET dramatically reduces the forward voltage drop at current levels above 12 amps. By reducing the forward drop, the conduction loss of the device is decreased. The gradual rising slope of the MOSFET in Figure 1a can be attributed to the relationship of VDS to RDS(on). The IGBT curve has an offset due to an internal forward biased pn junction and a fast rising slope typical of a minority carrier device. It is possible to replace the MOSFET with an IGBT and improve the efficiency and/or reduce the cost. As shown in Figure 1b, an IGBT has considerably less silicon area than a similarly rated MOSFET. Device cost is related to silicon area; therefore, the reduced silicon area makes the IGBT the lower cost solution. Figure 1c shows the resulting package area reduction realized by using the IGBT. The IGBT is more space efficient than an equivalently rated MOSFET which makes it perfect for space conscious designs.

HIGH VOLTAGE POWER MOSFETs

The primary characteristics that are most desirable in a solidstate switch are fast switching speed, simple drive requirements and low conduction loss. For low voltage applications, power MOSFETs offer extremely low onresistance, RDS(on), and approach the desired ideal switch. In high voltage applications, MOSFETs exhibit increased RDS(on) resulting in lower efficiency due to increased conduction losses. In a power MOSFET, the onresistance is proportional to the breakdown voltage raised to approximately the 2.7 power (1). MOSFET technology has advanced to a point where cell densities are limited by manufacturing equipment capabilities and geometries have been optimized to a point where the RDS(on) is near the predicted theoretical limit. Since the cell density, geometry and the resistivity of the device structure play a major role, no significant reduction in the RDS(on) is foreseen. New technologies are needed to circumvent the problem of increased onresistance without sacrificing switching speed. R DS(on) 2.7 T VDSS (1)

ENTER THE IGBT

By combining the low conduction loss of a BJT with the switching speed of a power MOSFET an optimal solid state switch would exist. The InsulatedGate Bipolar Transistor (IGBT) technology offers a combination of these attributes.

MOTOROLA Motorola, Inc. 1995

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PEAK CURRENT THROUGH DEVICE (AMPS) 40 35 30 25 20 15 10 5 0 0 2 4 6 FORWARD DROP (VOLTS) 8 10 VDS MTW20N50E MOSFET VCE(sat) MGW20N60D IGBT AREA (SQ. INCHES) 0.10

0.05

Figure 1b. Reduced Die Size of IGBT Realized When Compared to a MOSFET with Similar Ratings
0.60

IGBT DIE SIZE (0.17 X 0.227) MOSFET DIE SIZE (0.35 X 0.26) 1

AREA (SQ. INCHES)

Figure 1a. Reduced Forward Voltage Drop of IGBT Realized When Compared to a MOSFET with Similar Ratings When compared to BJTs, IGBTs have similar ratings in terms of voltage and current. However, the presence of an isolated gate in an IGBT makes it simpler to drive than a BJT. BJTs require that base current be continuously supplied in a quantity sufficient enough to maintain saturation. Base currents of onetenth of the collector current are typical to keep a BJT in saturation. BJT drive circuits must be sensitive to variable load conditions. The base current of a BJT must be kept proportional to the collector current to prevent desaturation under highcurrent loads and excessive base drive under lowload conditions. This additional base current increases the power dissipation of the drive circuit. BJTs are minority carrier devices and charge storage effects including recombination slow the performance when compared to majority carrier devices such as MOSFETs. IGBTs also experience recombination that accounts for the current tailing yet IGBTs have been observed to switch faster than BJTs. Thus far, the IGBT has demonstrated certain advantages over power MOSFETs with the exception of switching speed. Since the initial introduction of IGBTs in the early 1980s, semiconductor manufacturers have learned how to make the devices faster. As illustrated in Figure 2, some tradeoffs in conduction loss versus switching speed exist. Lower frequency applications can tolerate slower switching devices.
3.5 3.0 VCE(sat) (VOLTS) 2.5 2.0 1.5 1.0 0.5 0 0 HIGH SPEED SERIES

0.40

0.20

Figure 1c. Reduced Package Size of IGBT Realized When Compared to a MOSFET with Similar Ratings Because the loss period is a small percentage of the total on time, slower switching is traded for lower conduction loss. In a higher frequency application, just the opposite would be true and the device would be made faster and have greater conduction losses. Notice that the curves in Figure 2 show reductions in both the forward drop (VCE(sat)) and the fall time, tf of newer generation devices. These capabilities make the IGBT the device of choice for applications such as motor drives, power supplies and inverters that require devices rated for 600 to 1200 volts.

IGBT PACKAGE SIZE (TO220) MOSFET PACKAGE SIZE (T0247) 1

1ST GENERATION COMPETITOR 1985 2ND GENERATION COMPETITOR 1989 1ST GENERATION MOTOROLA 1993 3RD GENERATION COMPETITOR 1993 2ND GENERATION MOTOROLA DEMONSTRATED

LOW SATURATION SERIES

0.1

0.2

0.3

0.4

0.5 tf (s)

0.6

0.7

0.8

0.9

1.0

Figure 2. Advanced Features Offered by the Latest Motorola IGBT Technologies for Forward Voltage Drop (VCE(sat)) and Fall Time (tf) 2 MOTOROLA

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CHARACTERISTICS OF IGBTs: DEVICE STRUCTURE
The structure of an IGBT is similar to that of a double diffused (DMOS) power MOSFET. One difference between a MOSFET and an IGBT is the substrate of the starting material. By varying the starting material and altering certain process steps, an IGBT may be produced from a power MOSFET mask; however, at Motorola mask sets are designed specifically for IGBTs. In a MOSFET the substrate is N+ as shown in Figure 3b. The substrate for an IGBT is P+ as shown in Figure 3a. The n epi resistivity determines the breakdown voltage of a MOSFET as mentioned earlier using relationship (1). R DS(on) 2.7 T VDSS (1)

To increase the breakdown voltage of the MOSFET, the n epi region thickness (vertical direction in figure) is increased. As depicted in the classical resistance relationship (2), reducing the RDS(on) of a high voltage device requires greater silicon area A to make up for the increased n epi region. R 1 TA (2)

GATE EMITTER KEY METAL SiO2

POLYSILICON GATE N+ P N+ P+

P+

Rshorting

NPN MOSFET
Rmod

PNP

N EPI N+ BUFFER P+ SUBSTRATE

COLLECTOR

Figure 3a. Cross Section and Equivalent Schematic of an Insulated Gate Bipolar Transistor (IGBT) Cell

GATE SOURCE KEY METAL SiO2

POLYSILICON GATE N+ P

Device designers were challenged to overcome the effects of the high resistive n epi region. The solution to this came in the form of conductivity modulation. The n epi region to this was placed on the P+ substrate forming a pn junction where conductivity modulation takes place. Because of conductivity modulation, the IGBT has a much greater current density than a power MOSFET and the forward voltage drop is reduced. Now the P+ substrate, n epi layer and P+ emitter form a BJT transistor and the n epi acts as a wide base region. The subject of current tailing has been mentioned several times. Thus far, the device structure as shown in Figure 3 provides insight as to what causes the tailing. Minority carriers build up to form the basis for conductivity modulation. When the device turns off, these carriers do not have a current path to exit the device. Recombination is the only way to eliminate the stored charge resulting from the buildup of excess carriers. Additional recombination centers are formed by placing an N+ buffer layer between the n epi and P+ substrate. While the N+ buffer layer may speed up the recombination, it also increases the forward drop of the device. Hence the tradeoff between switching speed and conduction loss becomes a factor in optimizing device performance. Additional benefits of the N+ buffer layer include preventing thermal runaway and punchthrough of the depletion region. This allows a thinner n epi to be used which somewhat decreases forward voltage drop.
COLLECTOR

JFET channel

N+ P+

NPN
P+

GATE
DraintoSource Body Diode (Created when NPN baseemitter is properly shorted by source metal)

N EPI

EMITTER

Figure 4a. IGBT Schematic Symbol

N+ SUBSTRATE

DRAIN

DRAIN

GATE SOURCE

Figure 3b. Cross Section and Equivalent Schematic of an MetalOxideSemiconductor FieldEffect Transistor (MOSFET) Cell

Figure 4b. MOSFET Schematic Symbol

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The IGBT has a four layer (PNPN) structure. This structure resembles that of a thyristor device known as a Silicon Controlled Rectifier (SCR). Unlike the SCR where the device latches and gate control is lost, an IGBT is designed so that it does not latch on. Full control of the device can be maintained through the gate drive. To maximize the performance of the IGBT, process steps are optimized to control the geometry, doping and lifetime. The possibility of latching is also reduced by strategic processing of the device. Geometry and doping levels are optimized to minimize the onvoltage, switching speed and achieve other key parametric variations. Because the IGBT is a fourlayer structure, it does not have the inverse parallel diode inherent to power MOSFETs. This is a disadvantage to motor control designers who use the antiparallel diode to recover energy from the motor. Like a power MOSFET, the gate of the IGBT is electrically isolated from the rest of the chip by a thin layer of silicon dioxide, SiO2. The IGBT has a high input impedance due to the isolated gate and it exhibits the accompanying advantages of modest gate drive requirements and excellent gate drive efficiency. Equivalent Circuit of IGBT Figure 4b shows the terminals of the IGBT as determined by JEDEC. Notice that the IGBT has a gate like a MOSFET yet it has an emitter and a collector like a BJT. The operation of the IGBT is best understood by again referring to the cross section of the device and its equivalent circuit as shown in Figure 3a. Current flowing from collector to emitter must pass through a pn junction formed by the P+ substrate and n epi layer. This drop is similar to that seen in a forward biased pn junction diode and results in an offset voltage in the output characteristic. Current flow contributions are shown in Figure 3a using varying line thickness with the thicker lines indicating a high current path. For a fast device, the N+ buffer layer is highly doped for recombination and speedy turn off. The additional doping keeps the gain of the PNP low and allows twothirds of the current to flow through the base of the PNP (electron current) while onethird passes through the collector (hole current). Rshorting is the parasitic resistance of the P+ emitter region. Current flowing through Rshorting can result in a voltage across the baseemitter junction of the NPN. If the baseemitter voltage is above a certain threshold level, the NPN will begin to conduct causing the NPN and PNP to enhance each others current flow and both devices can become saturated. This results in the device latching in a fashion similar to an SCR. Device processing directs currents within the device and keeps the voltage across Rshorting low to avoid latching. The IGBT can be gated off unlike the SCR which has to wait for the current to cease allowing recombination to take place in order to turn off. IGBTs offer an advantage over the SCR by controlling the current with the device, not the device with the current. The internal MOSFET of the IGBT when gated off will stop current flow and at that point, the stored charges can only be dissipated through recombination. The IGBTs onvoltage is represented by sum of the offset voltage of the collector to base junction of the PNP transistor, the voltage drop across the modulated resistance Rmod and the channel resistance of the internal MOSFET. Unlike the MOSFET where increased temperature results in increased RDS(on) and increased forward voltage drop, the forward drop of an IGBT stays relatively unchanged at increased temperatures. Switching Speed Until recently, the feature that limited the IGBT from serving a wide variety of applications was its relatively slow turnoff speed when compared to a power MOSFET. While turnon is fairly rapid, initial IGBTs had current fall times of around three microseconds. The turnoff time of an IGBT is slow because many minority carriers are stored in the n epi region. When the gate is initially brought below the threshold voltage, the n epi contains a very large concentration of electrons and there will be significant injection into the P+ substrate and a corresponding hole injection into the n epi. As the electron concentration in the nregion decreases, the electron injection decreases, leaving the rest of the electrons to recombine. Therefore, the turnoff of an IGBT has two phases: an injection phase where the collector current falls very quickly, and a recombination phase in which the collector current decrease more slowly. Figure 5 shows the switching waveform and the tail time contributing factors of a fast IGBT designed for PWM motor control service.
TAIL TIME of MOTOROLA GEN. 2 IGBT #2 in 1.0 hp MOTOR DRIVE at 1750 RPM 6 5 I C (AMPS) 4 3 2 1 0 1 0 200 TAIL TIME

400 600

MOSFET TURNOFF PORTION PNP TURNOFF PORTION

800

1000

Figure 5. IGBT Current Turnoff Waveform In power MOSFETs, the switching speed can be greatly affected by the impedance in the gate drive circuit. Efforts to minimize gate drive impedance for IGBTs are also recommended. Also, choose an optimal device based on switching speed or use a slower device with lower forward drop and employ external circuitry to enhance turn off. A turnoff mechanism is suggested in a paper by Baliga et al [2].

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A FINAL COMPARISON OF IGBTs, BJTs AND POWER MOSFETs
The conduction losses of BJTs and IGBTs is related to the forward voltage drop of the device while MOSFETs determine conduction loss based on RDS(on). To get a relative comparison of turnoff time and conduction associated losses, data is presented in Table 1 where the onresistances of a power MOSFET, an IGBT and a BJT at junction temperatures of 25C and 150C are shown. Note that the devices in Table 1 have approximately the same ratings. However, to achieve these ratings the chip size of the devices vary significantly. The bipolar transistor requires 1.2 times more silicon area than the IGBT and the MOSFET requires 2.2 times the area of the IGBT to achieve the same ratings. This differences in die area directly impacts the cost of the product. At higher currents and at elevated temperatures, the IGBT offers low forward drop and a switching time similar to the BJT without the drive difficulties. Table 1 confirms the findings offered earlier in Figure 1a and elaborates further to include a BJT comparison and temperature effects. The reduced power conduction losses offered by the IGBT lower power dissipation and heat sink size. Thermal Resistance An IGBT and power MOSFET produced from the same size die have similar junctiontocase thermal resistance because of their similar structures. The thermal resistance of a power MOSFET can be determined by testing for variations in temperature sensitive parameters (TSPs). These parameters are the sourcetodrain diode onvoltage, the gatetosource threshold voltage, and the draintosource onresistance. All previous measurements of thermal resistance of power MOSFETs at Motorola were performed using the sourcetodrain diode as the TSP. Since an IGBT does not have an inverse parallel diode, another TSP had to be used to determine the thermal resistance. The gatetoemitter threshold voltage was used as the TSP to measure the junction temperature of an IGBT to determine its thermal resistance. However before testing IGBTs, a correlation between the two test methods was established by comparing the test results of MOSFETs using both TSPs. By testing for variations in threshold voltage, it was determined that the thermal resistance of MOSFETs and IGBTs are essentially the same for devices with equivalent die size . Short Circuit Rated Devices Using IGBTs in motor control environments requires the device to withstand short circuit current for a given period. Although this period varies with the application, a typical value of ten microseconds is used for designing these specialized IGBTs. Notice that this is only a typical value and it is suggested that the reader confirm the value given on the data sheet. IGBTs can be made to withstand short circuit conditions by altering the device structure to include an additional resistance (Re, in Figure 6) in the main current path. The benefits associated with the additional series resistance are twofold.
GATE EMITTER KEY METAL SiO2

POLYSILICON GATE N+
Re

N+ P+

R P+ shorting

NPN

MOSFET

Rmod

PNP

N EPI N+ BUFFER P+ SUBSTRATE

COLLECTOR

Figure 6. Cross Section and Equivalent Schematic of a Short Circuit Rated Insulated Gate Bipolar Transistor Cell First, the voltage created across Re, by the large current passing through Re, increases the percentage of the gate voltage across Re, by the classic voltage divider equation. Assuming the drive voltage applied to the gatetoemitter remains the same, the voltage actually applied across the gatetosource portion of the device is now lower, and the device is operating in an area of the transconductance curve that reduces the gain and it will pass less current.

Characteristic TMOS 20 A IGBT 20 A Bipolar 20 A Current Rating Voltage Rating 500 V 0.2 0.6 600 V 500 V* 0.18 R(on) @ TJ = 25C 0.24 0.23 R(on) @ TJ = 150C Fall Time (Typical) 0.24 ** 200 ns 40 ns 200 ns * Indicates VCEO Rating ** BJT TJ = 100C

Table 1. Advantages Offered by the IGBT When Comparing the MOSFET, IGBT and Bipolar Transistor OnResistances (Over Junction Temperature) and Fall Times (Resistance Values at 10 Amps of Current)

MOTOROLA

AN1541
Second, the voltage developed across Re results in a similar division of voltage across Rshorting and VBE of the NPN transistor. The NPN will be less likely to attain a VBE high enough to turn the device on and cause a latchup situation. The two situations described work together to protect the device from catastrophic failure. The protection period is specified with the device ratings, allowing circuit designers the time needed to detect a fault and shut off the device. The introduction of the series resistance Re also results in additional power loss in the device by slightly elevating the forward drop of the device. However, the magnitude of short circuit current is large enough to require a very low Re value. The additional conduction loss of the device due to the presence of Re is not excessive when comparing a short circuit rated IGBT to a nonshort circuit rated device. AntiParallel Diode When using IGBTs for motor control, designers have to place a diode in antiparallel across the device in order to handle the regenerative or inductive currents of the motor. As discussed earlier, due to structural differences the IGBT does not have a parasitic diode like that found in a MOSFET. Designers found that the diode within the MOSFET was, in fact, a parasitic, i.e., not optimized in the design process, and its performance was poor for use as a current recovery device due to slow switching speed. To overcome the lack of performance, an optimized antiparallel diode was used across the MOSFET sourcetodrain. Placing a packaged diode external to the MOSFET itself created performance problems due to the switching delays resulting from the parasitics introduced by the packages. The optimal setup is to have the diode copackaged with the device. A specific line of IGBTs has been created by Motorola to address this issue. These devices work very well in applications where energy is recovered to the source and are favored by motor control designers. Like the switching device itself, the antiparallel diode should exhibit low leakage current, low forward voltage drop and fast switching speed. As shown in Figure 7, the diode forward drop multiplied by the average current it passes is the total conduction loss produced. In addition, large reverse recovery currents can escalate switching losses. A detailed explanation of reverse recovery can be found in the Appendix. A secondary effect caused by large reverse recovery currents is generated EMI at both the switching frequency and the frequency of the resulting ringing waveform. This EMI requires additional filtering to be designed into the circuit. By copackaging parts, the parasitic inductances that contribute to the ringing are greatly reduced. Also, copackaged products can be used in designs to reduce power dissipation and increase design efficiency.
CURRENT IDIODE

IIGBT TIME VOLTAGE IRM(rec)

Vf POWER TIME

TIME

Figure 7. Waveforms Associated with AntiParallel Diode Turnoff

APPLICATION OF IGBTs: PULSE WIDTH MODULATED INDUCTION MOTOR DRIVE APPLICATION

Lineoperated, pulsewidth modulated, variablespeed motor drives are an application well suited for IGBTs. In this application, as shown in Figure 8, IGBTs are used as the power switch to PWM the voltage supplied to a motor to control its speed. Depending on the application, the IGBT may be required to operate from a fullwave rectified line. This can require devices to have six hundred volt ratings for 230 VAC line voltage inputs, and twelve hundred volt ratings for 575 VAC volt line inputs. IGBTs that block high voltage offer fast switching and low conduction losses, and allow for the design of efficient, high frequency drives of this type. Devices used in motor drive applications must be robust and capable of withstanding faults long enough for a protection scheme to be activated. Short circuit rated devices offer safe, reliable motor drive operation.

CONCLUSION
The IGBT is a one of several options for designers to choose from for power control in switching applications. The features of the IGBT such as high voltage capability, low onresistance, ease of drive and relatively fast switching speeds makes it a technology of choice for moderate speed, high voltage applications. New generations of devices will reduce the onresistance, increase speed and include levels of integration that simplify protection schemes and device drive requirements. The reliability and performance advantages of IGBTs are value added traits that offer circuit designers energy efficient options at reduced costs.

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IGBT IGBT 1/2 BRIDGE 1/2 BRIDGE IGBT 1/2 BRIDGE

INDUCTION MOTOR

DIODE BRIDGE FILTER CAPACITOR 230 VAC

TEMPERATURE CONTROL SYSTEM

I/O LON

CONTROL IC MCU OR ASIC

MIXED MODE IC CUSTOM LINEAR OR STANDARD CELL

GATE DRIVE HVIC OR OPTO & LVIC

PHASE CURRENTS AND VOLTAGES

Figure 8. Typical PulseWidth, Modulated, VariableSpeed Induction Motor Drives Are Where IGBTs Offer Performance Advantages

ACKNOWLEDGEMENTS
The writing of this document was assisted by a number of internal device designers. Their assistance was greatly appreciated by the authors. Bill Fragale, Steve Robb and Vasudev Venkatesan provided device operation insight and reference materials. Graphic material was provided by Basam Almesfer and Steve Robb. Finally, C. S. Mitter assisted with editing and accuracy of the material.

REFERENCES
[1] D. Y. Chen, J. Yang, and J. Lee Application of the IGT/COMFET to ZeroCurrent Switching Resonant Converters, PESC, 1987. [2] B. J. Baliga, Analysis of Insulated Gate Transistor Turnoff Characteristics, IEEE Electron Device Lett. EDL6, (1985), pp. 7477 . [3] B. J. Baliga, Switching Speed Enhancement in Insulated Gate Transistors by Electron Irradiation, IEEE Transactions on Electron Devices, ED31, (1984), pp. 17901795.

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APPENDIX

Diode Reverse Recovery Analysis [4]

di/dt IF

IRM(rec)

Qa Qb ta tb trr

A typical reverse recovery waveform is shown in Figure A1. The reverse recovery time trr has been traditionally defined as the time from diode current zerocrossing to where the current returns to within 10% of the peak recovery current IRM(rec). This does not give enough information to fully characterize the waveform shape. A better way to characterize the rectifier reverse recovery is to partition the reverse recovery time into two different regions, ta and tb, as shown in Figure A1. The ta time is a function of the forward current and the applied di/dt. A charge can be assigned to this region denoted Qa, the area under the curve. The tb portion of the reverse recovery current is not very well understood. Measured tb times vary greatly with the switch characteristic, circuit parasitics, load inductance and the applied reverse voltage. A relative softness can be defined as the ratio of tb to ta. General purpose rectifiers are very soft (softness factor of about 1.0), fast recovery diodes are fairly soft (softness factor of about 0.5) and ultrafast rectifiers are very abrupt (softness factor of about 0.2). [4] Source: Motor Controls, TMOS Power MOSFET Transistor Data, Q4/92, DL135, Rev 4, (Phoenix: Motorola, Inc., 1992), pp. 2922 to 2923.

trr = ta = tb = IRM(rec) =

total reverse recovery time fall time due to stored minority charge application and device dependent peak reverse recovery current

Figure A1. Reverse Recovery Waveform

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters can and do vary in different applications. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 18004412447 MFAX: RMFAX0@email.sps.mot.com TOUCHTONE (602) 2446609 INTERNET: http://DesignNET.com

JAPAN: Nippon Motorola Ltd.; TatsumiSPDJLDC, Toshikatsu Otsuki, 6F SeibuButsuryuCenter, 3142 Tatsumi KotoKu, Tokyo 135, Japan. 0335218315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 85226629298

*AN1541/D*

MOTOROLA AN1541/D

AN-983 (v.Int) (HEXFET is a trademark of International Rectifier)

IGBT Characteristics

Topics covered: How the IGBT complements the MOSFET Silicon structure and equivalent circuit Conduction characteristics and switchback Switching characteristics Latching Safe Operating Area Transconductance How to read the data sheet Families of IGBTs

1. HOW THE IGBT COMPLEMENTS THE POWER MOSFET

Switching speed, peak current capability, ease of drive, wide SOA, avalanche and dv/dt capability have made power MOSFETs the logical choice in new power electronic designs. These advantages, a natural consequence of being majority carrier devices, are partly mitigated by their conduction characteristics which are strongly dependent on temperature and voltage rating. Furthermore, as the voltage rating goes up, the inherent reverse diode displays increasing Qrr and Trr which leads to increasing switching losses. IGBTs on the other hand, being minority carrier devices, have superior conduction characteristics, while sharing many of the appealing features of power MOSFETs such as ease of drive, wide SOA, peak current capability and ruggedness. Generally speaking, the switching speed of an IGBT is inferior to that of power MOSFETs. However, as detailed in INT-990 Sec VIII, a new line of IGBTs from International Rectifier has switching characteristics that are very close to those of power MOSFETs, without sacrificing the much superior conduction characteristics. The absence of the integral reverse diode gives the user the flexibility of choosing an external fast recovery diode to match a specific requirement or to purchase a co-pak, i.e. an IGBT and a diode in the same package. The lack of an integral diode can be an advantage or a disadvantage, depending on the frequency of operation, cost of diodes, current requirement, etc.

GATE POLYSILICON

OXIDE

EMITTER N+ PP+ rb N- EPI N+ BUFFER LAYER G P+ SUBSTRATE COLLECTOR (a) DEVICE STRUCTURE E EMITTER rb N+ C COLLECTOR

rb

(b) Device Symbol

(c) EQUIVALENT CIRCUIT

Figure 1. Silicon cross-section of an IGBT with its equivalent circuit and symbol (N-Channel, enhancement mode). The terminal called collector is, actually, the emitter of the PNP. In spite of its similarity to the cross-section of a power MOSFET, operation of the two transistors is fundamentally different, the IGBT being a minority carrier device.

AN-983 (v.Int)

2. SILICON STRUCTURE AND EQUIVALENT CIRCUIT

Except for the P+ substrate, the silicon cross-section of an IGBT (Figure 1) is virtually identical to that of a power MOSFET. Both devices share a similar polysilicon gate structure and P wells with N+ source contacts. In both devices the N- type material under the P wells is sized in thickness and resistivity to sustain the full voltage rating of the device. However, in spite of the many similarities, the physical operation of the IGBT is closer to that of a bipolar transistor than to that of a power MOSFET. This is due to the P+ substrate which is responsible for the minority carrier injection into the N-region and the resulting conductivity modulation. In a power MOSFET, which does not benefit from conductivity modulation, a significant share of the conduction losses occur in the N-region, typically 70% in a 500V device. As shown in the equivalent circuit of Figure 1, the IGBT consists of a PNP driven by an N-Channel MOSFET in a pseudoDarlington configuration. The JFET has been included in the equivalent circuit to represent the contriction in the flow of curr ent between adjacent P-wells. The cell density of the MOSFET structure is higher than that of a high-voltage, comparable technology MOSFET and, consequently, has better Resistance-Area product. The base region of the PNP is not brought out and the emitter-base PN junction, spanning the entire extension of the wafer cannot be terminated nor passivated. This influences the turn-off and reverse blocking behavior of the IGBT, as will be explained later. The breakdown voltage of this junction is about 20V and is shown in the IGBT symbol as an unconnected terminal (Figure 1).

3. CONDUCTION CHARACTERISTICS
As it is apparent from the equivalent circuit, the voltage drop across the IGBT is the sum of two components: a diode drop across the P-N junction and the voltage drop across the driving MOSFET. Thus, unlike the power MOSFET, the on-state voltage drop across an IGBT never goes below a diode threshold. The voltage drop across the driving MOSFET, on the other hand, has one characteristic that is typical of all low voltage MOSFETs: it is sensitive to gate drive voltage. This is apparent from Figures 12 and 13 where, for currents that are close to their rated value, an increase in gate voltage causes a reduction in collector-to-emitter voltage. This is due to the fact that, within its operating range, the gain of the PNP increases with current and an increase in gate voltage causes an increase in channel current, hence a reduction in voltage drop across the PNP. This is quite different from the behavior of a high voltage power MOSFET that is largely insensitive to gate voltage. As the final stage of a pseudo-Darlington, the PNP is never in heavy saturation and its voltage drop is higher than what could be obtained from the same PNP in heavy saturation. It should be noted, however, that the emitter of an IGBT covers the entire area of the die, hence its injection efficiency and conduction drop are much superior to that of a bipolar transistor of the same size. Two options are available to the device designer to decrease the conduction drop: 1. 2. Reduce the on-resistance of the MOSFET. This can be done by increasing the die size and/or the cell density. Increase the gain of the PNP. As explained later, this option is limited by latch-up considerations and voltage withstanding capability.

International Rectifier has been pursuing the optimization of the MOSFET component of the IGBT to the point where its devices can be correctly referred to as a "conductivity modulated MOSFET" with its characteristic features of high speed, low voltage drop and efficient silicon utilization. Other semiconductor companies, on the other hand, have concentrated on the optimization of the bipolar part and the resulting product should be more correctly referred to as a "MOSFET-driven transistor" with a different set of characteristics. The dramatic impact of conductivity modulation on voltage drop can be seen from Figure 2 which compares a HEXFET power MOSFET and an IGBT of the same die size. Temperature dependence, very significant in a power MOSFET, is minimal in an IGBT, just enough to ensure current sharing of paralleled devices at high current levels under steady state conditions, as shown in Figure 14 for the IRGBC20U. This same figure shows that the temperature dependence of the voltage drops is different at different current levels. This is because the diode component of this drop has a temperature coefficient that is initially negative becoming positive at higher current levels. The MOSFET component, on the other hand, is positive. The problem is made more complex by the fact that these two components are weighted differently at different current and temperatures.

AN-983 (v.Int) In addition to reducing the voltage drop and its temperature coefficient, conductivity modulation virtually eliminates its dependence on the voltage rating. This is shown in Table I, where the conduction drops of four IGBTs of different voltage ratings are compared with those of HEXFETs at the same current density. A common misconception is that power MOSFETs exhibit a voltage dependence of the RDS(on) of the following type: R = RO V with = 2.5,

50 40 10A 30
40 IRF8

20 ON-STATE VOLTAGE DROP (VOLTS)

10 7

i.e., the on-resistance increases with the voltage rating at a 5 higher rate than a square law. In reality, assuming that a power law is a true representation of the underlying physical phenomena, the correct value would be 1.6, as can be easily 3 verified from the data sheets of any manufacturer. These data sheets will also contradict the common misconception that IRGBC40U 2 power MOSFETs have better silicon utilization at low voltage. In actual fact they achieve their highest power handling IRGBC40S capability per unit area between 400V and 600V, even if they are unbeatable at low voltages, on account of their resistive 1 20 30 50 70 90 110 130 150 voltage drop. The voltage drop of a conductivity modulated device with minority lifetime killing may exhibit a peculiar JUNCTION TEMPERATURE (0C) behavior frequently referred to as switchback: the voltage Figure 2. On-state voltage drop as temperature of drop at low current and low temperature is higher than two IGBTs of different switching characteristics expected, suddenly dropping to its expected value if current or compared to those of a HEXFET of the same die temperature are increased. The term comes from the fact that, size (IRGBC40S and IRGBC40U vs IRF840). when measuring voltage drop with a curve tracer, the trace Conductivity modulation causes a dramatic suddenly switches to the left of the screen as the current improvement in the on-state voltage drop. To take increases. This behavior is ascribed to lifetime killing which, the avalanche capability of the HEXFET into in so far as it facilitates recombination, delays the onset of account, a 500V device is compared with 600V conductivity modulation. Hence, the voltage drop for current IGBTs. levels below conductivity modulation is higher than for a somewhat higher collector current, after conductivity modulation is established. This phenomenon is one of the causes of the forward recovery of fast (reverse recovery) diodes and of higher values of latching current in minority lifetime killed thyristors. A trace of this phenomenon can be seen in the bump in the VCE(Sat) portion of Figure 12. Notice that the bump disappears in Figure 13 because temperature increases the lifetime of the charges and speeds up the onset of conductivity modulation. Notice, also, that only the Ultrafast IGBTs exhibit this phenomenon, because of higher levels of lifetime killing. Rated Voltage IGBT HEXFET IGBT HEXFET 100 100 1.5 2.0 300 250 2.1 11.2 600 500 2.4 26.7 1200 1000 3.1 100

Typical Voltage Drop 2 @ 1.7A/mm , 1000C Table 1: Dependence of Voltage Drop From Voltage Rating

The voltage rating of the HEXFET power MOSFETs used in this comparison are lower than the IGBTs to take into account their avalanche capability.

4. SWITCHING CHARACTERISTICS
The biggest limitation to the turn-off speed of an IGBT is the lifetime of the minority carriers in the N- epi, i.e., the base of the PNP. Since this base is not accessible, external drive circuitry cannot be used to improve the switching time. It should be remembered, though, that since the PNP is in a pseudo-Darlington connection, it has no storage time and its turn-off time is much faster than the same PNP in heavy saturation. Even so, it may still be inadequate for many high frequency applications.

AN-983 (v.Int) The charges stored in the base cause the characteristic tail in the current waveform of an IGBT at turn-off (Figure 3). As the MOSFET channel stops conducting, electron current ceases and the IGBT current drops rapidly to the level of the hole recombination current at the inception of the tail. This tail increases turn-off losses and requires an increase in the deadtime between the conduction of two devices in a halfbridge. Traditional lifetime killing techniques and/or an N+ buffer layer to collect the minority charges at turn-off are commonly used to speed-up recombination time. Insofar as they reduce the gain of the PNP, these techniques increase the voltage drop. Pushed to the extreme, minority lifetime killing causes a quasi-saturation condition at turn-on, as shown in Figure 4, where the turn-on losses have become larger than the turn-off losses. Thus, the gain of the PNP is constrained by conduction and turn-on losses on one hand, and by latching considerations on the other, as explained in the next section. Like all minority carrier devices, the switching performance of an IGBT degrades with temperature. IGBTs operated in zero current switching may exhibit quasisaturation losses at turn-on that are somewhat higher than in switchmode circuits. The low di/dt that is characteristic of this mode of operation emphasizes the "switchback" phenomenon described in the previous section. Similarly, with zero-voltage turn-off, the IGBT may experience a short burst of current if the complementary device is turned on soon after the current has ceased in the one that was conducting. This is due to the fact that the turn-on of the complementary device causes the supply voltage to appear across the first IGBT, thereby depleting its base region and causing a final sweep-out of the minority carriers that were still left there. There is, however, a component of current that is due to the charging of the device capacitances and is totally unrelated to minority carriers.
IC

VCE

VCE : 100V/div. IC : 5A/div., 0.2 s/div.

Figure 3. Turn-off waveform of a commercial IGBT at 250C, rated current. Notice the clean break at the inception of the "tail". Switching circuit as in Figure 16.

VCE

IC ENERGY VCE : 100V/div. IC: 10A/div. E: 5 mJ/div., 1 s/div.

Figure 4. Switching waveforms of a commercially available IGBT with heavy lifetime killing. It takes approximately 0.5ms for the voltage to drop the last 50V. The energy plot shows that the losses at turn-on are twice as high as those at turn-off. Switching circuit as in Figure 16.

5. LATCHING
As shown in the cross-section of Figure 1, the IGBT is made of four alternate P-N-P-N layers. Given the necessary conditions (NPN + PNP > 1) the IGBT could latch-up like a thyristor. The N+ buffer layer and the wide epi base reduce the gain of the PNP, while the gain of the NPN, which is the parasitic bipolar of the MOSFET, can be reduced with the same techniques [1] that are commonly employed to give HEXFETs their avalanche and dv/dt capability, mainly a drastic reduction of the rb. If this rb is not adequately reduced, "dynamic latching" could occur at turn-off when a high density of hole current flows in r b, taking the gain of the parasitic NPN to much higher values.

6. SAFE OPERATING AREA

The safe operating area (SOA) describes the capability of a transistor to withstand significant levels of voltage and current at the same time. The three main conditions that would subject an IGBT to this combined stress are the following:

AN-983 (v.Int) 1. Operation in short circuit. The current in the IGBT is limited by its gate voltage and transconductance and can reach values well in excess of 10 times its continuous rating. The level of hole current that flows underneath the N+ source contact can cause a drop across rb, large enough to turn on the NPN parasitic bipolar with possible latching. This is normally prevented by a reduction in rb, as mentioned in the previous section or by a reduction of the total device transconductance. Since this second technique increases conduction losses and reduces switching speed, two families of IGBTs have been made available by IR, one optimized for low conduction losses, the other for short circuit operation, as indicated in Section 9. Inductive turn-off, sometimes referred to as "clamped IL." In an inductive turn-off the voltage swings from a few volts to the supply voltage with constant current and with no channel current. These conditions are different from those described in the previous section in so far as the load current is totally made up of holes flowing through rb. For this reason some manufacturers suggest the use of gate drive resistors to slow down the turn-off dv/dt and maintain some level of electron current, thereby avoiding a potential "dynamic latching" condition. IGBTs from International Rectifier can be operated at their maximum switching speed without any problem. Reasons to limit the switching speed should be external to the device (e.g., overshoots due to stray inductance), rather than internal. Operation as a linear amplifier. Linear operation exercises the SOA of the IGBT in a combination of the two modes described above. No detailed characterization of IGBTs as linear amplifiers has been carried out by IR, given the limited use of IGBTs in this type of application.

2.

3.

7. TRANSCONDUCTANCE
The current handling capability of a semiconductor can be limited by thermal constraints or by gain / transconductance constraints. While the "headline current rating" of power semiconductors is based solely on thermal considerations, it is entirely possible, as is frequently the case with bipolar transistors, that the device cannot operate at the current level it is thermally capable of, because its gain has fallen to very low values. As shown in Figure 5, the transconductance of an IGBT tops out at current levels that are well beyond its thermal capability, while the gain of a bipolar of similar die size is on a steep downslope within its current operating range. The flattening out of transconductance occurs when the saturation effects in the MOSFET channel, that reduce the base current of the PNP, combine with the flattening of the gain of the PNP. Since temperature reduces the MOSFET channel current more than it increases the gain of the PNP, the saturation in transconductance occurs at lower current as the temperature increases.
100 70 40 20 gfe hfe 10 7 4 2 1 1A 10A 100A COLLECTOR/DRAIN CURRENT 1000A BUX98
C50U IRGP

1000C

0 45 IRF

Figure 5. Current dependence of the transconductance of an IGBT compared to that of a HEXFET and to the gain of a bipolar of approximately the same die size. The IGBT, like te power MOSFET, is not "gain limited."

Since lifetime killing reduces the gain of the PNP, the transconductance of fast IGBTs peaks at a lower level than those without lifetime killing. This, however, is a second order effect because the gain of the PNP is determined mainly by the N+ buffer layer. The decrease in transconductance at very high current and its additional decrease with temperature helps protect the IGBT under short circuit conditions. With a gate voltage of 15V, the current density of a standard IGBT from International Rectifier reaches values of 10-20A/mm2 in short circuit. This high transconductance is partly responsible for their superior switching and conduction characteristics.

8. HOW TO READ THE DATA SHEET

International Rectifier prides itself on having one of the most comprehensive IGBT data sheets in the industry, with all the information required to operate the IGBT reliably. However, like all technical documents it requires a good understanding by the user of the different terms and conditions. These are briefly explained in the following sections.

AN-983 (v.Int)

IR G P C 4 0 U D2
CO-PAK INTERNATIONAL RECTIFIER
D2 DIODE IS ONE DIE SIZE SMALLER D1 DIODE IS TWO DIE SIZES SMALLER

IGBT

SPEED DESIGNATOR
S STANDARD F FAST M FAST, SHORT CIRCUIT U ULTRAFAST K ULTRAFAST, SHORT CIRCUIT

PACKAGE DESIGNATOR
B P TO-220 TO-247

VOLTAGE DESIGNATOR
C E F G H 600V 800V 900V 1000V 1200V

MODIFIER DIE SIZE

Figure 6. Simplified nomenclature code for commercial IGBTs from International Rectifier

8.1. The Headline Information

In addition to the mechanical layout, the front page gives the voltage drop at the 100C current ratings. The part number itself contains in coded form the key features of the IGBT, as explained in Figure 6.

8.2. The Absolute Maximum Ratings

This table sets up a number of constraints on device operation that apply under any circumstance. Continuous Collector Current @ TC = 25C and 100C (IC). This represents the dc current level that will take the junction to its rated temperature from the stipulated case temperature. It is calculated with the following formula: IC = T j c VCE ( on ) @ I C

where is the temperature rise from the stipulated case temperature to the maximum junction temperature (150C) . Notice that VCE(On) @ IC is not known because IC is not known. 1t can be found with few iterations . It is clear, from this formula, that a current rating has no meaning without a corresponding junction and case temperature. Since in normal applications the case temperature is much higher than 25C, the associated rating is of no practical value and is only reported because transistors have been traditionally rated in this way. Figure 7 shows how this rating changes with case temperature, with a junction temperature of 150C, for a specific device.

Pulsed Collector Current (ICM). Within its thermal limits, the IGBT can be used to a peak current well above the rated continuous DC current. The temperature rise during a high current transient can be calculated as indicated in Section Y. The test circuit is shown in Figure 8. Collector-to-Emitter Voltage (VCE). Voltage across the IGBT should never exceed this rating, to prevent breakdown of the collector-emitter junction. The breakdown itself is guaranteed in the Table of Electrical Characteristics .

AN-983 (v.Int)

MAXIMUM COLLECTOR CURRENT (AMPS DC)

Maximum Gate-to-Emitter Voltage (VGE). The gate voltage is limited by the thickness and characteristics of the gate oxide layer. Though the gate dielectric rupture is typically around 80 volts, the user is limited to 20V to limit current under fault conditions and to ensure long term reliability. Clamped Inductive Load Current (ILM). This rating guarantees that the device is able to repetitively turn off the specified current with a clamped inductive load, as encountered in most applications. In fact, the test circuit (Figure 9) exposes the IGBT to the peak recovery current of the free-wheeling diode, which adds a significant component to the turn-on losses (Figure 10). This rating guarantees a square switching SOA, i.e., that the device can sustain high voltage and high current simultaneously. The ILM rating is specified at 150C, 80% of the rated voltage. This complements the information supplied by the RBSOA. Reverse Avalanche Energy (EARV). This subject is covered in detail in the BVECS section of the electrical characteristics . Maximum Power Dissipation @ 25C and 100C (PD). It is calculated with the following formula:
PD = T jc

15

12

0 25 50 75 100 125 150 Tc, CASE TEMPERATURE (0C)

Figure 7. Maximum Collector Current vs. Case Temperature

The same comments that were made on the Continuous Collector Current apply to Power Dissipation. Junction Temperature (Tj): the device can be operated in the industry standard range of -55C to 150C.

480V

32F 600V

480 RL = 4 X IC @ 250C 480V

10H 32F 600V

40HFL60

10 DUT

10 DUT

Figure 8. Pulsed Collector Current Test Circuit

Figure 9. Clamped Inductive Load Test Circuit

8.3. Thermal Resistance

Rthjc, Rthcs, Rthja are needed for the thermal design, as explained in INT-949

8.4. Electrical Characteristics

The purpose of this section is to provide a detailed characterization of the device so that the designer can predict with accuracy its behavior in a specific application.

Collector-to-Emitter Breakdown Voltage (BVCES). This parameter guarantees the lower limit of the distribution in breakdown voltage. Breakdown is defined in terms of a specific leakage current and has a positive temperature coefficient (listed in the table as BVCES/T) of about 0.63V/C. This implies that a device with 600V breakdown at 25C would have a breakdown voltage of 550V at -55C.

AN-983 (v.Int)

VCE

VCE

IC VCE : 100V/div. IC : 5A./div., 0.1 s/div

IC

VCE : 100V/div. IC : 5A./div., 0.1 s/div

Figure 10a . Turn-on with a clamped inductive load and a fast recovery diode. Test circuit as in Figure 9.

Figure 10b . Turn-on with an ideal diode (zener clamp). Test circuit as in Figure 16.

The reverse recovery is a significant contributor to turn-on losses. To discriminate between the losses that are intrinsic to the IGBT and those due to the diode reverse recovery, the test circuit shown in Figure 16 has been used to generate the data sheet values.

Emitter-to-Collector Breakdown Voltage (BVECS). This rating characterizes the reverse breakdown of the unterminated collector-base junction of the PNP. The relevance of this specification and its associated reverse avalanche energy can be better understood with reference to Figure 11. When an IGBT turns off and current is transferred to the diode across the complementary device, the turn-off di/dt in the stray inductance that is in series with the diode generates a reverse voltage spike across the IGBT (i.e., the collector voltage goes negative with respect to the emitter). This reverse voltage is typically less than 10V, though higher voltages can result from very high di/dt or poor layout. Since this reverse voltage can cause avalanche in the junction, International Rectifier IGBTs have an energy rating, given in the Absolute Maximum Ratings table, that is more useful to the designer than a traditional diode characterization. This rating is typically an order of magnitude more than what would be required by the user. Collector-to-Emitter Saturation Voltage (VCE(on)). Being the key rating to calculate conduction losses, this value is supported by three figures that provide a detailed characterization in temperature, current and gate voltage (Figures 14, 15, and 16 for the IRGBC20U). These replace the older format shown in Figure 12 and 13. Gate Threshold Voltage (VGE(th)). This is the range of voltage on the gate at which collector current starts to flow. The variation in gate threshold with temperature is also specified (VGE(th) / j). Typically the coefficient is -11 mV/C, leading to a reduction of about 1.4V in the threshold voltage at high temperature. Forward Transconductance (gFE). This parameter is measured by superimposing a small variation on a gate bias that takes the IGBT to its 100C rated current in "linear" mode. As mentioned in Section 7, transconductance increases significantly with current so that the "current throughput" of an IGBT is not limited by gain, as a bipolar, but by thermal considerations.

T1

D1

LS

LS

T2 D2

Figure 11. When T2 goes off, load current flows into the diode in parallel with T1. The reverse turnoff di/dt of T2 developes a voltage across the stray inductance in series with D1 which reverse biases T1. IR's IGBTs have a specified reverse blocking capability (BVC E S) and an avalanche rating (ERV)

AN-983 (v.Int)

Zero-Gate-Voltage Collector Current (ICES). This parameter guarantees the upper limit of the leakage distribution at the rated voltage and two temperatures. It complements the BVCES rating seen above.

8.5. Switching Characteristics

GateChargeParameters(Qg, Qge, Qgc). Gate charge values of an IGBT are useful to size the gate drive circuit and estimating gate drive losses. Unfortunately they cannot be used to predict switching times, as for a power MOSFET, because of the minority carrier nature of this device. The test method and the characteristics described in the application note INT-944. Figure 17 gives the typical value of the total gate charge as a function of the voltage applied to the gate. The shape of the curve is explained in detail in INT-944. Switching Times (td, tr, tf). The switching times for a simple IGBT are defined with reference to the Switching Loss Test Circuit of Figure 18. Those for co-paks are defined with reference to the Clamped Inductive Load of Figure 19.
For a simple device, they are defined as follows: Turn-on delay time: 10% of gate voltage to 10% of collector current Rise time: 10 to 90% of collector current Turn-off delay time: 90% of gate voltage to 90% of collector current Fall time: 90 to 10% of collector current.

For a copak, they are defined as follows: Turn-on delay time: 10% of gate voltage to 10% of collector current Rise time: 10 to 90% of collector current Turn-off delay time: 90% of gate voltage to 10% of collector voltage Fall time: 90 to 10% of collector current.

Switching times provide a useful guideline to establish the appropriate deadtime between the turn-off and subsequent turn-on of complementary devices in a half bridge configuration and the minimum and maximum pulse widths. They provide a very unreliable indication of switching losses. Because of the current tail mentioned in Section 8.2, a significant part of the turn-off energy may be dissipated as the current is below 10%. The voltage fall time, on the other hand, is not characterized in any way. Thus, two significant contributors to losses are not properly accounted for by the switching times. Switching losses are fully characterized as such in the data sheet, as explained in the next paragraph.
VGE 50V 15V 10V 7.0V 5.0V
VGE 50V 15V 10V 7.0V BOTTOM 5.0V TOP

Ic, COLLECTOR-TO-EMITTER CURRENT (AMPS)

101

BOTTOM

Ic, COLLECTOR-TO-EMITTER CURRENT (AMPS)

TOP

101

100

5.0V

100

5.0V

10-1

10-2

20s pulse width Tj = 250C

20s PULSE WIDTH Tj = 250C 10-1 0 2 4 6 8 10 Vce, COLLECTOR-TO-EMITTER VOLTAGE (VOLTS)

0 2 4 6 8 10 Vce, COLLECTOR-TO-EMITTER VOLTAGE (VOLTS)

Figure 12. Typical Output Characteristics. Tc = 250C

Figure 13. Typical Output Characteristics, Tc = 1500C

AN-983 (v.Int)

100

100

IC, Collector-to-emitter Current (A)

IC, Gate-to-emitter Current (A)

Tj = 250C

Tj = 1500C 10

Tj = 1500C 10

Tj = 1500C

VGE = 15V 20s PULSE WIDTH 1 VCE, Collector-to-emitter Voltage (V) 10

0.1 5

VCC = 100V 5ms PULSE WIDTH 10 15 VGE, Gate-to-emitter Voltage (V) 20

Figure 14. It should be remembered that IGBTs, like power MOSFETs, do not have a storage time. The turn-off delay is due to the Miller effect, as explained in Section I.A of INT-990.

Figure 15.

4.0 Vce, COLLECTOR-TO-EMITTER VOLTAGE (VOLTS) Ic = 13A Vge = 15V 80ms pulse width

Switching Energy (Eon, Eoff, Ets). IGBTs from International Rectifier have a guaranteed switching energy providing a full characterization in terms of temperature, collector current and gate resistance (Figures 20, 21 and 22 for the IRGBC20U). This allows the designer to calculate the switching losses, without worrying about the actual current and voltage waveshapes, the tail and the quasisaturation.
Any test circuit for measuring switching losses has to satisfy two fundamental requirements: 1. It must simulate the switching conditions as they are encountered in a practical application, i.e., a clamped inductive load with continuous current flow. It must reflect the losses that are attributable to the IGBT, and must be independent from those due to other circuit components, like the reverse recovery of the freewheeling diode.

3.0 Ic = 6.5A

2.0

Ic = 3.3A

1.0 -60 -40 -20

20

40

60

80 100 120 140 160

2.

Tc, CASE TEMPERATURE (0C)

Figure 16. Collector-to-Emitter Saturation Voltage vs. Case Temperature

The test circuit that meets these requirements for a simple IGBT is shown in Figure 18. Its operation is as follows: The driver IGBT builds the test current in the inductor. When it is turned off, current flows in the zener. At this point the switching time and switching energy test begins, by turning on and off the device under test (DUT). The DUT will see the test current that was flowing into the inductor and the voltage across the zener, without any reverse recovery component from a freewheeling diode. This test can exercise the IGBT to its full voltage and current without any spurious effect due to diode reverse recovery. The test method, on the other hand, must account for all losses that occur because of the switching operation, including the quasisaturation at turn-on and the tail at turn-off. To fulfill this requirement, the energy figures reported in the data sheet are defined as follows:

AN-983 (v.Int)

Vge, GATE-TO-EMITTER VOLTAGE (VOLTS)

Eon: From 5% of test current to 5% of test voltage. We feel that 5% is a reasonable compromise between the resolution of the instrumentation and the need to account for the quasi-saturation that could occur in some devices. Eoff: This energy is measured over a period of time that starts with 5% of test voltage and goes on for 5 sec. While the current tail of most IGBTs would be finished well before that time, it was felt that the contribution of the leakage losses to the total energy is minimal. Ets: This is the sum of the turn-on and turn-off losses. As shown in Figure 22, switching energy for International Rectifier IGBTs is closely proportional to current. This is not necessarily true for IGBTs from other manufacturers. The test circuit for a co-pack, on the other hand, should include the losses due to the diode, assuming a clamped inductive load with an identical device in a complementary position (Figure 19). The definitions are as follows: Eon: From 10% of test current to 5% of test voltage. Eoff: This energy is measured over a period of time that starts with 10% of test voltage and goes on for 5 sec. Internal Emitter Inductance (LE) This is the package inductance between the bonding pad on the die and the electrical connection at the lead. This inductance slows down the turn-on of the IGBT by an amount that is proportional to the di/dt of the collector current, just like the Miller effect slows it down by an amount that is proportional to the collector dv/dt. With a di/dt of 1000 A/sec, the voltage developed across this inductance is in excess of 7V. Device Capacitances (Ciee, Coee, Cree). The test circuit and a brief explanation of the test method can be found in Figure 20. The output capacitance has the typical voltage dependence of a P-N junction. The reverse transfer (Miller) capacitance is also strongly dependent on voltage (inversely proportional), but in a more complex way than the output capacitance. The input capacitance, which is the sum of the gate-to-emitter and of the Miller capacitance, shows the same voltage dependence of the Miller capacitance but in a very attenuated form since the gate-toemitter capacitance is much larger and voltage independent.

20 Vce = 480V Ic = 6.5A 16

12

0 0 4 8 12 16 Qg, TOTAL GATE CHARGE (nC) 20

Figure 17. Typical Gate Charge vs. Gate - to Emitter Voltage

LC

DRIVER *

DUT

* DRIVER SAME TYPE AS DUT VC = 80% OF BVCES

Figure 18a

1 2 90% 3 VC 90% 5% 10% tr Eon Ets = (Eon + Eoff) tf Eoff t = 5 s 10%

td(off)

IC

Figure 18b. Figure 18. Switching Loss Test Circuit and Waveforms

AN-983 (v.Int)

+ Vge

90% Vge

Same type device as D.U.T.

Vce 10% Vce Ic tf 90% Ic 5% Ic t1+5s Eoff = Vce Ic dt t1

Ic

80% of Vce

430F D.U.T.

td (off)

t1

t2

Figure 19a.
GATE VOLTAGE DUT 10% +Vg +Vg tx 10% Vcc Vpk Ic

Figure 19b.
trr Qrr=

trr Id dt tx

10% Irr Vcc

Vce 10% Ic 90% Ic 5% Vce

DUT VOLTAGE AND CURRENT

Vcc

Ipk

Ic

td (on)

tr

t2 Eon = Vce Ic dt t1 t2

DIODE REVERSE WAVEFORMS t4 Erec= Vd Id dt t3 t4

t1

DIODE REVERSE RECOVERY ENERGY t3

Figure 19c.

Figure 19d.
Vg GATE SIGNAL DEVICE UNDER TEST

CURRENT D.U.T.

VOLTAGE IN D.U.T.

CURRENT IN D1

Figure 19e.

AN-983 (v.Int)

0.350 TOTAL SWITCHING ENERGY LOSSES (mJ)

Vce = 480V Vge = 15V Tc = 250C Ic = 6.5A

0.345

TOTAL SWITCHING ENERGY LOSSES (mJ)

Vge = 15V Vcc = 480V Rg = 50

Ic = 13A 100 Ic = 6.5A

0.340

0.335 0.330

Ic = 3.3A

0.325

0.320 20

25

30 35 40 45 50 Rg, GATE RESISTANCE (OHMS)

55

10-1 -60 -40 -20

0 20 40 60 80 100 120 140 160 Tc, CASE TEMPERATURE (0C)

Figure 20. Typical Switching Losses vs. Gate Resistance

Figure 21. Typical Switching Losses vs. Case Temperature

The Transfer Characteristic (Figure 15 for the IRGBC20U). This curve deviates from the traditional definition of transfer characteristic in one detail: the drain is not connected to the gate but to a fixed (100V) supply. When gate and drain are tied together, the curve is the boundary separating operation in full enhancement from operation in linear mode (sometimes referred to as "sat mode"). Figure 15 provides an indication of current when operated in short circuit. In the normal range of operation this curve shows a slight negative dependence on temperature and is largely independent from applied voltage. The Short-Circuit Withstand Time (for short-circuit rated IGBTs) defines the guaranteed minimum time the IGBT can be in short circuit in the specified conditions. Notice that the gate resistor cannot be any lower than specified and the overvoltage at turn-off has to be maintained to the indicated value by an appropriate clamp.
If a diode is copackaged with the IGBT, its characteristics are included in this table, together with their associated graphs. The parameters included in the table are defined in application note AN-989.
1.00 TOTAL SWITCHING ENERGY LOSSES (mJ) Tc = 1500C Rg = 250 Vcc = 480V Vge = 15V

9: The IGBT Families from IR

Table II may be useful in placing different power transistors in the proper perspective. In general, the IGBT offers clear advantages in high voltage (>300V), high current (1-3 A/mm2 of active area), and medium speed (to 5-50 kHz). International Rectifiers technology is characterized by very low voltage drop per unit of current density. This allows higher levels of minority lifetime killing and, consequently, much lower switching losses. To maximize the value to the user of its technological breakthrough, International Rectifier has introduced three different families of devices with different crossover frequency: Standard, Fast and UltraFast. IR's Standard IGBTs have been optimized for voltage drop and conduction losses and have the lowest voltage drop per unit of current density that is presently available in the market.

0.90 0.80 0.70

0.60 0.50

0.40

0.30 3

6 9 12 15 Ic, COLLECTOR-TO-EMITTER CURRENT (AMPS)

Figure 22. Typical Switching Losses vs. Collector Current

AN-983 (v.Int) IR's UltraFast IGBTs have been optimized for switching losses and have the lowest switching losses per unit of current density presently available in the market. As it is apparent from Figure 24, these devices have switching speeds that are comparable to those of power MOSFETs in practical applications. They can operate comfortably at 50 kHz in PWM and well over 100 kHz in resonant or ZVS/ZCS circuits.

620K DUT Ciee = Ccg + Cge =

HIGH CAPACITANCE METER

1F

BIAS VOLTAGE

1 1 Cmeasured 1 C2

10M 620K

LOW

C2

Figure 23a.
HIGH C2 620K Coee = Ccg + Cce = CAPACITANCE METER DUT BIAS VOLTAGE LOW 620K = 1 1 Cmeasured 1 C2

Figure 23b.
LOW 10:1 1f 620K Cree = Ccg DUT CAPACITANCE METER HIGH 10M 620K BIAS VOLTAGE =

Figure 23c. Figure 23. Capacitance test circuits

The IGBT is biased with 25V between collector and emitter. Two of its terminals are ac shorted with a large value capacitor. Capacitance is measured between these two terminals and the third.
IR's Fast devices offer a combination of low switching and low conduction losses that closely matches the switching characteristics of many popular bipolar transistors. Table III shows the key features of the three families. The Fast and Ultrafast IGBTs are also available in short-circuit rated versions for those applications, like motor drives, that require it. The short circuit capability comes at the expenses of a slight increase in conduction losses.

AN-983 (v.Int)

VCE

VCE

IC ENERGY VCE : 100V/div. IC : 10a/div. E : 0.5J/div., 0.1ms/div.

IC ENERGY VCE : 100V/div. IC : 10A/div. E : 0.5 mJ/div., 0.1 s/div

Figure 24a.

Figure 24b.

Figure 24. IRGPC50U switching 50A at 480V, 1250C. Test circuit is as shown in Figure 16.

Type of Drive Drive Power Drive Complexity

POWER MOSFETs Voltage Minimal Simple

IGBTs Voltage Minimal Simple

Current Density For Give Voltage Drop Switching Losses

High at low voltages Low at high voltages Very Low

Very High Small trade-off with switching speed Low to Medium depending on trade-off with conduction losses

Bipolars Current Large High Large positive and negative currents are required Medium Severe trade-off with switching speed Medium to High depending on trade-off with conduction losses

Darlingtons Current Medium Medium

Low

High

Table II: Comparative Table of Power Transistor Characteristics

References: 1. U.S. Patents No. 4,376,286 and 4,642,666

Characteristic VCE Switching Energy Conduction Losses (50% dc)

Standard 1.3V 0.54 mJ/A mm

2

Fast 1.5V 0.16 mJ/A mm

2

Ultrafast 1.9V 0.055mJ/A mm

2

0.625W
2

0.75W

0.95W

Table III. International Rectifier IGBT Families

1A/mm , 1000C, Typical Values

PD 91453B

IRG4BC30UD
INSULATED GATE BIPOLAR TRANSISTOR WITH ULTRAFAST SOFT RECOVERY DIODE
Features
UltraFast: Optimized for high operating frequencies 8-40 kHz in hard switching, >200 kHz in resonant mode Generation 4 IGBT design provides tighter parameter distribution and higher efficiency than Generation 3 IGBT co-packaged with HEXFREDTM ultrafast, ultra-soft-recovery anti-parallel diodes for use in bridge configurations Industry standard TO-220AB package
C

UltraFast CoPack IGBT

VCES = 600V
G E

VCE(on) typ. = 1.95V

@VGE = 15V, IC = 12A

n-cha nn el

Benefits
Generation -4 IGBT's offer highest efficiencies available IGBTs optimized for specific application conditions HEXFRED diodes optimized for performance with IGBTs . Minimized recovery characteristics require less/no snubbing Designed to be a "drop-in" replacement for equivalent industry-standard Generation 3 IR IGBTs

TO-220AB

Absolute Maximum Ratings

Parameter
VCES IC @ TC = 25C IC @ TC = 100C ICM ILM IF @ TC = 100C IFM VGE PD @ TC = 25C PD @ TC = 100C TJ TSTG Collector-to-Emitter Voltage Continuous Collector Current Continuous Collector Current Pulsed Collector Current Q Clamped Inductive Load Current R Diode Continuous Forward Current Diode Maximum Forward Current Gate-to-Emitter Voltage Maximum Power Dissipation Maximum Power Dissipation Operating Junction and Storage Temperature Range Soldering Temperature, for 10 sec. Mounting Torque, 6-32 or M3 Screw.

Max.
600 23 12 92 92 12 92 20 100 42 -55 to +150 300 (0.063 in. (1.6mm) from case) 10 lbfin (1.1 Nm)

Units
V

V W

Thermal Resistance
Parameter
RJC RJC RCS RJA Wt Junction-to-Case - IGBT Junction-to-Case - Diode Case-to-Sink, flat, greased surface Junction-to-Ambient, typical socket mount Weight

Min.
-------------------------

Typ.
----------0.50 ----2 (0.07)

Max.
1.2 2.5 -----80 ------

Units
C/W

g (oz)

www.irf.com

1
4/17/00

IRG4BC30UD
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
Parameter Min. Collector-to-Emitter Breakdown VoltageS 600 V(BR)CES/ TJ Temperature Coeff. of Breakdown Voltage ---VCE(on) Collector-to-Emitter Saturation Voltage ---------VGE(th) Gate Threshold Voltage 3.0 VGE(th)/TJ Temperature Coeff. of Threshold Voltage ---gfe Forward Transconductance T 3.1 ICES Zero Gate Voltage Collector Current ------V FM Diode Forward Voltage Drop ------IGES Gate-to-Emitter Leakage Current ---V(BR)CES Typ. Max. Units ------V 0.63 ---- V/C 1.95 2.1 2.52 ---V 2.09 ------- 6.0 -11 ---- mV/C 8.6 ---S ---- 250 A ---- 2500 1.4 1.7 V 1.3 1.6 ---- 100 nA Conditions VGE = 0V, IC = 250A VGE = 0V, IC = 1.0mA IC = 12A VGE = 15V IC = 23A See Fig. 2, 5 IC = 12A, TJ = 150C VCE = VGE, IC = 250A VCE = VGE, IC = 250A VCE = 100V, IC = 12A VGE = 0V, VCE = 600V VGE = 0V, VCE = 600V, TJ = 150C IC = 12A See Fig. 13 IC = 12A, TJ = 150C VGE = 20V

Switching Characteristics @ TJ = 25C (unless otherwise specified)

Qg Qge Qgc td(on) tr td(off) tf Eon Eoff Ets td(on) tr td(off) tf Ets LE Cies Coes Cres t rr Irr Qrr di (rec)M/dt Parameter Total Gate Charge (turn-on) Gate - Emitter Charge (turn-on) Gate - Collector Charge (turn-on) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Switching Loss Turn-Off Switching Loss Total Switching Loss Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Switching Loss Internal Emitter Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Diode Reverse Recovery Time Diode Peak Reverse Recovery Current Diode Reverse Recovery Charge Diode Peak Rate of Fall of Recovery During tb Min. ---------------------------------------------------------------------------------Typ. 50 8.1 18 40 21 91 80 0.38 0.16 0.54 40 22 120 180 0.89 7.5 1100 73 14 42 80 3.5 5.6 80 220 180 120 Max. Units Conditions 75 IC = 12A 12 nC VCC = 400V See Fig. 8 27 VGE = 15V ---TJ = 25C ---ns IC = 12A, VCC = 480V 140 VGE = 15V, RG = 23 130 Energy losses include "tail" and ---diode reverse recovery. ---mJ See Fig. 9, 10, 11, 18 0.9 ---TJ = 150C, See Fig. 9, 10, 11, 18 ---ns IC = 12A, VCC = 480V ---VGE = 15V, RG = 23 ---Energy losses include "tail" and ---mJ diode reverse recovery. ---nH Measured 5mm from package ---VGE = 0V ---pF VCC = 30V See Fig. 7 --- = 1.0MHz 60 ns TJ = 25C See Fig. 120 TJ = 125C 14 IF = 12A 6.0 A TJ = 25C See Fig. 10 TJ = 125C 15 VR = 200V 180 nC TJ = 25C See Fig. 600 TJ = 125C 16 di/dt 200A/s ---- A/s TJ = 25C See Fig. ---TJ = 125C 17

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IRG4BC30UD
16

12

Load Current ( A )

D uty c yc le : 5 0% T J = 12 5 C T s in k = 90 C G a te d rive a s s pe c ified T urn -o n losse s in clud e effects of re verse re co very

Pow e r D is sipatio n = 21 W 6 0 % o f ra te d vo l ta g e

0 0.1 1 10

A
100

f, Frequency (kHz)

Fig. 1 - Typical Load Current vs. Frequency

(Load Current = IRMS of fundamental)

100

100

I C , C olle cto r-to -E m itte r C u rre n t (A )

TJ = 2 5 C TJ = 1 5 0 C
10

I C , C o lle cto r-to -E m itte r C u rre n t (A )

TJ = 1 5 0 C
10

TJ = 2 5 C

0.1 0.1 1

VG E = 1 5 V 2 0 s P U L S E W ID T H A
10

0.1 5 6 7 8

V CC = 10V 5 s P U L S E W ID T H
9 10 11

A
12

V C E , C o lle cto r-to -E m itte r V o lta g e (V )

VG E , G a te -to -E m itte r V o lta g e (V )

Fig. 2 - Typical Output Characteristics

Fig. 3 - Typical Transfer Characteristics

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IRG4BC30UD
M a xim u m D C C o lle c to r C u rre n t (A
25

V C E , C ollector-to-Em itter Volta ge (V)

V GE = 15V

3.0

VGE = 15V 8 0 s P U L S E W ID T H

IC = 2 4 A

20

2.5

15

IC = 1 2 A
2.0

10

I C = 6 .0 A
A
-60 -40 -20 0 20 40 60 80 100 120 140 160

0 25 50 75 100 125

A
150

1.5

TC , C a s e Te m p e ra tu re ( C )

T J , Ju n c tio n T e m p e ra tu re ( C )

Fig. 4 - Maximum Collector Current vs. Case Temperature

Fig. 5 - Typical Collector-to-Emitter Voltage vs. Junction Temperature

10

Therm al Response (Z thJ C )

1
D = 0.5 0

0.20 0.10
PD M

0 .1

0 .05 0 .0 2 0 .0 1 S IN G L E PU LS E (T H E R M AL RE S PO N SE )

1
t2

N o te s : 1 . D u ty f ac t or D = t

/ t

0 .0 1 0 .0 0 0 0 1

2 . P e a k TJ = P D M x Z th J C + T C

0 .0 0 0 1

0 .0 0 1

0 .0 1

0 .1

10

t 1 , R ectangular Pulse Duration (sec)

Fig. 6 - Maximum IGBT Effective Transient Thermal Impedance, Junction-to-Case

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IRG4BC30UD
2000

V G E , G a te -to -E m itte r V o lta g e (V )

A

C, C apa cita nc e (pF )

1600

V GE = C ie s = C re s = C oes =

0V , f = 1MHz C g e + C g c , C ce S H O R TE D C gc C ce + C g c

20

VCE = 400V IC = 12A

16

C ie s
1200

12

800

C oes

400

C re s

0 1 10

0 0 10 20 30 40

A
50

100

V C E , C o lle c to r-to -E m itte r V o lta g e (V )

Q g , T o ta l G a te C h a rg e (n C )

Fig. 7 - Typical Capacitance vs. Collector-to-Emitter Voltage

Fig. 8 - Typical Gate Charge vs. Gate-to-Emitter Voltage

0.60

10

Total Switchig Losses (mJ)

0.58

Total Switchig Losses (mJ)

V C C = 480V V G E = 15V T J = 25 C I C = 12A

R G = 23 V G E = 15V V C C = 480V

I C = 24A

0.56

I C = 12A

0.54

I C = 6.0A

0.52

0.50 0 10 20 30 40 50

A
60

0.1 -60 -40 -20 0 20 40 60 80 100 120 140

A 160

R G , Gate Resistance ( )

TJ , Junction Temperature ( C)

Fig. 9 - Typical Switching Losses vs. Gate Resistance

Fig. 10 - Typical Switching Losses vs. Junction Temperature

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IRG4BC30UD
2.0

Total Switchig Losses (mJ)

1.6

I C , C ollector-to-E m itter C urrent (A )

RG TJ V CC V GE

= 23 = 150 C = 480V = 15V

1000

VG = 2 0V EE G T J = 12 5 C

100

1.2

S A FE O P E R A TIN G A R E A
10

0.8

0.4

0.0 0 10 20 30

0 .1 1 10 100 1000

I C , Collector-to-Emitter Current (A )

V C E , Collecto r-to-E m itter V oltage (V )

Fig. 11 - Typical Switching Losses vs. Collector-to-Emitter Current

100

Fig. 12 - Turn-Off SOA

Instan tan eou s Fo rwa rd C urre nt - I F (A )

TJ = 15 0 C
10

TJ = 12 5 C TJ = 2 5 C

1 0.4 0.8 1.2 1.6 2.0 2.4

Fo rwa rd V oltage D rop - V FM (V )

Fig. 13 - Maximum Forward Voltage Drop vs. Instantaneous Forward Current

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IRG4BC30UD
160 100

VR = 2 0 0 V TJ = 1 2 5 C TJ = 2 5 C
120

VR = 2 0 0 V TJ = 1 2 5 C TJ = 2 5 C

I F = 24 A I F = 1 2A
80

I IR R M - (A )

I F = 2 4A
10

t rr - (ns)

I F = 1 2A I F = 6 .0A

I F = 6 .0 A

40

0 100

d i f /d t - (A / s)

1000

1 100

1000

di f /dt - (A /s)

Fig. 14 - Typical Reverse Recovery vs. dif/dt

600

Fig. 15 - Typical Recovery Current vs. dif/dt

10000

VR = 2 0 0 V TJ = 1 2 5 C TJ = 2 5 C

VR = 2 0 0 V TJ = 1 2 5 C TJ = 2 5 C

400

d i(re c )M /d t - (A / s)

1000

Q R R - (n C )

IF = 6.0 A

I F = 2 4A I F = 1 2A

I F = 12 A
100

200

I F = 6.0 A

I F = 2 4A

0 100

d i f /d t - (A / s)

1000

10 100

1000

d i f /d t - (A / s)

Fig. 16 - Typical Stored Charge vs. dif/dt

Fig. 17 - Typical di(rec)M/dt vs. dif/dt

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IRG4BC30UD
90% Vge +Vge

Same ty pe device as D .U.T.

Vce

Ic 80% of Vce 430F D .U .T.

10% Vce Ic

9 0 % Ic 5 % Ic

td (o ff)

tf

Eoff =

t1 + 5 S V c e ic d t t1

Fig. 18a - Test Circuit for Measurement of ILM, Eon, Eoff(diode), trr, Qrr, Irr, td(on), tr, td(off), tf
t1 t2

Fig. 18b - Test Waveforms for Circuit of Fig. 18a, Defining

Eoff, td(off), tf

G A T E V O L T A G E D .U .T . 1 0 % +V g +Vg

trr Ic

Q rr =

trr id d t tx

tx 10% Vcc Vce Vcc 1 0 % Ic 9 0 % Ic D UT VO LTAG E AN D CU RRE NT Ip k Ic

1 0 % Irr V cc

V pk Irr

D IO D E R E C O V E R Y W A V E FO R M S td (o n ) tr 5% Vce t2 E o n = V ce ie d t t1 t2 D IO D E R E V E R S E REC OVERY ENER GY t3 t4

E re c =

t1

t4 V d id d t t3

Fig. 18c - Test Waveforms for Circuit of Fig. 18a,

Defining Eon, td(on), tr

Fig. 18d - Test Waveforms for Circuit of Fig. 18a,

Defining Erec, trr, Qrr, Irr

www.irf.com

IRG4BC30UD

V g G A T E S IG N A L D E V IC E U N D E R T E S T C U R R E N T D .U .T .

V O L T A G E IN D .U .T .

C U R R E N T IN D 1

t0

t1

t2

Figure 18e. Macro Waveforms for Figure 18a's Test Circuit

L 1000V 50V 6000 F 100 V Vc*

D.U.T.

RL= 0 - 480V

480V 4 X IC @25C

Figure 19. Clamped Inductive Load Test Circuit

Figure 20. Pulsed Collector Current Test Circuit

www.irf.com

INSTITUTO DE ELETRNICA DE POTNCIA

DEPARTAMENTO DE ENGENHARIA ELTRICA CENTRO TECNOLGICO UNIVERSIDADE FEDERAL DE SANTA CATARINA

MCT
A G

Acadmico Cssio Guimares Lopes Prof. Arnaldo Jos Perin

Florianpolis, maro de 1996

MCT - MOS CONTROLLED THYRISTOR

NDICE

Assunto Introduo Princpio de Funcionamento Caractersticas Parmetros Operao Forma de Onda da Tenso de Gatilho Amplitude Negativa Transio Negativa Amplitude Positiva Transio Positiva rea de Operao Segura de Bloqueio Circuitos de Comando Coeficiente de Temperatura da Tenso Comparao: IGBT versus MCT Queda de Tenso em Conduo Comutao Tenso de Operao Segura de Bloqueio Onde Usar o MCT? Referncias Bibliogrficas

Pgina 3 4 5 6 8 8 9 9 9 9 10 10 12 13 13 13 14 14 15

INEP - INSTITUTO DE ELETRNICA DE POTNCIA

MCT - MOS CONTROLLED THYRISTOR

INTRODUO

A eletrnica de potncia invariavelmente soluciona problemas relacionados utilizao de energia eltrica. Progressos nesta rea traduzem-se, freqentemente, na dependncia do aperfeioamento ou do desenvolvimento de novos interruptores base de dispositivos semicondutores. Um novo dispositivo semicondutor de potncia, o MOS Controlled Thyristor, ou simplesmente MCT - j disponvel comercialmente - emerge como uma alternativa mpar para a implementao e projeto das estruturas envolvidas em eletrnica de potncia. Possui seu prprio conjunto de caractersticas, embora carregue consigo semelhanas com interruptores mais antigos, como SCRs ou GTOs. Objetivando a familiarizao com o componente, descreve-se de maneira genrica, porm concisa, o seu funcionamento e suas principais caractersticas, no havendo compromisso com o aprofundamento do assunto, o que torna-se possvel consultando as referncias bibliogrficas apresentadas.

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MCT - MOS CONTROLLED THYRISTOR

PRINCPIO DE FUNCIONAMENTO
A figura 1 mostra o circuito equivalente do MCT tipo P, o P-MCT, baseado no modelo de tiristor a dois transistores. Nota-se tambm a presena de dois FETs, responsveis pelo disparo e bloqueio via gatilho - o arranjo permite o comando do MCT atravs da tenso gate-anodo, VGA . No P-MCT, o mosfet canal P realiza o disparo. Aplicando-se tenso VGA negativa, o PFET acionado, polarizando a base do transistor inferior (NPN), o que coloca o MCT em conduo.

ANODO

PFET-DISPARO

GATILHO

NFET-BLOQUEIO

CATODO

Fig. 1 - Circuito Equivalente O bloqueio proporcionado, via gatilho, pela aplicao de tenso VGA positiva. O mosfet canal N entra em conduo, desviando a corrente de emissor do transistor PNP bloqueando-o. Isto provoca o corte da corrente de polarizao da base do transistor NPN,

INEP - INSTITUTO DE ELETRNICA DE POTNCIA

MCT - MOS CONTROLLED THYRISTOR

interrompendo a corrente de catodo do MCT e efetuando o seu bloqueio. O MCT tambm bloqueado por corrente reversa, como ocorre com tiristores comuns.

CARACTERSTICAS
Pela sua constituio, o MCT combina a capacidade de corrente dos tiristores com a alta impedncia de entrada das portas MOS, permitindo o controle de disparo/bloqueio por tenso. A figura 2 apresenta sua simbologia.

A ANODO RETORNO GATILHO GATILHO G

CATODO K

Fig. 2 - Simbologia A primeira gerao de P-MCT, 600 V, constituda de cerca de 11.000 grupos de clulas em paralelo. Cada grupo constitue-se de 9 clulas de 0.4 cm2 , uma das quais destina-se ao disparo, sendo rodeada pelas 8 restantes responsveis pelo bloqueio. O MCT apresenta diversas vantagens quando comparado com os interruptores tradicionais utilizados em eletrnica de potncia: A alta impedncia do gatilho MOS exige uma quantidade mnima de energia para a comutao, simplificando os circuitos de comando; Possui baixa queda de tenso em conduo;

INEP - INSTITUTO DE ELETRNICA DE POTNCIA

MCT - MOS CONTROLLED THYRISTOR

Grande capacidade de di/dt e dv/dt; Baixa capacitncia de entrada, tipicamente 10 nF, no apresentando corrente Miller na comutao; Excelente capacidade de corrente: para quedas de tenso similares, pode apresentar densidades de corrente centenas de vezes maior que seu contemporneo IGBT (figura 3); Tiristores, GTOs e MCTs podem apresentar queda de tenso em conduo reduzida, porm este ltimo possuir dimenses menores (economia de silcio); Para uma mesma quantidade de silcio, o MCT apresenta queda de tenso bem inferior quando comparado a outros interruptores como GTOs ou tiristores comuns; So fabricados sobre uma ampla faixa de valores, de 100V a 8KV, podendo alcanar os 10KV. O bloqueio pode ser simtrico ou assimtrico (suporta apenas tenses positivas ou tambm negativas).

PARMETROS
O MCT assemelha-se em certos aspectos aos tiristores. Muitos parmetros encontrados em seus manuais so idnticos aos presentes nos manuais dos FETs de potncia. Entretanto, alguns parmetros so diferentes dos convencionais: Tenso de Bloqueio de Pico (MCT Bloqueado), VDRM - mxima tenso permissvel entre catodo e anodo; Tenso de Pico Reversa, VRRM - o MCT no projetado como um componente de bloqueio de tenso reversa mas, como o IGBT, possui capacidade de bloqueio suficiente para permitir o uso de um diodo em antiparalelo; Corrente de Catodo de Pico No Repetitiva, ITSM - a mxima corrente permissvel atravs do componente sob o formato de um pulso. A temperatura da juno limita sua amplitude e largura;
INEP - INSTITUTO DE ELETRNICA DE POTNCIA

MCT - MOS CONTROLLED THYRISTOR

Corrente Controlvel de Pico, ITC - representa o mximo valor de corrente de catodo bloquevel atravs do sinal de gatilho. Bloquear correntes que ultrapassem este valor pode significar a destruio do componente;

DENSIDADE DE CORRENTE (A/cm2)

1 10 4

N-MCT P-MCT
1000

N-IGBT
100

DARLINGTON
10

N-MOSFET TEMPERATURA:
1 0 0.5 1.0 1.5 2

o 25

C
2.5

QUEDA

DE

TENSO (VOLTS)

Fig. 3 - Comparao entre alguns Interruptores de Potncia Tenso Gate-Anodo (pico), VGA - o componente permite sobretenses (overshoot) durante as transies de bloqueio e disparo; Mxima Potncia Dissipada, PT - funo da mxima resistncia trmica junoencapsulamento (0,6oC/W) e da mxima diferena de temperatura juno-encapsulamento (+125oC).

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MCT - MOS CONTROLLED THYRISTOR

OPERAO
Certos cuidados devem ser tomados para a operao com sucesso. Segundo testes realizados pelo fabricante (HARRIS) , o MCT operou bloqueando 80A a 300oC, suportando dV/dts de 10KV/s a 250oC. Com a juno a uma temperatura de 235oC, ele suportou cerca de 100 horas ao teste de vida de bloqueio. Recomenda-se para tanto, manter-se continuamente a polarizao do gatilho. Forma de Onda da Tenso de Gatilho O desempenho do MCT est ligado diretamente forma de onda da tenso de gatilho. O seu funcionamento mapeado na figura 4, que serve como base para a definio de valores de tenso para o circuito de comando.
VGA POSITIVA (VOLTS) (BLOQUEIO) 25 20 15 10 5 0 -5 -10 -15 -20 -25 TEMPO EM us
REGIO SEGURA MCT EM CONDUO REGIO SEGURA MCT EM CONDUO REGIO SEGURA MCT BLOQUEADO TRANSIO NEGATIVA (DISPARO) TRANSIO

1
(BLOQUEIO)

1
(DISPARO)

Fig. 4 - Limites da Forma de Onda da Tenso de Gatilho Durante a ocorrncia dos pulsos de comando (amplitude constante) deve-se caracterizar a forma de onda pelas regies seguras. Nos perodos de transio, o sinal de gatilho deve enquadrar-se nas reas sombreadas.

INEP - INSTITUTO DE ELETRNICA DE POTNCIA

MCT - MOS CONTROLLED THYRISTOR

Amplitude Negativa A tenso limite de -7V na regio segura (figura 4) coloca o componente em conduo com certo atraso. A tenso de -20V, ainda na regio segura, limita o funcionamento normal do MCT sem danific-lo por tenso excessiva. Transio Negativa Distintamente no MCT, o gatilho (valor de tenso) no pode ser usado no controle do tempo de disparo, o que pode ser conseguido variando-se a inclinao da transio negativa da tenso. Quando o perodo da transio reduzido, a corrente de deslocamento provocar o disparo com a tenso de gatilho ainda positiva. Amplitude Positiva Com a aplicao de tenso gate-anodo positiva, o MCT bloqueado e assim permanece. O bloqueio da corrente conseguido com uma tenso da ordem de 18V com uma durao mnima de 1,5 s. Limita-se em 20V a tenso na regio segura a fim de se evitar a destruio por excesso da mesma. Permite-se que a tenso alcance os 25V nas transies. Transio Positiva Para maximizar a capacidade de bloqueio, deve-se acionar o gatilho rapidamente. Caso o crescimento da tenso ocorra de maneira lenta, a corrente ser redistribuida nas clulas internas alcanando valores que impossibilitaro o bloqueio. Isto estabelece 200 ns como limite de tempo para a transio positiva.

INEP - INSTITUTO DE ELETRNICA DE POTNCIA

MCT - MOS CONTROLLED THYRISTOR

rea de Operao Segura de Bloqueio Similarmente a outros interruptores a semicondutor tipo P, o P-MCT apresenta limitaes na rea de operao segura de bloqueio (SOA). Basicamente trs fatores so incisivos na capacidade de comutao: Tempo de subida da Tenso de Gatilho: para valores superiores ao recomendado anteriormente, a rea de operao segura ser delimitada abaixo da curva mostrada na figura 5. Tenso de Gatilho durante o Bloqueio: a tenso de gatilho deve alcanar e manter os valores anteriormente indicados sob pena da reduo da regio superior plana da curva. Tenso VKA de Pico: na regio de alta tenso da curva a capacidade de comutao influenciada por este valor. Aconselha-se a aplicao de sobretenso (25 V) durante a comutao para o auxlio do bloqueio. Circuitos de Comando Os circuitos de comando destinados ao MCT devem apresentar as seguintes caractersticas: Tenso de Comando de Gatilho: superior a 20V; Tempo de Subida/Descida: < 200ns; Corrente de pico: superior a 2A; Interface de sinal: isolao tica ou magntica;

Isolao de Potncia: o circuito de comando deve ser fisicamente conectado ao anodo do MCT. Requer-se isolamento da tenso de barramento e capacidade de suportar dv/dt resultante das comutaes.

INEP - INSTITUTO DE ELETRNICA DE POTNCIA

10

MCT - MOS CONTROLLED THYRISTOR

o Ik (A) Tj=+150 C, Vg=18V,L=200u 170 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 0 -50 -150 -250 -350 -450 -550 VKA (V Fig. 5 - Curva de Capacidade de Bloqueio Tpica A tenso de gatilho pico a pico requerida limita as escolhas de CIs que possam comandar diretamente o MCT. Os circuitos de comando so tipicamente energizados por um transformador e um retificador para prover a isolao CC. O sinal de comando geralmente ser acoplado por fibra tica ou por meio de um optoacoplador. Uma opo de circuito de comando implementada e testada por Franklin Miguel [4], apresentada na figura 6.

INEP - INSTITUTO DE ELETRNICA DE POTNCIA

11

MCT - MOS CONTROLLED THYRISTOR

+20V

R2 470 W

D1 +20V 1N4148 Q1 BD139 RG 1W G

+20V

R1 540 W

C1 3.3 nF

D2 1N4148

RA 470W A RB 330 W

CA 22 uF

Vin

Q3 2N3819

R3 330W

D3 1N4148

Q2 BD140

CB 10 uF

C2 1 nF

D4 1N4148

Fig. 6 - Sugesto para circuito de Comando

Coeficiente de Temperatura da Tenso Um importante aspecto da queda de tenso em conduo o valor de corrente para o qual o coeficiente de temperatura zero. Abaixo deste valor o coeficiente negativo, ou seja, a tenso decresce com a temperatura. Acima do mesmo a queda de tenso em conduo aumenta conjuntamente com a corrente, denotando um coeficiente de temperatura positivo. Do ponto de vista do paralelismo, vantajoso fixar-se na regio de coeficiente positivo. Dependendo da configurao do circuito, pode-se operar acima da capacidade de comutao de pico de um nico componente. Para a operao acima da corrente de coeficiente de temperatura zero, o circuito deve ser ressonante ou a mesma deve ser conduzida a um nvel de comutao segura.

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MCT - MOS CONTROLLED THYRISTOR

COMPARAO: MCT VERSUS IGBT

Em muitas aplicaes, os requisitos de cada circuito especfico pode influenciar bastante na comparao. Ambos possuem o gatilho isolado, so interruptores controlados por campo, com valores da temperatura da juno em torno de 150oC. Sendo uma mescla bipolar/MOS, as duas estruturas so aplicveis em circuitos de comutao de potncia onde requer-se 600V ou mais, usados tambm em freqncias de comutao mais altas do que geralmente praticado com transistores Darlington de potncia. Em circuitos de alta potncia, a remoo de calor tem impacto significativo no tamanho e na natureza do encapsulamento. Portanto, perdas de comutao e em conduo perfazem o primeiro confronto dos citados a seguir: Queda de Tenso em Conduo A mais importante caracterstica do MCT a queda de tenso em conduo, com valores situados de 1/3 a 1/2 dos valores do IGBT, aumentando modestamente mesmo em grandes picos de corrente, diferindo do seu concorrente. Comutao O disparo no MCT iniciado pelo gatilho e completado regenerativamente como um SCR. Apresenta rapidez, grande capacidade de di/dt e de picos de corrente, com baixas perdas em conduo. No IGBT o disparo , com freqncia, intencionalmente lento para controlar a recuperao reversa do diodo de circulao, porm com sacrifcio das perdas em conduo.Os melhores IGBTs fabricados atualmente podem superar o ento P-MCT na velocidade de bloqueio apresentando menores perdas por ciclo de comutao (grosseiramente por um fator 2).

INEP - INSTITUTO DE ELETRNICA DE POTNCIA

13

MCT - MOS CONTROLLED THYRISTOR

A deciso final a ser tomada para a escolha do componente depende da proporo entre as perdas no chaveamento e em conduco, ou seja, depender do circuito em questo. Tenso de Operao Segura de Bloqueio (SOA) A rea de operao segura de bloqueio descreve o lugar geomtrico das combinaes permissveis de tenso e corrente atravs do interruptor que no provoque a sua operao indevida. Para o P-MCT, a corrente nominal de bloqueio sustentvel de 50% a 60% do valor da tenso de ruptura, contra os 80% do IGBT, que apresenta uma melhor rea de operao segura.

ONDE USAR O MCT?

Em qualquer circuito dominado por perdas de conduo, a primeira gerao de PMCT pode reduzir pela metade as perdas e a rea ativa de silcio: um componente menor e mais eficiente. Na substituio a GTOs e transistores bipolaress, ele oferece a considervel vantagem do gatilho MOS. Tambm em circuitos de comutao dissipativa, em freqncias de muitos KHz e abaixo, o P-MCT pode ser uma boa escolha, apesar da provvel necessidade de um circuito limitador de tenso (geralmente um simples capacitor: snubber) para mant-lo na rea de operao segura. O seu uso pode tornar-se desinteressante em circuitos onde as perdas de comutao so equivalentes s perdas de conduo. Na substituio de um IGBT com perdas de conduo de 50W e de comutao de 30W por exemplo, o lucro seria pequeno: a primeira gerao de MCTs tipo P, apresentaria perdas por conduo < 25W, mas suas perdas de comutao seriam aproximadamente 60W.

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14

MCT - MOS CONTROLLED THYRISTOR

Em circuitos de comutao dissipativa ou PWM, as baixas perdas de comutao do IGBT sobrepujam as baixas perdas de conduo do MCT, particularmente em freqncias acima de 10 Khz. Em circuitos PWM, a maior tenso na rea de operao segura de bloqueio do IGBT de 600V, cerca de 480V, podem torn-lo a soluo preferida para tenses contnuas entre 300V e 400V. Com MCTs tipo P o uso de capacitores limitadores ou componentes com valores mais elevados torna-se necessrio para a operao nesta mesma faixa. Circuitos de descarga de pulso geralmente favorecem o MCT, devido velocidade de disparo e grande capacidade de picos de corrente sob baixa queda de tenso. Apesar de suas caractersticas, o MCT ainda no preenche todos as lacunas em eletrnica de potncia. Em freqncias de comutao acima de 50Khz na comutao dissipativa e acima de 100Khz na comutao suave, os MOSFETs de potncia ainda afirmam-se como a nica soluo prtica no momento (1995).

REFERNCIAS BIBLIOGRFICAS
[1]V. Temple, Power Device Evolution and the MOS-Controlled Thyristor, PCIM, Nov,1987 pp 23-29; [2] V.A.K. Temple, S. D. Arthur et al., Megawatt MOS Controlled Thyristor for High Voltage Power Circuits, PESC 92 Proceedings, pp 1018-1025 (Toledo, Spain, June 29 - July 3, 1992) [3] Manual do Fabricante - Harris Semiconductor, 1994. [4] Franklin Miguel, MCT, Relatrio de Estgio, PET-EEL, 1995.

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15

Semiconductor

April 1999

PRO

CE

IGNS WN DRA EW DES H T I TW ON PAR ETE - N L BSO SS O

MCTV75P60E1, MCTA75P60E1
JEDEC STYLE TO-247 5-LEAD
ANODE ANODE CATHODE GATE RETURN GATE

75A, 600V P-Type MOS Controlled Thyristor (MCT)

Package

Features
75A, -600V VTM = -1.3V(Maximum) at I = 75A and +150oC 2000A Surge Current Capability 2000A/s di/dt Capability MOS Insulated Gate Control 120A Gate Turn-Off Capability at +150oC

Description
The MCT is an MOS Controlled Thyristor designed for switching currents on and off by negative and positive pulsed control of an insulated MOS gate. It is designed for use in motor controls, inverters, line switches and other power switching applications. The MCT is especially suited for resonant (zero voltage or zero current switching) applications. The SCR like forward drop greatly reduces conduction power loss. MCTs allow the control of high power circuits with very small amounts of input energy. They feature the high peak current capability common to SCR type thyristors, and operate at junction temperatures up to +150oC with active switching.
PART NUMBER INFORMATION PART NUMBER MCTV75P60E1 MCTA75P60E1 PACKAGE TO-247 MO-093AA BRAND MV75P60E1 MA75P60E1

JEDEC MO-093AA (5-LEAD TO-218)

ANODE ANODE CATHODE GATE RETURN GATE

Symbol
G A

NOTE: When ordering, use the entire part number.

Absolute Maximum Ratings

TC = +25oC, Unless Otherwise Specied MCTV75P60E1 MCTA75P60E1 UNITS V V A A A A V V A/s W W/oC oC oC

Peak Off-State Voltage (See Figure 11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDRM Peak Reverse Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Cathode Current (See Figure 2) TC = +25oC (Package Limited) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TC = +90oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Repetitive Peak Cathode Current (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peak Controllable Current (See Figure 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gate-Anode Voltage (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gate-Anode Voltage (Peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rate of Change of Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rate of Change of Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Lead Temperature for Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (0.063" (1.6mm) from case for 10s) NOTE: VRRM IK25 IK90 IKSM IKC VGA VGAM dv/dt di/dt PT TJ, TSTG TL

-600 +5 85 75 2000 120 20 25 See Figure 11 2000 208 1.67 -55 to +150 260

1. Maximum Pulse Width of 250s (Half Sine) Assume TJ (Initial) = +90oC and TJ (Final) = TJ (Max) = +150oC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper ESD Handling Procedures. Copyright

Harris Corporation 1999

File Number

3374.6

2-18

Specications MCTV75P60E1, MCTA75P60E1

Electrical Specications
PARAMETER Peak Off-State Blocking Current TC = +25oC Unless Otherwise Specied SYMBOL IDRM TEST CONDITIONS VKA = -600V, VGA = +18V Peak Reverse Blocking Current IRRM VKA = +5V VGA = +18V On-State Voltage VTM IK = IK90, VGA = -10V Gate-Anode Leakage Current Input Capacitance IGAS VGA = 20V VKA = -20V, TJ = +25oC VGA = +18V L = 200H, IK = IK90 RG = 1, VGA = +18V, -7V TJ = +125oC VKA = -300V TC = +150oC TC = +25oC TC = +150oC TC = +25oC TC = +150oC TC = +25oC MIN TYP MAX 3 100 4 100 1.3 1.4 200 UNITS mA A mA A V V nA

CISS

10

nF

Current Turn-On Delay Time Current Rise Time Current Turn-Off Delay Time Current Fall Time Turn-Off Energy Thermal Resistance

tD(ON)I

300

ns

tRI tD(OFF)I

200 700

ns ns

tFI EOFF RJC

1.15 10 .5

1.4 .6

s mJ
oC/W

Typical Performance Curves

300 120 110 IK , DC CATHODE CURRENT (A) 100 90 80 70 60 50 40 30 20 10 1 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 25 35 45 55 65 75 85 95 105 115 125 135 145 155 PACKAGE LIMIT

IK, CATHODE CURRENT (A)

100

PULSE TEST PULSE DURATION - 250s DUTY CYCLE < 2%

TJ = +150oC 10 TJ = TJ = +25oC

-40oC

VTM, CATHODE VOLTAGE (V)

TC, CASE TEMPERATURE (oC)

FIGURE 1. CATHODE CURRENT vs SATURATION VOLTAGE (TYPICAL)

FIGURE 2. MAXIMUM CONTINUOUS CATHODE CURRENT

2-19

MCTV75P60E1, MCTA75P60E1 Typical Performance Curves (Continued)

500 TD(ON)I , TURN-ON DELAY (ns) TJ = +150oC, RG = 1, L = 200H TD(OFF)I , TURN-OFF DELAY (s) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 10 20 30 40 50 60 70 80 90 100 110 120 VKA = -200V VKA = -300V TJ = +150oC, RG = 1, L = 200H

400

300

VKA = -300V

200

VKA = -200V

100

0 10

20

30

40

50

60

70

80

90

100

110 120

IK, CATHODE CURRENT (A)

IK, CATHODE CURRENT (A)

FIGURE 3. TURN-ON DELAY vs CATHODE CURRENT (TYPICAL)

FIGURE 4. TURN-OFF DELAY vs CATHODE CURRENT (TYPICAL)

500

TJ = +150oC, RG = 1, L = 200H

2.0 1.8

TJ = +150oC, RG = 1, L = 200H

400 tFI , FALL TIME (s) tRI, RISE TIME (ns)

1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 VKA = -200V VKA = -300V

300 VKA = -200V 200 VKA = -300V 100

0 10

20

30

40 50 60 70 80 90 IK , CATHODE CURRENT (A)

100

110

120

0.0 10

20

30

40 50 60 70 80 90 IK , CATHODE CURRENT (A)

100

110

120

FIGURE 5. TURN-ON RISE TIME vs CATHODE CURRENT (TYPICAL)

TJ = +150oC, RG = 1, L = 200H VKA = -300V VKA = -200V

FIGURE 6. TURN-OFF FALL TIME vs CATHODE CURRENT (TYPICAL)

20.0 VKA = -300V TJ = +150oC, RG = 1, L = 200H

EOFF, TURN-OFF SWITCHING LOSS (mJ)

EON, TURN-ON SWITCHING LOSS (mJ)

5.0

10.0

VKA = -200V

1.0

0.1 10

20

30

40 50 60 70 80 90 IK, CATHODE CURRENT (A)

100

110

120

1.0 10

20

30

40 50 60 70 80 90 IK , CATHODE CURRENT (A)

100

110

120

FIGURE 7. TURN-ON ENERGY LOSS vs CATHODE CURRENT (TYPICAL)

FIGURE 8. TURN-OFF ENERGY LOSS vs CATHODE CURRENT (TYPICAL)

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MCTV75P60E1, MCTA75P60E1 Typical Performance Curves (Continued)

fMAX , MAX OPERATING FREQUENCY (kHz) 100 EON 0, tD(ON) I 0 VKA = -200V VKA = -300V fMAX1 = 0.05(tD(ON) I + tD(OFF) I) fMAX2 = (PD - PC) / ESWITCH PD: ALLOWABLE DISSIPATION PC: CONDUCTION DISSIPATION (PC DUTY FACTOR = 50%) RJC = 0.5oC/W 100 IK , CATHODE CURRENT (A) 200 IK , PEAK CATHODE CURRENT (A) EON = tD(ON) I = 0 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 0 -50 TJ = +150oC, VGA = 18V, L = 200H

10

TURN-OFF SAFE OPERATING AREA

1 10

-150 -250 -350 -450 VKA , PEAK TURN OFF VOLTAGE (V)

-550

FIGURE 9. OPERATING FREQUENCY vs CATHODE CURRENT (TYPICAL)

TJ = +150oC, VGA = 18V -725 VDRM, BREAKDOWN VOLTAGE (V) -700 -675 -650 -625 -600 -575 -550 -525 -500 -475 -450 -425 0.1 1.0 10.0 100.0 dv/dt (V/s) 1000.0 10000.0

FIGURE 10. TURN-OFF CAPABILITY vs ANODE-CATHODE VOLTAGE

-200 CS = 0.1F, TJ = +150oC CS = 1F, TJ = +150oC SPIKE VOLTAGE (V)

-100 CS = 0.1F, TJ = +25oC

-10

CS = 2F, TJ = +150oC CS = 1F, TJ = +25oC CS = 2F, TJ = +25oC

-1 1 6 11 16 21 26 31 di/dt (A/s) 36 41 46

FIGURE 11. BLOCKING VOLTAGE vs dv/dt

FIGURE 12. SPIKE VOLTAGE vs di/dt (TYPICAL)

Operating Frequency Information

Operating frequency information for a typical device (Figure 9) is presented as a guide for estimating device performance for a specic application. Other typical frequency vs cathode current (IAK) plots are possible using the information shown for a typical unit in Figures 3 to 8. The operating frequency plot (Figure 9) of a typical device shows fMAX1 or fMAX2 whichever is smaller at each point. The information is based on measurements of a typical device and is bounded by the maximum rated junction temperature. fMAX1 is defined by fMAX1 = 0.05 / (tD(ON)I + tD(OFF)I). tD(ON)I + tD(OFF)I deadtime (the denominator) has been arbitrarily held to 10% of the on-state time for a 50% duty factor. Other definitions are possible. tD(ON)I is defined as the 10% point of the leading edge of the input pulse and the point where the cathode current rises to 10% of its maximum value. tD(OFF)I is defined as the 90% point of the trailing edge of the input pulse and the point where the cathode current falls to 90% of its maximum value. Device delay can establish an additional frequency limiting condition for an application other than TJMAX. tD(OFF)I is important when controlling output ripple under a lightly loaded condition. fMAX2 is dened by fMAX2 = (PD - PC) / (EON + EOFF). The allowable dissipation (PD) is dened by PD = (TJMAX - TC) / RJC. The sum of device switching and conduction losses must not exceed PD. A 50% duty factor was used (Figure 10) and the conduction losses (PC) are approximated by PC = (VAK IAK) / (duty factor/100). EON is dened as the sum of the instantaneous power loss starting at the leading edge of the input pulse and ending at the point where the anodecathode voltage equals saturation voltage (VAK = VTM). EOFF is dened as the sum of the instantaneous power loss starting at the trailing edge of the input pulse and ending at the point where the cathode current equals zero (IK = 0). The switching power loss (Figure 10) is defined as fMAX2 (EON + EOFF). Because Turn-on switching losses can be greatly influenced by external circuit conditions and components, fMAX curves are plotted both including and neglecting turn-on losses.

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MCTV75P60E1, MCTA75P60E1 Test Circuits

200H

VG RURG8060

+ -

IK

VK

DUT 20V

10k CS DUT

500

VA

9V

4.7k IK

FIGURE 13. SWITCHING TEST CIRCUIT

FIGURE 14. VSPIKE TEST CIRCUIT

MAXIMUM RISE AND FALL TIME OF VG IS 200ns VG 10% 90%

VG di/dt

-VKA 90%

IK VSPIKE VTM

IK

10% tD(OFF) I tF I tR I tD(ON) I VAK

FIGURE 15. SWITCHING TEST WAVEFORMS

FIGURE 16. VSPIKE TEST WAVEFORMS

Handling Precautions for MCT's

MOS Controlled Thyristors are susceptible to gate-insulation damage by the electrostatic discharge of energy through the devices. When handling these devices, care should be exercised to assure that the static charge built in the handler's body capacitance is not discharged through the device. MCT's can be handled safely if the following basic precautions are taken: 1. Prior to assembly into a circuit, all leads should be kept shorted together either by the use of metal shorting springs or by the insertion into conductive material such as *ECCOSORB LD26 or equivalent. 2. When devices are removed by hand from their carriers, the hand being used should be grounded by any suitable means - for example, with a metallic wristband. 3. Tips of soldering irons should be grounded. 4. Devices should never be inserted into or removed from circuits with power on. 5. Gate Voltage Rating - Never exceed the gate-voltage rating of VGA. Exceeding the rated VGA can result in permanent damage to the oxide layer in the gate region. 6. Gate Termination - The gates of these devices are essentially capacitors. Circuits that leave the gate open-circuited or oating should be avoided. These conditions can result in turn-on of the device due to voltage buildup on the input capacitor due to leakage currents or pickup. 7. Gate Protection - These devices do not have an internal monolithic zener diode from gate to emitter. If gate protection is required an external zener is recommended.
Trademark Emerson and Cumming, Inc.

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