I.

CIRCUIT BASICS Electrical quantities Current: I =

dq dt

[Units: C/s = Amps (A)]

Voltage: V = dw
dq

[Units: J/C = Volts (V)]

dq Power: P = dw = dw = VI

dt dq dt [Units: J/s = Watts (W)] T avg power: P = 1 I (t )V (t )dt T 0

P = IV > 0: power delivered P = IV < 0: power extracted

Primitive circuit elements Voltage Source Current Source

Resistor follows Ohms Law: V = IR (note polarity) R = resistance [Units: V/A = Ohms ()] G = 1/R = conductance [Units: Siemens (S)] Resistor power dissipation: P = IV = I 2 R = V
2

Circuit definitions Node point where 2 or more circuit elements are connected Series elements same current flows through all elements Parallel elements same voltage across all elements

II. CIRCUIT ANALYSIS BASICS

KCL (Kirchhoffs Current Law) Sum of all currents entering a node = 0 Sum of all currents leaving a node = 0 (currents in) = (currents out)

KVL (Kirchhoffs Voltage Law) Sum of voltage drops around a loop = 0 Sum of voltage rises around a loop = 0 (voltage drops) = (voltage rises)
n 1 1 = Req k =1 R k

Series resistors:

Req =

k =1

Rk

Parallel resistors:

Req = R1 + R2

Req = R1 || R 2 =

R1 R 2 R1 + R 2

1 1 1 1 = + + Req R1 R 2 R3

Voltage divider

Current divider

V2 =

R2 VS R1 + R 2

V3 =

R3 VS R1 + R 2 + R3

I2 =

R1 IS R1 + R2

1 I3 = 1 R1 + 1

R3 + 1 R3

IS

R2

Source combinations (series voltage sources and parallel current sources)

III. CIRCUIT ANALYSIS METHODS

Nodal Analysis finds unknown node voltages in a circuit; once all node voltages are known, currents can be found through IV relationships of circuit elements (e.g., Ohms Law) 1. Choose a reference node (ground) 2. Define unknown voltages (those not fixed by voltage sources) 3. Write KCL at each unknown node, expressing current in terms of node voltages - use IV relationships of the circuit elements (e.g., I=V/R for resistors) 4. Solve the set of independent equations (N eqns for N unknown node voltages) Supernode for a floating voltage source (where both terminals are unknown voltages), define a supernode around the source, write KCL at supernode, and use the voltage source equation
V I1 + I 2 = x V + y

R1

R2

VF = V y Vx

Superposition In any linear circuit containing multiple independent sources, any I or V in the circuit can be calculated as the sum of the individual contributions of each source acting alone o Linear circuit circuit with only independent sources and linear elements (linear RLC, linear dependent sources). Linear elements have linear IV characteristics. 1. Leave one source on and turn off all other sources replace voltage source with short circuit (V=0) replace current source with open circuit (I=0) 2. Find the contribution from the on source 3. Repeat for each independent source. 4. Sum the individual contributions from each source to obtain the final result

Note: Superposition doesnt work for power, since power is nonlinear (P=I2R=V2/R)

Thevenin/Norton Equivalent Circuit Models Any linear 2-terminal network of independent sources and linear resistors can be replaced by an equivalent circuit consisting of 1 independent voltage source in series with 1 resistor (Thevenin) or 1 independent current source in parallel with 1 resistor (Norton). The circuit models have the same IV characteristics.

Three variables: Vth=Voc, Rth=RN, IN=Isc. Thevenin/Norton relationship: Vth=INRth only 2 of the 3 variables are required Vth = Voc: open-circuit voltage Leave the port open (IL=0) and solve for Voc. IN = Isc: short-circuit current Short the port (VL=0) and solve for IN. Rthc: Thevenin/Norton resistance Turn off all independent sources (leave the dependent sources alone). If there are no dependent sources, simplify the resistive network using series and parallel reductions to find the equivalent resistance. If dependent sources are present, attach Itest or Vtest and use KCL/KVL to find Rth=Vtest/Itest.
note the direction of Itest and the polarity of Vtest

V R th = test I test

Source Transformations conversion between Thevenin and Norton equivalent circuits Maximum Power Transfer Theorem power transferred to load resistor RL is maximized when RL=Rth

Load-line Analysis graphical method solving circuits with 1 nonlinear circuit element graph the IV curves for the nonlinear circuit element and the Thevenin/Norton equivalent of the rest of the circuit on the same axes; the operating point is where the two curves intersect

IV. CAPACITORS AND INDUCTORS

Capacitor passive circuit element that stores electric energy Capacitance: C = Q/V [Units: Coulombs/Volt = Farads (F)]

IV relationship:

ic = C
2

dvc dt

note polarity!

Energy stored: Ec = CV voltage across capacitor vc cannot change instantaneously: vc(0-)=vc(0+) in steady-state, capacitor is an open circuit (dvc/dt=0ic=0) low freq: open circuit; high freq: short-circuit n Parallel capacitors: Ceq = Ck Series capacitors: 1 = n 1
k =1

Ceq

k =1 Ck

Capacitive voltage divider

V2 =

C1 VS C1 + C 2

1 V3 = 1 C1 + 1

C3 + 1 C3

VS

C2

Inductor passive circuit element that stores magnetic energy Inductance: L = /I [Units: Webers/Amps = Henrys (H)]

IV relationship:

vL = L
2

diL dt

note polarity!

Energy stored: EL = LI current through inductor iL cannot change instantaneously: iL(0-)=iL(0+) in steady-state, inductor is a short circuit (diL/dt=0vL=0) low freq: short circuit; high freq: open-circuit n Series inductors: Leq = Lk Parallel inductors: 1 = n 1
k =1

Leq

k =1 Lk

Capacitor and Inductor Summary :

Capacitor Inductor
v=L

IV relationship Energy storage Continuity Steady-state Series Parallel

i=C

Ec = CV2 Voltage: vc(0-)=vc(0+) Open circuit (I=0)

n 1 1 = Ceq k =1Ck

dv dt

EL = LI2 Current: iL(0-)=iL(0+) Short circuit (V=0)

Leq =
k =1 n

di dt

Lk

Ceq =

k =1

Ck

1 1 = Leq k =1 Lk

V. FIRST-ORDER CIRCUITS

RC circuit contains only sources, resistors, and 1 capacitor RL circuit contains only sources, resistors, and 1 inductor voltages and currents are described by 1st-order ODE (ordinary differential equation) RC Circuits RL Circuits

RC

dvc (t ) + vc (t ) = vi (t ) dt

RC

dvc (t ) + vc (t ) = ii (t ) R dt

v (t ) L di L (t ) + i L (t ) = i R R dt

L diL (t ) + iL (t ) = ii (t ) R dt

Time constant: = RC
st

Time constant: = L/R

Time-domain Analysis for 1 -order Circuits 1. Write the ODE in terms of the variable of interest X(t), using KCL/KVL and IV relationships for R, L, C. 2. Find the homogeneous solution Xh(t) by setting input to 0 and substituting Xh(t)=Ke-t/ as the solution to find the time constant (=RC for RC circuit and =L/R for RL circuit) . (Note: The value of K cannot be found until the complete solution is found in Step 4.) 3. Find the particular solution Xp(t). Remember the output follows the form of the input: input function constant exponential sinusoid -t -t particular solution A Ae + Bte Acos(wt)+Bsin(wt) Guess the form of the solution and solve the ODE to find any arbitrary constants.
(Note: For sinusoidal inputs, the particular solution can be found more easily using complex impedance.)

4. Combine the homogeneous and particular solutions to get the complete solution: X(t) = Xh(t)+Xp(t). Use the initial conditions to find the missing variables (i.e., the K in Xh(t)). Example: Find vc(t>0) for RC circuit w/ vi(t)=VDD, vc(0-)=0V. dv (t ) t K t 2) vc,h(t) = Ke-t/ RC 1) RC c + vc (t ) = vi (t ) e + Ke = 0 = RC dt 3) Since vi(t) is a constant, guess vc,p(t)=A. Plugging into the ODE, A=VDD=vc,p(t). 4) vc(t) = vc,h(t) + vc,p(t) = Ke-t/ + VDD. vc(0-)=vc(0+) by capacitor voltage continuity. vc(0)=0=K+VDD K=-VDD. So, vc(t) = VDD-VDDe-t/. Note: Xh(t) represents the transient response of the circuit and should decay to 0 as time passes. Xp(t) represents the steady-state response of the circuit which persists after the transients have died away and which takes the form of the input.
Time constant amount of time for the transient exponential response e-t/ to decay by 63% (e-1 = 0.63). In 5 time constants, the response decays by 99%. Faster circuits have smaller . General 1st-order Transient Response for Voltage/Current Step
X (t ) = X f + X (t o ) X f e (X is any voltage or current in the circuit) Xf = final value, to = time voltage/current step occurred (1) Find initial value X(to+) and final value Xf. Use continuity (x(0-)=x(0+)) and steady-state rules (open/short) for cap/ind. (2) Calculate (=RC for RC circuit, =L/R for LR circuit). R is the Thevenin equivalent resistance seen by the cap/ind.

(t t o )

VI. SECOND-ORDER CIRCUITS

RLC circuit contains only sources, resistors, 1 capacitor, and 1 inductor voltages and currents are described by 2nd-order ODE (ordinary differential equation) General 2nd-order ODE: Error! Bookmark not defined.
dx(t ) + o 2 x(t ) = f (t ) 2 dt dt = damping coefficient, o = undamped natural freq (AKA resonant freq) = /o = damping ratio, f(t) = forcing function (related to the input) + 2 d 2 x(t )

Series RLC Circuit

=
1 R 2 L 1 o = LC

Parallel RLC Circuit

=
1 2 RC 1 o = LC

d 2 i (t ) dt
2

R di (t ) 1 1 dvi (t ) + i(t ) = L dt LC L dt
st

d 2 v(t ) dt
2

1 dv(t ) 1 1 dii (t ) v(t ) = + RC dt LC C dt

Time-domain Analysis for 2 -order Circuits 1. Write the ODE in terms of the variable of interest X(t), using KCL/KVL and IV relationships for R, L, C. 2. Obtain the characteristic equation by setting the input to 0 and substituting X(t)=Kest into the ODE: s2+2s+ o2=0. Find and o. The roots of the characteristic equation are s1,2 = 2 o 2 ; the form of the solution depends on the damping ratio = /o.

3. Find the homogeneous solution Xh(t) depending on :

overdamped: critically damped: underdamped:

> o , > 1 = o , = 1 < o , < 1

X h (t ) = K1e

( + 2 o )t
2

+ K 2e

( 2 o )t
2

X h (t ) = K1e t + K 2te t
X h (t ) = K1e t cos( n t ) + K 2 e t sin( n t )

n = o 2 2 = damped natural frequency

(Note: The value of K1 and K2 cannot be found until the complete solution is found.) 4. Find the particular solution Xp(t). Remember the output follows the form of the input: input function constant exponential Sinusoid particular solution A Ae-t + Bte-t Acos(wt)+Bsin(wt) Guess the form of the solution and solve the ODE to find any arbitrary constants.
(Note: For sinusoidal inputs, the particular solution can be found more easily using complex impedance.)

5. Combine the homogeneous and particular solutions to get the complete solution: X(t) = Xh(t)+Xp(t). Use the initial conditions to find the missing variables (i.e., K1, K2 in Xh(t)).

VII. SINUSOIDAL STEADY-STATE ANALYSIS

Any steady-state (SS) voltage or current in a linear time-invariant (LTI) circuit with a sinusoidal input source is sinusoidal with the same frequency. Only the magnitude and phase (relative to the source) may be different.

Phasors vectors (i.e., complex numbers) that represent sinusoids. Since all V,I in the circuit are sinusoids with the same frequency, only magnitude & phase are needed to describe any V,I. sinusoids: v(t) = Vcos(t+) = Re[Vej(t+)] = Re[Vejet] phasor: Vej = V v(t) = Vsin(t+) = Vcos(t+-/2) phasor: V(-/2) For convenience, define phasors in terms of cosine (i.e., the real part of a complex exponential)

Eulers Identity: e jx = cos( x) + j sin( x) , cos( x) = 1 e jx + e jx , sin( x) = 1 e jx e jx

2 2j d dt

Differentiation/integration become algebraic operations w/ phasors (i.e., complex exponentials) j

dt

1 j
1 jC

Ex: d e j (t + ) = je j (t + )
dt

Capacitor Impedance:

ZC =

ICE Current (I) LEADS Voltage (EMF) by 90

Inductor Impedance: Z L = jL ELI Voltage (EMF) LEADS Current (I) by 90 Complex Impedance/Generalized Ohms Law: Z = V
I

allows for easy nodal analysis (no differential equations); series/parallel resistor laws apply Maximum Average Power Transfer Theorem power transferred to load impedance ZL is maximized when ZL=Zth* Decibel (dB) unit of measure for ratios of power, voltage, and current levels (often used to express gain). Power: 1dB=10log10(P1/P2); V,I: 1dB=20log10(V1/V2)=20log10(I1/I2) Frequency Response systems inputoutput transfer function vs. frequency (given sinusoidal input). Both magnitude and phase plots are needed (output freq = input freq) General transfer function can be written as a product of poles and zeroes Error! Bookmark not defined.
H ( ) = Ae
j

1 + 1 + z1 zeroes roots numerator z2 of the ( j )n j of the poles roots denominator j 1 + 1 +

p1

p2

H ( j ) H ( j )

Break point frequency BP poles and zeros are break point freqs at a zero frequency, the magnitude is +3dB (=2) and the phase is +45 at a pole frequency, the magnitude is -3dB (=1/2) and the phase is -45 Bode Plot logarithmic plots for frequency response Aej
A 0dB 1
+

j
+ 20 dB
dec

1/j
20 dB
dec

(1+j/z)
40 dB 20 dB 0dB
+ 20 dB dec

1/(1+j/p)
p
0dB 20 dB 40 dB
10 p 10 p

0dB 1

z z 10 z
10

+
+

20 dB

H ( j )

p
z z 10 z
10

dec

0
2

10 p 10 p

to draw Bode plot for general transfer function, add individual pole and zero plots

Filters Lowpass Filter (LPF) VC in RC circuit / VR in RL circuit / VC and RLC circuit (for current output, switch from series to parallel and switch L and C)

H () =

Vout Vin

1 1+ jL R

H ( ) =

Vout Vin

1 1+ jRC

H ( ) =

Vout Vin

1 2 1+ jRC + ( j ) LC

Highpass Filter (HPF) VL in RL circuit / VR in RC circuit / VL in RLC circuit (for current output, switch from series to parallel and switch L and C)

H ( ) =

Vout jL R = Vin 1+ jL R

H ( ) =

Vout jRC = Vin 1+ jRC

H ( ) =

Vout Vin

LC 2 1+ jRC + ( j ) LC

( j )

Bandpass Filter (BPF) VR, IR in RLC circuit

H ( ) =

Vout jRC = 2 Vin 1+ jRC + ( j ) LC

1 Z C = j C

at low freq, cap. impedance

dominates

I = Z in Zin = jCVin , Vout = IR jRCVin tot C

in in I = Z in Zin = j , V = IR jL L out R tot L

at high freq, ind. impedance Z L = jL dominates

Resonant Frequency o = 1

LC

At o, Z C = 1 = j L = jZ o , Z L = jo L = + j L = + jZo Vout = Vin j o C C C (capacitor and inductor impedances are equal in magnitude, opposite in sign) Characteristic Impedance: Z o = L C

BPF Bandwidth = 2 = difference between half-power frequencies Quality Factor Q (1) measure of peakiness or filter selectivity (high Q low bandwidth) (2) measure of energy stored vs. energy dissipated (high Q low loss)
Q=

= 1

series RLC: Q =

Zo = R

LC R

parallel RLC: Q = R =
Zo

R LC

Tradeoffs: Bandwidth/selectivity/speed/energy loss (e.g., high Q low (high selectivity) low slow transients e-t)

VIII. DIODES Passive devices that only pass current in one direction

Shockley Diode Equation: i D = I S e v D Vth 1

IS = reverse-bias saturation current (~10-12 A for Silicon) Vth = kBT/q = thermal voltage (~26mV @ room temp T=300K)

Large-Signal Diode Model (simplifies circuit analysis) 2 states: on forward bias (vD = VT): iD 0 off reverse bias (vD < VT): iD = 0 VT = threshold voltage ~ 0.6V Ideal Diode Model (Perfect Rectifier) large-signal diode model with VT = 0 Zener Diode (simplified) iD 0 3 states: forward bias: vD = VT, reverse bias: VBD < vD < VT, iD = 0 iD 0 breakdown: vD = VBD, Diode Circuit Analysis Method of Assumed States (1) Guess the state of each diode (on or off). For large-signal diode model, replace on diodes with voltage source with voltage drop VT and off diodes with open circuits. (2) Solve the circuit using KCL/KVL. (3) Check if assumptions for diode states were correct (i.e., check that on diodes have iD 0 and off diodes have vD < VT). If not, start over, guessing new states for the diodes. Rectifier Circuit

Peak Detector Circuit (VT=0)

AC-DC Converter (VT=0)

IX. MOSFET

Metal Oxide Semiconductor Field Effect Transistor

(transistor a 3+ terminal device in which one terminal controls the current flow between the other two terminals)

For a MOSFET, the gate controls the current flow between source and drain. For an n-channel MOSFET (NMOS), a positive gate voltage produces current flow For a p-channel MOSFET (PMOS), a negative gate voltage produces current flow Circuit Symbols:

NMOS

PMOS

NMOS Physical Structure:

analog

digital

NMOS IV Characteristic Square Law Model 3 regions of operation: IDS = 0 cutoff VGS < VTn VGS > VTn triode/linear IDS = Kn(VGS-VTn-VDS/2)VDS VDS VGS - VTn VGS > VTn saturation IDSAT = Kn(VGS-VTn)2 VDS VGS -VTn VGS = VGVS , VDS = VDVS VTn = threshold voltage (NMOS) VDSAT = VGS - VTn = saturation voltage IDSAT = saturation current Kn = constant determined by manufacturing process and transistor size (units: A/V2) Channel-Length Modulation Parameter In the saturation region, IDS is not perfectly constant for all VDS VDSAT; as VDS increases, IDS also increases. An additional factor (1+VDS) in the IV equation models this effect (the factor is also added to the triode equation to make the IV curve continuous): IDS = 0 cutoff VGS < VTn

triode/linear saturation

VGS > VTn VDS VDSAT VGS > VTn VDS VDSAT

IDS = Kn(VGS-VTn-VDS/2)VDS(1+nVDS) IDS = Kn(VGS-VTn)2(1+nVDS)

PMOS IV Characteristic Square Law Model Same as NMOS, but switch polarity for everything (VTp is typically negative) ISD = 0 cutoff VSG < -VTp VSG > -VTp triode/linear ISD = Kp(VSG+VTp-VSD/2)VSD(1+pVSD) VSD VSG + VTp VSG > -VTp saturation ISD = Kp(VSG+VTp)2(1+pVSD) VSD VSG +VTp

X. MOSFET CIRCUIT ANALYSIS

Notation: uppercase w/ uppercase subscript (e.g., VIN, VOUT) DC large signal lowercase w/ lowercase subscript (e.g., vin, vout) AC small signal lowercase w/ uppercase subscript (e.g., vIN, vOUT) total signal, DC+AC

Large-signal Analysis find DC operating point (models nonlinearity of MOSFET IV equation) Method 1: Load-line (graphical) Analysis. Requires MOSFET IV curves. Method 2: Method of Assumed States. Large-signal (1) Guess region of operation for each MOSFET. Circuit Model (2) Solve circuit with KCL/KVL/nodal analysis, substituting appropriate IV equation for MOSFET IDS. (3) Check that assumptions for MOSFET operating regions were correct (triode: VGS VT, VDS VGS-VT; saturation: VGS VT, VDS VGS-VT). If not, start over, guessing new operating regions for the MOSFETs. Small-signal Analysis find small-signal gain, Rin, Rout (use a linearized circuit model for the MOSFET) small-signal circuit model is a linearized model for the MOSFET, only valid for small signals near a given DC operating point (AKA quiescent point) Small-signal allows for linear circuit theory (superposition, phasor analysis) Circuit Model

transconductance: g m = DS vGS Q

1 output resistance: ro = 1 =
g ds

i DS v DS Q

Note: Evaluate small-signal parameters at DC operating point ro small-signal parameter Gm triode/linear saturation

MOSFET Amplifier Analysis

(1) Large-signal analysis Find DC operating point w/ load-line analysis or method of assumed states. (2) Small-signal analysis Zero out all DC sources, replace MOSFETs with small-signal model, and find gm and ro for each MOSFET at the DC operating point. To find voltage gain Av = vout/vin, solve for vout using KCL/KVL/nodal analysis. To find Rin and Rout, zero out all independent sources and find Rth at the input and the output (this may require VTEST/ITEST method).

KVDS(1+VDS) K(VGS-VT)(1+VDS)

small VDS: 1/[K(VGS-VT)] 1/[K(VGS-VT)2]

Common Source Amplifier

Large Signal

Small Signal Av=vout/vin = -gm(ro || RD) Rin = Rout = ro || RD

XI. OP-AMPS Operational amplifier high-gain voltage amplifier with differential inputs and single output
Circuit Symbol Circuit Model Input/Output Characteristic

Vo = A(Vp-Vn), Vo = [VSS,VDD] Note: Vo cannot exceed the power supply rails VDD and VSS A = Gain, Rin = input resistance, Rout = output resistance Ideal op-amp: A , Rin , Rout 0 Negative Feedback since its hard to make the op-amp gain stable over all operating conditions (the gain fluctuates with temperature, process variation, and power supply noise), negative feedback is used to stabilize the op-amp output
negative feedback usually occurs when the output is connected to the negative input terminal

Suuming Point Constraint for ideal op-amp in negative feedback (2) vp=vn (for stable Vo=A(Vp-Vn), A=) (1) ip=in=0 (since Rin=) Op-amp Analysis (1) Check for negative feedback. (2) Apply summing point constraint.
(3) Solve the circuit using circuit-analysis techniques (remember that Vo cannot exceed the supply rails).

Op-amp Circuits
Inverting Amplifier Noninverting Amplifier Unity-gain Buffer

Vout Vin

R2 R1

Vout Vin

= 1+

R1 R2

Vout Vin

=1

Adder

Subtractor

R R Vout = R3 V1 + R3 V2 2 1

Vout =

R2 (V V2 ) R1 1

Integrators

Vout = j1 Vin RC

Vout = 1 Vin j L R

Vout Vin

( j )

1
2

LC

Differentiators

Vout = jRC Vin

Vout Vin

= j L R

Vout Vin

= ( j )2 LC

Cascading Op-amp Circuits Find gain of each stage and multiply them together to get total gain

XII. DIGITAL CIRCUITS

analog: signals (voltage and current) are continuous with time digital: signals are discrete (e.g., 0 and 1) advantage: less sensitive to noise, easier to transmit

Booelan Algebra Primitive Rules

Associative Commutative Distributive Identity Identity Complement Idempotence Absorption Absorption A + (B + C) = (A + B) + C A+B=B+A A + (B C) = (A + B) (A + C) A+1=1 A+0=A A + A= 1 A+A=A A + (A B) = A A + ( A B) = A + B A (B C) = (A B) C AB=BA A (B + C) = (A B) + (A C) A0=0 A1=A A A= 0 AA=A A (A + B) = A A ( A + B) = A B

Common Gates (Note: Bubble means inversion)

DeMorgans Laws (AKA bubble pushing)

(1) A B = A + B (2) A + B = A B

A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Out 1 0 1 0 1 0 0 0

Truth Tables list output value for each input combination (2n entries for n inputs) Sum of Products Form write output logic expression as sum (OR) of
products (ANDs), where each product corresponds to each 1 entry in the truth table

Ex: Out = A B C + A B C + A B C

MOSFET Switch Models (NMOS)

Ideal Switch Model Switch-Resistor Model

Noise Margins
Voltage Output High/Low: VOH=F(VOL), VOL=F(VOH) Voltage Input High/Low (VIH, VIL):
where voltage transfer curve slope=-1

Noise Margin High/Low: NMH = VOHVIH NML = VILVOL Logic Swing: VOHVOL

NMOS Inverter (Resistor Pull-up)

Loadline Analysis:

NMOS Inverter Disadvantages: No rail-to-rail swing (low noise margins) Large RD required to keep VOL low and power low [I=VDD/(RD+Ron)] Large RD means large area and slow transient response for Vout=0VDD

CMOS Inverter

Voltage-Transfer Characteristic:

Loadline Analysis:

CMOS Inverter Advantages:

Rail-to-rail swing (big noise margins) No static power consumption (either NMOS or PMOS off)

NMOS Pass Strong 0, Weak 1 For Vin=VDD: Since VGSVTn for NMOS on and VGS=VDDVOUT, VDDVoutVTn, VoutVDDVTn NMOS cant pass strong 1

PMOS Pass Strong 1 , Weak 0 (same analysis as above)

General CMOS Logic Gate Implementation

Pull-up network (PUN) and Pull-down network (PDN) are complementary (only one is on at a time), so Vout is either VDD or GND (0 or 1) PUN and PDN are duals of each other (parallel transistors in one network are series transistors in the other network)

Procedure: (1) Express logic as F = ( X ) , the NOT of some logic expression X. (2) Since F=0 when X=1, construct PDN from X. Series NMOS=AND, parallel NMOS=OR. (3) Construct the PUN as the dual of the PDN.

CMOS Inverter Propagation Delay delay from input to output due to output load capacitance

measured between 50% transition points of the input and output signals use switch-resistor model for MOSFETs

high-to-low delay (NMOS on):

low-to-high delay (PMOS on):

tpHL=0.69RnCL

tpLH=0.69RpCL

average propagation delay: tp = (tpHL+tpLH)/2

General CMOS Gate Delay replace MOSFETs with switch-resistor model, find Req for PUN or PDN, tp=0.69ReqCL