Q) body effect : Usually, in an integrated circuit there will be several MOSFETs and in order to maintain cut-off condition for

all MOSFETs the body substrate is connected to the most negative power supply (in case of PMOS most positive power supply). This causes a reverse bias voltage between source and body that effects the transistor operation, by widening the depletion region. The widened depletion region will result in the reduction of channel depth. To restore the channel depth to its normal depth the VGS has to be increased. This is effectively seen as change in the threshold voltage - Vt. This effect, which is caused by applying some voltage to body is known as body effect. Q) what are the various factors that effect the thresh hold voltage aapart for body effect.

12. Why is NAND gate preferred over NOR gate for fabrication? Explain???? NAND is a better gate for design than NOR because at the transistor level the mobility of electrons is normally three times that of holes compared to NOR and thus the NAND is a faster gate. Additionally, the gate-leakage in NAND structures is much lower. If you consider t_phl and t_plh delays you will find that it is more symmetric in case of NAND ( the delay profile), but for NOR, one delay is much higher than the other(obviously t_plh is higher since the higher resistance p mos's are in series connection which again increases the resistance). 14. Explain sizing of the inverter? Why? In order to drive the desired load capacitance we have to increase the size (width) of the inverters to get an optimized performance. 17. What happens to delay if you increase load capacitance? Which delay and how?????/ delay increases. Q) what is scaling Q) limitations in increasing the power supply to reduce delay Q)For CMOS logic, give the various techniques you know to minimize power consumption? Q) What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus Q) Why is the substrate in NMOS connected to Ground and in PMOS to VDD? Q)Which transistor has higher gain. BJT or MOS and why? Q) Why is bjt cccd and mos vccd Q)All of us know how an inverter works. What happens when the PMOS and NMOS are interchanged with one another in an inverter? Does it act like a buffer ?
Q) Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel Length Modulation Q) Explain the various MOSFET Capacitances & their significance

Q) In the design of a large inverter, why do we prefer to connect small transistors in parallel
(thus increasing effective width) rather than lay out one transistor with large width? if we design inverter with lage width gate capasitance increases , thus input capacitance ofinverter increases.

if we use parellel connection of small transistors ,all gate capasitances will be in parellel then resultant capasitance decreases. There are two reasons 1. Small transistors share active areas, so total diffusion capacitance seen is less 2. Signal EM violation are bound to occur with single large transisor, with small transistors thereparallel paths

How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM?s performance? Draw a 6-T SRAM Cell and explain the Read and Write operations How can you model a SRAM at RTL Level?