IPASJ International Journal of Electronics & Communication (IIJEC)

A Publisher for Research Motivatin........

Volume 1, Issue 1, June 2013

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm Email: editoriijec@ipasj.org ISSN 2321-5984

Modulator with Low power Using ChargePump Based Switched-Capacitor Integrator

Seyed ali sadatnoori1
1

sama technical and vocational training school,Islamic azad university, dezfoul branch, dezfoul, iran

ABSTRACT
Modified charge-pump based switched-capacitor integrator is a promising technique to reduce opamp power dissipation. In this paper, design methodologies are introduced to incorporate such kind of integrator into a low-power delta-sigma modulator. A second-order sigma-delta modulator was designed and simulated to verify the proposed modulator topology.

Keywords: sigma delta modulator, low power, quantization noise, switched-capacitor integrator

1. INTRODUCTION
Switched-capacitor (SC) ADCs are widely used in high -resolution applications for their insensitiveness to parasitics and relaxed accuracy requirements. However, the SC circuit introduces kT/C noise due to the thermal noise generated by the on-resistance of the sampling switches. The oversampling ratio (OSR) in high-resolution low-to-medium bandwidth ADCs may be large, and the quantization noise in such applications is easy to suppress by increasing the loop order, internal quantizer resolution and OSR. Recently, Nilchi and Johns proposed a new SC integrator which has a lower kT/C noise for the same power dissipation (or lower power dissipation for the same kT/C noise) compared to conventional SC integrator [1]. It uses a voltage doubling input branch. Figure 1 compares the Nilchi-Johns integrator with a conventional one.

Figure 1 (a) Conventional SC integrator. (b) Nilchi-Johns integrator. However, the kT/C noise depends only on the OSR, sampling capacitor size and input topology. For the same kT/C noise specification and the same input topology, the power dissipation of the first integrator remains almost unchanged for different OSRs. This is because the sampling capacitor size can be halved for every doubling of the OSR. The power

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IPASJ International Journal of Electronics & Communication (IIJEC)

A Publisher for Research Motivatin........

Volume 1, Issue 1, June 2013

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm Email: editoriijec@ipasj.org ISSN 2321-5984

dissipation of the input integrator with halved load and doubled speed is roughly unchanged, neglecting the parasitics and the load capacitance. The power consumption of the quantizer and the digital decimation filter is proportional to the operating speed. Therefore, the overall dissipation can be reduced by using a low OSR, while at the same time ensuring enough quantization noise suppression. However, the OSR cannot be too low. One reason is quantization noise suppression concern mentioned above; another reason is that the chip area would be very big for large sampling capacitor size. There are ongoing efforts to effectively extend the bandwidth of an SC modulator while maintaining low power consumption. Basically, two approaches can be explored to achieve this commitment. The first one deals with architecture innovation. Amongst various new modulator architectures, low-power topology [2-5] is a very attractive one. The other approach focuses on transistor level design[7-8]. This paper proposes a new modulator topology to incorporate the modified charge pumping based SC integrator into a low-distortion feed-forward modulator. The paper is organized as follows: Section II introduces the new SC input integrator for ADCs. Section III analyzes the new integrator, and compares its properties with those of a conventional SC integrator. In Section IV, ADCs with the new SC integrator and the conventional one are simulated and compared. Section V summarizes the paper.

2.

LOW POWER SC INTEGRATOR

Figure 2 shows the general structure of the new SC integrator. 1 and 2 here are non -overlapping clock phases. During 1, all the Ns sampling capacitors are connected in parallel. The effective sampling capacitor is Cs during 1. The voltage difference Vin-Vdac is stored on the sampling capacitors. Here, Vin is the input signal and Vdac is the feedback DAC output of the ADC. The difference of Vin and Vdac becomes smaller for a higher resolution feedback DAC and a more slowly moving input, which means a higher resolution internal quantizer and a higher OSR. This is true for high-resolution low-to-medium bandwidth ADCs. A charge pumping based SC integrator is shown in Figure 3 in a singleended configuration. Vin is the input signal and Vdac comes from feedback DAC. In this integrator, sampling capacitor Cs is divided into two halves with CS1=CS2=CS/2. During sampling phase 1, input signal is sampled on two capacitors. During integration phase 2, CS1 and CS2 are connected in series and discharge into the integrating capacitor CF. Applying charge conservation, the transfer function of this charge pumping based SC integrator can be expressed as: (1)

Figure 2 The general structure of the low-power SC integrator As can be seen from (1), the integrator gain can be accurately set by the capacitor ratio. Compared to a conventional parasitic insensitive SC integrator, charge pumping based SC integrator offers a smaller capacitive loading and a larger feedback factor when realizing the same integrator gain and same input thermal noise level. One potential drawback for this charge pumping based SC integrator is that the 1/2Vdac term in (1) can reduce the modulator dynamic range by as much as 8dB which is truly undesired in a low supply voltage design.

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IPASJ International Journal of Electronics & Communication (IIJEC)

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Volume 1, Issue 1, June 2013

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Figure 3 A charge pumping based SC integrator A modified charge pumping based SC integrator is proposed in [6] aiming to mitigate the input dynamic range reduction while maintaining all the other advantages of the charge pumping based SC integrator. The circuit is shown in Figure 4 in a single-ended configuration. Feedback DAC voltage is sampled during 1 instead of 2. Applying charge conservation, the transfer function of this modified charge pumping based SC integrator can be expressed as: (2) The gain of the modified charge pumping based SC integrator remains unchanged but the 1/2 term before the Vdac is eliminated which means modulator input full scale range is not limited to be less than half the V dac.

3.

LOW POWER SIGMA DELTA MODULATOR USING CHARGE PUMPING BASED SC INTEGRATOR

To achieve a broadband and low power modulator design, it is an effective measure to combine low power topology and charge pumping based SC integrator simultaneously. Original charge pumping based SC integrator can fit into the low-power topology without any problem. However, employing the modified charge pumping based SC integrator is not straightforward since there is an explicit half-cycle delay in the modulator feedback path due to the fact that input signal and the feedback DAC signal are sampled at the same clock phase. Adding this half-cycle delay into the feedback path of a feed-forward modulator causes instability. As a consequence, some measures should be taken to mitigate this additional half-cycle delay. Figure 4 shows the proposed low-power modulator topology which is able to adopt the modified charge pumping based SC integrator as the very first integrator. A second order modulator is shown here for simplicity. Nevertheless, the concept hereby can be extended to arbitrary order of modulator. The key point here is to make the first integrator half-cycle delayed instead of one-cycle delayed. This modification restored the NTF of the modulator which makes the modulator loop stable. Applying linear analysis, NTF of this particular second-order modulator is:

Figure 4 Proposed second order low-power modulator

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IPASJ International Journal of Electronics & Communication (IIJEC)

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Volume 1, Issue 1, June 2013

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As a demonstration of the proposed topology, a feed-forward second order modulator with modified charge pumping based SC integrator as the very first integrator was designed. The opamps were represented by macro models with finite DC gain (50dB). The dynamic behavior of the proposed modulator was simulated in HSPICE Spectre simulator. The output digital bits were sampled and processed in MATLAB. In the simulation, we assume a 6MHz signal bandwidth, an input signal at 1.95MHz, an oversampling ratio of 15, and a 8-level internal quantizer. Figure 5 shows the simulated output spectrum of the proposed second-order low-power modulator with a -1.5 dBFS input signal. Simulated SQNR=69.4dB which does not include thermal noise.

Figure 5 simulated PSD of a second-order modulator with low-power topology

4.

CONCLUSION

A new modulator topology is proposed to effectively employ the modified charge pumping base SC integrator in a low-power configuration. A second order modulator with the proposed technique was designed and simulated to verify the effectiveness. The low power feature at both architecture level and transistor level makes it a good candidate for broadband, high linearity and low power applications.

Figure 1 Testing data- load current (amperes)

References
[1] A. Nilchi, D.A. Johns, Charge-pump based switched-capacitor integrator for modulators, Electron. Lett., 46, (6), pp. 400401, 2010. [2] H. Park, K. Nam, D.K. Su, K. Vleugels and B.A. Wooley, A 0.7-V 870-W Digital-Audio CMOS Sigma-Delta Modulator, IEEE J. Solid-State Circuits, vol. 44, no. 4, pp.10781088, March 2009. [3] Guessab S, Benabes P and Kielbasa R: A passive delta-sigma modulator for low-power applications. IEEE Circuits and Systems 2004; 3: 295-298. [4] Thompson H, Hufford M, Evans W and NaviaskyE: A low-voltage low-power sigma-delta modulator with improved performance in overload condition. IEEE Custom Integrated Circuits Conference; 519 522, 2004. [5] E.Bonizzoni,A.Pena-Perez,F.Maloberti,andM.Garcia-Andrade,Third-Order sigma delta Modulator with 61-dB SNR and 6- MHz Bandwith Consuming 6mW, Proc .of the IEEE European Solid-State Circuits Conference (ESSCIRC), pp.218-221, Sept.2008.

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IPASJ International Journal of Electronics & Communication (IIJEC)

A Publisher for Research Motivatin........

Volume 1, Issue 1, June 2013

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm Email: editoriijec@ipasj.org ISSN 2321-5984

[6] T. Wang and G.C.Temes, Low power switched-capacitor integrator for ADCs, in submission to MWCAS 2010. [7] K. Lee, J. Chae, M. Aniya, K. Hamashita, K. Takasuka, S. Takeuchi and G. C. Temes, A noise-coupled timeinterleaved ADC with 4.2MHz BW, -98dB THD and 79dB SNDR, in ISSCC Dig. Tech. Papers, Feb. 2008, pp. 494-495.\ [8] Y. Fujimoto, Y. Kanazawa, P. Lo Re and M. Miyamoto, An 80/100MS/s 76.3/70.1dB SNDR ADC for Digital TV Receivers, in ISSCC Dig. Tech. Papers, Feb. 2006, pp. 76-77. AUTHOR

Seyed ali sadat noori received his B.Sc.degree in Electrical Engineering from the Islamic Azad University Dezfoul Branch and M.Sc.degree in Electrical Engineering from the Central Tehran Branch Islamic Azad University, respectively, in 2001 and 2006.He is currently a Ph.D. student in Electrical Engineering at the Research and Science Branch Islamic Azad University in Tehran and he is also a Lecturer of Shoushtar and Dezfoul Branch Islamic Azad university. His current research interests include sigma delta modulator, operational amplifier, low noise and low power amplifier, etc.

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