ADVANCED POWER MOSFET FOR INTEGRATED DC-DC CONVERTERS

Phil Mawby
&

C. F. Tong
16-May-09

University of Warwick
Founded in 1965 Youthful, innovative, entrepreneurial University of Warwick Relevance to Society; not grounded by heritage and tradition Most dynamic and progressive of UK universities Top 10 UK University Aim to be World Top 50 by 2015

Outline
I. II. III. IV. V. Synchronous Buck DC-DC Converter Power MOSFET fundamentals Power Losses Advanced Power MOSFET Advanced Integration

DC to DC conversion
Probably the fastest growing sector of the power device and power IC market Hand held and portable equipment where efficiency is of utmost importance Generally higher frequency operation allows the magnetic components to be reduced and reduce footprint or system size Can operate into multi-MHz Switched mode power supplies are better than 80% efficient.

Classification
SMPS

Non-isolated

Isolated

Buck

Buck-Boost

Asymmetric

Symmetric

Boost

Flyback

Forward

PushPull

Half bridge Full bridge

Single

Double

Single

Double

Step-Down (Buck) Converter

Low-pass filter Vi + + VD D L VL C R VO +

Diode Voltage (VD)

Diode Voltage (VD)

Diode Voltage (VD)

Output Voltage (Vo)

Thus the boost converter acts like a dc transformer with a variable output voltage, which depends on the duty cycle D, usually 0.1 < D < 0.9

Vo = DVi
Average output current If we assume there are no losses, then

Pi = Po
or,

I iVi = I oVo Io 1 = Ii D

Inductor Current IL

Inductor Current IL

Inductor Current IL

Output Ripple Current

I L
I L (t ) ton

Vi dI I L = ton = D(1 D)T dt L

I L 2
T 2

The ripple Current is usually very small <1%, set by the value of L.

Output Ripple Voltage

If we assume all the ripple current flows through C, then

Q 1 T I L 1 T 2 D(1 D ) VC = = = Vi C 22 2 8 LC

The ripple voltage is usually very small <1%, set by the value of C.

Transient Response
V Transient Respond ?
Load Voltage

Load Current

Large V

Small V

18

Consideration and Performance

Application Transient Response Ripple Efficiency Size and Cost

19

Control of DC-DC Converters

The output voltage is generally required to be maintained within tight limits (say 1%) In order to achieve this, feedback is used The duty cycle is altered to keep Vo constant with variations in the load. The error amplifier may need scaling and compensation to maintain stability
Carrier Vref + Av Compensation components duty cycle + Vo SMPS

comp

PWM

Onstate and Switching losses

A typical switching cycle for a power switch in an inductive circuit is shown below. From this it is easy to produce an estimate of the losses per cycle and hence the average power dissipation. This power needs to be dissipated in a heat sink.
OFF TURN-ON ON TURN-OFF OFF

I,V

dI dt

I RM

dV dt

I tail
ttail tturn-on ton ton time

Smart Chip Power Requirements

< 1V few mV >100A > 100A/s without loosing regulation Increased power density multi-phase (5 x 20A)
Distributed Power

Synchronous Buck duty cycle > 0.1 Isolated forward converter larger voltage steps

AC-DC 5-72V DC-DC DC-DC DC-DC DC-DC DC-DC

Multiphase Synchronous Buck

Two or more converter are connected in parallel Advantages
Can stack up total output current Can reduce ripple Can have a few smaller power devices instead of one big one Larger area for heat dissipation

Another major benefit is the transient respond will be much quicker. For VRM application, fast transient respond is a major requirement.

23

CPU Voltage and Current Specifications

Synchronous Buck
Q1 L C Vin Control Q2 Vo

The synchronous buck converter is a variation of the traditional buck converter. The main switching device is the power MOSFET Q1. The freewheeling diode (usually Schottky device is replaced by a power MOSFET Q2 and is driven in a complementary or synchronous fashion to Q1. A small amount of time delay between the switching sequence of Q1 and Q2 is necessary to prevent cross conduction.

Courtesy of National Semiconductors

Synchronous MOSFET
MOSFET operated in 3rd Quadrant where body diode must not turn on. Gate drive applied to open up channel Must have very low on resistance e.g.. 5m so that voltage drop is low at high currents e.g.. 50A. This MOSFET is fast as it does not depend on minority carriers. Body diode characteristics

MOS characteristics Synchronous operation is in this region in 3rd Quadrant

Driving High Side transistors

Problem is that to drive T1 on its gate must be 15V above its source (Vdc + 15V) High-side transistor T1 T2 Vdc

There are several ways to tackle this: 1) High Voltage IC using a) internal charge pumping b) bootstrap operation 2) 3) Pulse transformer Fully isolated floating power supply

Low-side transistor or other load

Efficiency and Power Loss

FET Loss Controller and Gate Drive Loss

Switching Loss Conduction Loss Body Diode Loss Gate Drive Loss Controller Loss Load and Filter Loss

Phigh side =
Plow side =

Vi I L (Qgd + Qgs ) 2 Fsw + RDS ( on ) I L D 2 IG

Qrr + Qoss 2 Vi Fsw + RDS ( on ) I L (1 D ) 2

Load and Filter loss

PBD = t deadtime FswVF I L

PG = QgVg Fsw

29

Power loss
For below 1Mhz switching frequency As switching frequency increase
Switching loss become very significant Conduction loss stay constant

Aim is to keep the switching losses (Qg) low, while not sacrificing the conduction losses (RdsON) to become higher when designing the power device
Figure taken Brian Lynch and Kurt Hesse 2003 Power Seminar

30

Losses at 5Mhz

Body diode amounts to 28% loss. Total switching loss is 24%+28%=52% Total gate driver loss is 16%
Figure taken from Yali Xiong APEC 07

Low Voltage Buck DC-DC

Low Power DC-DC Converter Market Trends Low Power DC-DC Converter Targets

Figures taken from Prof Wai-Tung Ngs ISPS 08 Short Course

32

Power MOSFET
Vertical
Gate Gate Oxide

Lateral
Gate Drain

n+
P+

Source

N+

Cgd
n

P+

Cgd
N-

N+

Substrate

n+
Drain

Vertical Device is low in RdsON Lateral Device is low in Qg

33

Turn On-Resistance, Rds(ON)

Power MOSFET Structures

MOSFET Extended Drain Orthogonal Gate EDMOS Low Qgd but high on-state Vertical Vertical Trench Split-Gate Vertical Trench Low on-state but higher Qgd Field-balanced Split-Gate

35

Extended Drain
Source N+ P NSubstrate Gate Drain N+

Designed to improve Breakdown Voltage High RdsON Simple to built Well known RESURF method can be use to further optimise the e-field.

36

Orthogonal Gate EDMOS

Source N+ P Gate Drain N+ N-

Substrate

Designed to improve Qgd Gate is buried into vertical direction in TEOS RdsON is around 40mmm2 0.18 CMOS process

Publish by H. Wang et al ISPSD 08

37

VDMOS
Source

Gate N+ P+ P

The channel is horizontal and the current turns through 90 degrees to reach the drain. It is formed by the difference between the two diffusions, and is self-aligned to the gate The P+ sinker is used to reduce the likelihood of the parasitic BJT being turned on, and provides good Ohmic contact to the p-well, which is very important in removing minority carriers. The accumulation layer helps to spread out the current as it emerges from the channel. Trench Technology allow densely packed VDMOS for maximising the density

N- epitaxial layer

Drain

Trench VDMOS
Source N+ P+ P

Gate

N- epitaxial layer N+ Drain

Trench filled with oxide and poly Gate channel is form vertically instead of laterally as in VDMOS This structure shows trench goes into the drift Advantage of trench going into the drift is to encourage RESURF effect Need to have a thicker oxide in drift Improve Qgd due to thicker oxide Still relatively large Qgd

Split-Gate RSO Trench VDMOS

Source N+ P+ P

Gate

Split-Poly

N- epitaxial layer N+ Drain

Poly underneath the channel is spitted Thicker oxide at the drift region. The RESURF effect between trenched still remain Much lower Qgd achieve due to Gate is separated from the drain Slight increase in Qgs Oxide between the poly can be manipulate to decrease Qgs

Fabrication Process

41

E-field of RSO MOSFET

42

Measuring Qgd

Figure taken from R. J. E. Hueting IEEE Electron Devices Aug 04

Qgd of Split Gate RSO

Qgd of Split-gate is clearly smaller than the normal RSO. Should note that Qgs is slightly larger in Splitgate. Qgs can be minimise by manipulating the oxide between the poly.

44

Optimisation
Rds(ON) and Qgd/A is a trade off of each other. E.g. HEXFET is optimised in terms of Rds(ON) by increasing the trench density, but HEXFET will have a high Qgd/A.

45

PiN? Split-Gate Trench VDMOS

Source N+ P+ P

Gate

Split-Poly Intrinsic Intrinsic

Field balanced intrinsic region is introduce between the trenches. Improves the turn-on resistance E-field is better spread Simulation results shows Qgd is improved

N- epitaxial layer N+ Drain

Device Modelling
Potential line PiN SG SG RSO Current flow PiN SG SG RSO

Smart Power IC
Conventional Integrated Chip is use only for signal processing (Analogue or Digital). The power switches are not part of the chip. Smart Power IC is where both the decision making (brain) and power switch (brawn) in one single IC. System in Chip and System in Package.

Brain

Brawn

48

BCD Processes
BCD stands for Bipolar CMOS DMOS Bipolar for precision application, CMOS for signal processing and DMOS for Power Devices Expensive process Figure show some of the variety of the device to choose

Figure taken from EE Times Asia on Semiconductor Technologies for Power Management

49

CMOS Compatible
Dedicated process might be the most optimise but it is expensive Compatible process means there will be compromises but the cost will be cheaper since process is usually is already ready to use Another advantage is to reuse the older processes where the new product is moved to the more expensive process
Wafer start Trench Etch Trench Fill Implantation

Oxidation

50

Power Switch of Buck Converter

Power Switches Vi + + VD D L VL C R VO +

Design Challenges
High side
Low gate charge for switching speed Low RdsON for low conduction loss

Low side
Low conduction loss P-type for easier drive

Due to the different FOM of the two switches, ideally is to have two different design Two different DMOS in an integrated design will cost much more

52

Passives of Buck Converter

Passives Vi + + VD D L VL C R VO +

Integrated Magnetics
Board integration is inductor integrated in substrate, PCB or in PCB substrate Package integration is commercially available (i.e. stacked die) Wafer integration is magnetic integration into silicon

Current
100A Board 10A Integration 1A 100mA 10mA 100K
Wafer Integration Package Integration

1M

10M 100M

f
54

SiP DC-DC Converter

LTM4061AVH
Integrated Filter

Typical System in Package design Filter is integrated into the same chip Stacked die

Figure taken from Linear Technology LTM4061AVH datasheet

55

SiP from NXP

The Passives

Active on Passive

Picture taken Henk Jan Berveld talk at PowSoc 08 Conference

56

System on Chip Challenges

Advanced integrated skill and process required Good integrated magnetic component required Total efficiency need to be above 90% Integration of passives need to be cheap
20 MHz dc-dc converter designed by PERL group in University College Cork Vin = 2.6 V, Vout = 1.2 V Micro-inductor = 110 nH Wire-wound inductor = 110 nH
Figure taken T. ODonnell talk at PowSoc 08 Conference

Micro-inductor efficiency Converter with Micro-inductor Converter with Coilcraft inductor Coilcraft inductor efficiency

57

Conclusions
The market trend is showing more towards integrated solution Integrated chip will rely a lot on the improvement on the passives Faster switching power switch will allow smaller passive but will not solve the efficiency issue of passives Layout and device structure of the power switch is important to reduce the packaging losses
SEM Image of fabricated inductor Closed Core Shape Inductor

Figure taken Shan X. Wang talk at PowSoc 08 Conference

58