The emphasis in VLSI design has shifted from high speed to low power due to the proliferation of portable

electronic systems. Many of the techniques have already been used in low power design with additional techniques emerging continuously at all levels. The goal of this work is to provide a comprehensive study of low-power circuit and design techniques using complementary metal-oxidesemiconductor (CMOS) technology. This will encompass aspects such as circuit design; transistor size, layout technique, cell topology, and circuit design for low power operation while paying particularly attention on the methodology of logic style. This thesis specifically deals with the comparison between static CMOS and complementary pass-transistor logic (CPL) styles, in a 0.35 mum CMOS technology, to determine the most efficient choice for low power design. The comparison study allows a selection procedure between static CMOS and CPL for low-power logic circuits, and provides a set of comparison results for use with other circuit design techniques.

It is widely accepted that, as semiconductor technology continues to evolve, interconnects have dominated over transistors in terms of both performance and power consumption in VLSI. Common belief is that interconnects at the on-chip global level or above in a large extent limit the system performance. While we certainly agree with that, we also believe that local interconnects manifest themselves as critical as the devices in datapath design, if not more so. We intend to show that the interconnect dominance is ubiquitous, and deserves a vertical treatment rather than focusing on a certain level only. In this dissertation, we address several open issues and problems faced by today's designers to reflect the above philosophy: (1) We propose a passive compensation scheme for improving the signal quality over long metal interconnects. The proposed method tries to mimic the behavior of distortionless transmission line by evenly adding shunt resistors between the signal line and ground. Design parameters such as shunt value, spacing and termination are leveraged to achieve the best eye-diagram jitter, and the tradeoff between jitter and eye-opening is also studied. The evaluation of the worst-case jitter and eye-opening is enabled by a fast analytical prediction method based on any given bitonic step response, which is new to the best knowledge of the author. (2) We revisit the design of cyclic shifter by introducing two orthogonal new techniques: fanout splitting and cell order optimization using Integer Linear Programming. Both methods emphasize on reducing the interconnect burden in the shifter network, and significant savings on delay and power are reported. (3) We solve the open problem of constructing zero-deficiency prefix adder of minimum depth. This work complements previous studies of the asymptotic behavior of depth-size tradeoff in prefix adders. To designers, it answers the question of how far should we push the timing so as not to incur exponential cost of area and power in prefix adders. Together these contributions made efforts toward high-performance lowerpower VLSI design in the nanometer era. The demands of future computing, as well as the challenges of nanometer-era VLSI design, require new digital logic techniques and styles that are simultaneously high performance, energy efficient, and robust to noise and variation. We propose a new family of logic styles called Preset Skewed Static Logic (PSSL). PSSL bridges the gap between the two main logic styles, static CMOS logic and domino logic, occupying an intermediate region in the energy-delay-robustness space between the two. PSSL is better than domino in terms of energy and robustness, and is better than static CMOS in terms of delay. PSSL works by

partially overlapping the execution of consecutive iterations through speculative evaluation. This is accomplished by presetting nodes at register boundaries before input arrival.

Testing low power very large scale integrated (VLSI) circuits has recently become an area of concern due to yield and reliability problems. This dissertation focuses on minimising power dissipation during test application at logic level and register-transfer level (RTL) of abstraction of the VLSI design flow. The first part of this dissertation addresses power minimisation techniques in scan sequential circuits at the logic level of abstraction. A new best primary input change (BPIC) technique based on a novel test application strategy has been proposed. The technique increases the correlation between successive states during shifting in test vectors and shifting out test responses by changing the primary inputs such that the smallest number of transitions is achieved. The new technique is test set dependent and it is applicable to small to medium sized full and partial scan sequential circuits. Since the proposed test application strategy depends only on controlling primary input change time, power is minimised with no penalty in test area, performance, test efficiency, test application time or volume of test data. Furthermore, it is shown that partial scan does not provide only the commonly known benefits such as less test area overhead and test application time, but also less power dissipation during test application when compared to full scan. To achieve power savings in large scan sequential circuits a new test set independent multiple scan chain-based technique which employs a new design for test (DFT) architecture and a novel test application strategy, is presented. The technique has been validated using benchmark examples, and it has been shown that power is minimised with low computational time, low overhead in test area and volume of test data, and with no penalty in test application time, test efficiency, or performance. The second part of this dissertation addresses power minimisation techniques for testing low power VLSI circuits using built-in self-test (BIST) at RTL. First, it is important to overcome the shortcomings associated with traditional BIST methodologies. It is shown how a new BIST methodology for RTL data paths using a novel concept called test compatibility classes (TCC) overcomes high test application time, BIST area overhead, performance degradation, volume of test data, faultescape probability, and complexity of the testable design space exploration. Second, power minimisation in BIST RTL data paths is achieved by analysing the effect of test synthesis and test scheduling on power dissipation during test application and by employing new power conscious test synthesis and test scheduling algorithms. Third, the new BIST methodology has been validated using benchmark examples. Further, it is shown that when the proposed power conscious test synthesis and test scheduling is combined with novel test compatibility classes simultaneous reduction in test application time and power dissipation is achieved with low overhead in computational time.