CHAPTER 1

INTRODUCTION

One of the main form of communication that has been in use since 19th century is Radio Wave communication. Radio Waves have found its place in each and every field whether it be medical, electronics or space. In general it exists in every system in one or the other form. Our project demonstrate one such example were Radio Wave is employed in a way which is helpful to us. This project is designed and developed for helping the passengers traveling in train and bus especially during night. The people who are not aware of the station on which one should get down will find this very helpful. Here the station name is displayed and announced simultaneously when the station is about to reach which can assist both literate and illiterate. The RF technology is used in the project to communicate between the transmitter and receiver. Each transmitter has a unique binary code which is transmitted continuously to space in a particular range. This signal is captured by the receiver when it reaches in its range. So in the case of a train, the transmitter placed in the station is detected by the receiver in the train and the binary code is processed to give out the station name display. A LCD unit is used for displaying the station name.

1.1. BLOCK DIAGRAM

The block diagram consists of the transmitter and receiver section. They can be represented as the following block diagrams.

1.1.1. Transmitter

Fig. 1.1 Block Diagram of Transmitter Module

The block diagram of the transmitter is given in fig. 1.1. The main parts in the transmitter are: 1. Power Supply The power supply section is the section which provide +5V for the transmitter section to work. IC LM7805 is used for providing a constant power of +5V. 2. Encoder This section contains the identity of the transmitter. An encoder can be a device used to change a signal (such as a bit stream) or data into a code. The code serves any of a number of purposes such as compressing information for transmission or storage, encrypting or adding redundancies to the input code etc

3. RF Transmitter This section transmits the binary data to space in a particular range based on the antenna used. This signal is received by the receiver and it compares the binary code to find the corresponding station name from the database.

1.1.2. Receiver

Fig. 1.2 Block Diagram of Receiver Module

1. Power Supply The power supply section is the section which provide +5V for the transmitter section to work. IC LM7805 is used for providing a constant power of +5V. 2. Decoder A decoder is a device which does the reverse of the encoder, undoing the encoding so that the original information can be retrieved.
3

3. Microcontroller

Unlike microprocessors, microcontrollers are generally optimized for specific applications. As a result the peripherals can be simplified and reduced which cuts down the production cost.

4. RF Receiver

The RF signal transmitted by the transmitter is detected and received by this section of the receiver. This binary encoder data is sent to the decoder for decoding the original data.

5. LCD

This is the output unit in the receiver section. The station name is displayed on this display unit when the receiver comes in the range of the transmitter.

CHAPTER 2

PROJECT DESCRIPTION

2.1. INTRODUCTION
RF based station name intimation is based traditionally on RF signal. RF signal at the frequency range 434 MHz is employed for communication between transmitter unit and receiver unit in our project. Each station is identified by a unique binary code, for example, 000 for SANGRUR and 111 for NEW DELHI. This binary code is transmitted by transmitter module continuously at a frequency range of 434 MHz within a distance of 400 foot outdoor and 200 foot indoor. This distance can be enhanced by using additional RF antenna. When the receiver comes within the range of transmitter, it receives the data from the transmitter in the form of RF signal which is further decoded to collect the binary code and display the station name respectively.

2.2. TRANSMITTER MODULE

Transmitter section is the smallest section having few components which include: 1. RF transmitter TWS-434 A 2. Encoded HT-12 E 3. Voltage Regulator LM7805. LM7805 assures a constant supply of +5 V for the transmitter module. This voltage of +5 V is used to drive transmitter and encoder.

2.2.1. Circuit Description

The third pin of TWS-434 A RF transmitter and 18th pin of Encoder HT-12E is connected to the output pin of Voltage Regulator LM7805 which drives the circuit with a constant voltage of 5V. The first pin of TWS-434 A and all the address bus are connected to second pin of LM7805 which represent ground. The first pin of voltage regulator receives a voltage of 9V from a battery source. The other connection include a connection between the Dout (7th pin) of HT-12 E and the data pin (2nd pin) of TWS-434 A.

Fig. 2.1 Circuit diagram of Transmitter Module

2.2.2. Working Principle

The binary values unique to each station are assigned by the encoder HT-12E. Each address/data input can be set to the logic state 0 or 1.Grounding the pin is taken as 0 while 1 can be achieved by giving 5V or leaving the pins open (No connection). So in order to get a binary value of 0001 only one pin is pulled high i.e. 13th pin (D11) is pulled high while pins 10, 11 and 12 are grounded to represent logical zero. On receipt of transmit enable i.e. TE-active (14th pin) is pulled low. The data which is here is the binary value is fed as input to the transmitter TWS-434 A from Dout (17th pin) along with header bits. Received data from HT-12E encoder is amplitude modulated and transmitted at a frequency range of 433.92 MHz.

2.3. RECEIVER MODULE

Receiver is the output section of the project. Receiver module includes the following components: 1. RF Receiver RWS-434 A 2. Microcontroller 89S52 which is regarded as the brain of the circuit. 3. LCD module for display the station name 4. Power supply section which contains transformer, rectifier, filter, regulator which ensures a constant +5V. Main function of the receiver unit is to detect the RF signal transmitted by the TWS-434A and give the response according to the received data from the receiver.

2.3.1. Circuit Description

A constant voltage of +5V is applied to the 4th and 5th pin of the receiver, 2nd pin of the LCD module, 40th pin of Microcontroller 89S52 , 18th pin of the decoded IC HT-12D. It derives its input voltage from bridge rectifier. The 8 bit data pins D0 -D7 are used to send information

from port 2 of the microcontroller to the LCD. RS (register select) is one of the important registers inside the LCD. The RS pin is used for their selection as follows. If RS=0, the instruction code register is selected, allowing the user to send a command such as clear display, cursor at home, etc. if RS=1 the data register is selected, allowing the user to send data to be displayed on the LCD.R/W input pin of LCD allows the user to write information to the LCD or read information from it. R/W=1 when reading; R/W=0 when writing. E (enable) the enable pin is used by the LCD to latch information presented on its data pins. When data is supplied to data pins, a high to low pulse must be applied to this pin in order for the LCD to latch in the data present at the data pins. These 3 pins (RS, RW, and E) of LCD are connected to the 89S52 through port 0. The communication between AT 89S52 . Microcontroller receives data from decoder HT-12 D through port 1 which is an 8 bit bidirectional I/O port from the output data pins D8-D11 of HT-12 D. The receiver RWS-434 is connected to decoder such that the received RF signal is fed as input to the data input pin Din (pin 14) of the decoder from 2nd pin of the receiver.
8

Fig. 2.2 Circuit Diagram Receiver Module 9

2.3.2. Working Principle

When the receiver unit comes in the range of transmitter unit which continuously transmit RF signal, the whole receiver unit gets activated. The receiver unit receives the RF signal at a frequency range of 434 MHz which actually is a digital data which includes the binary code assigned to the particular transmitter which denotes a station and a carrier signal. Digital output is taken from pin 2 of RWS-434 and received by decoder HT-12 D through data input pin (18th pin). The received serial input data are compared three times continuously with the local address. If no error or unmatched codes are found, the input codes are decoded and then transferred to the output pins. The VT (Valid Transmission) pin (12th pin) gives high to indicate a valid transmission. The decoded signal is given as data input to AT 89S52 at port 1. On receipt of the binary code microcontroller which act as a database of station name, compares the received binary code with its stored binary code, on no error or unmatched code the station name corresponding to the binary code is displayed on the LCD screen. The whole cycle will be repeated when the receiver receives a new set of binary code transmitted by some other transmitter denoting a different station. The display will be active only for pre defined duration, after which the LCD return to its ideal state. The data to be displayed on the LCD screen is available at port 2 and control of the register of the LCD is through port 3.

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CHAPTER 3 HARDWARE DESCRIPTION 3.1. RF TRANSMITTER

The function of a radio frequency (RF) transmitter is to modulate, up convert, and amplify signals for transmission into free space. An RF transmitter generally includes a modulator that modulates an input signal and a radio frequency power amplifier that is coupled to the modulator to amplify the modulated input signal. The radio frequency power amplifier is coupled to an antenna that transmits the amplified modulated input signal. The RF transmitter used in our project is TWS-434A. This RF transmitter transmits data in the

frequency range of 433.92 MHz with a range of approximately 400 foot (open area) outdoors. Indoors, the range is approximately 200 foot, and will go through most walls. TWS-434A has features which includes small in size, low power consumption i.e. 8mW and operate from 1.5 to 12 Volts- DC, excellent for applications requiring short-range RF signal. Data to be sent is Amplitude modulation with the carrier RF signal.

Fig. 3.1 Pin Description of RF Transmitter 11

3.1.1. Pin Description of Transmitter PIN 1: GROUND (-5V) PIN2: INPUT PIN FOR DATA FROM ENCODER PIN3: SUPPLY (+5V) PIN 4: PIN FOR EXTERNAL RF ANTENNA

3.2. RF RECEIVER
The RF receiver receives an RF signal, converts the RF signal to an IF signal, and then converts the IF signal to a base band signal, which it then provides to the base band processor. As is also known, RF transceivers typically include sensitive components susceptible to noise and interference with one another and with external sources. The RF receiver is coupled to the antenna and includes a low noise amplifier, one or more intermediate frequency stages, a filtering stage, and a data recovery stage. The low noise amplifier receives an inbound RF signal via the antenna and amplifies it. The RF receiver used is RWS-434. This RF receiver receives RF signal which is in the frequency of 434.92 MHz and has a sensitivity of 3uV. The RWS-434 receiver operates from 4.5 to 5.5 voltsDC, and has both linear and digital outputs and its tunable to match the frequency of the transmitter unit

12

.
Fig. 3.2 Pin Description of RF Receiver

3.2.1. Pin Description of Receiver PIN1: GROUND (-5V) PIN2: OUTPUT PIN FOR DIGITAL DATA RECEIVED PIN 3: OUTPUT PIN FOR ANALOG DATA RECEIVED PIN4: SUPPLY (+5V) PIN5: SUPPLY (+5V) PIN6: GROUND (-5V PIN7: GROUND (-5V) PIN 8: PIN FOR EXTERNAL RF ANTENNA

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3.3. ENCODER
An encoder can be a device used to change a signal (such as a bit stream) or data into a code. The code serves any of a number of purposes such as compressing information for transmission or storage, encrypting or adding redundancies to the input code, or translating from one code to another. This is usually done by means of a programmed algorithm, especially if any part is digital, while most analog encoding is done with analog circuitry. Encoder used here is HT 12E. The HT12E encoder is a CMOS IC It is capable of encoding 8 bits of address (A0-A7) and 4- bits of data (AD8-AD11) information. Each address/data input can be set to one of the two logic states, 0 or 1. Grounding the pins is taken as a 0 while a high can be given by giving +5V or leaving the pins open (no connection). Upon reception of transmit enable (TE-active low), the programmed address/data are transmitted together with the header bits via an RF medium.

Fig. 3.3 Pin Diagram of Encoder

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Pin A0~A7

I/O I

Description Input pins for address A0~A7 setting These pins can be externally set to VSS or left open

AD8~AD11

Input pins for address/data AD8~AD11 setting These pins can be externally set to VSS or left open

D8~D11

Input pins for data D8~D11 setting and transmission en- able, active low These pins should be externally set to VSS or left open

DOUT

Encoder serial transmission output

L/MB

Latch/Momentary transmission format selection pin: Latch: Floating or VDD Momentary: VSS

TE OSC1

I I

Transmission enable, active low Oscillator input pin

OSC2

Oscillator output pin

X1 X2 VSS

I 0 I

455kHz resonator oscillator input 455kHz resonator oscillator output Negative power supply, grounds

VDD

Positive power supply

Table. 3.1 Pin Description of Encoder 15

3.4. DECODER
A decoder is a device which does the reverse of an encoder, undoing the encoding so that the original information can be retrieved. The same method used to encode is usually just reversed in order to decode. In digital electronics this would mean that a decoder is a multiple-input, multipleoutput logic circuit that converts coded inputs into coded outputs. Enable inputs must be on for the decoder to function, otherwise its outputs assume a single "disabled" output code word. Decoding is necessary in applications such as data multiplexing, 7 segment display and memory address decoding. The decoder used here is HT 12D. The HT12D is a decoder IC made especially to pair with the HT 12E encoder. It is a CMOS IC. The decoder is capable of decoding 8 bits of address (A0 - A7) and 4 bits of data (AD8- AD11) information. For proper operation, a pair of encoder/decoder with the same number of addresses and data format should be chosen. The decoders receive serial addresses and data from programmed encoders that are transmitted by a carrier using an RF or an IR transmission medium. They compare the serial input data three times continuously with their local addresses. If no error or unmatched codes are found, the input data codes are decoded and then transferred to the output pins. The VT pin also goes high to indicate a valid transmission. The decoders are capable of decoding information that consists of N bits of address and 12_N bits of data. Of this series, the HT 12D is arranged to provide 8 address bits and 4 data bits.

Fig. 3.3 Pin Diagram of Decoder 16

Pin Name A0~A7 (HT12D)

I/O

Description

Input pins for address A0~A7 setting These pins can be externally set to VSS Or left open.

D8~D11 (HT12D) DIN VT

Output data pins, poweron state is low

I 0

Serial data input pin Valid transmission, active high

OSC1 OSC2 VSS

I 0

Oscillator input pin Oscillator output pin Negative power supply, ground

Table. 3.2 Pin Description of Decoder

3.5. LCD MODULE A liquid crystal display (LCD) is an electronically-modulated optical device shaped into a thin, flat panel made up of any number of color or monochrome pixels filled with liquid crystals and arrayed in front of a light source (backlight) or reflector. It is often utilized in battery-powered electronic devices because it uses very small amounts of electric power. LCD has material which combines the
17

properties of both liquids and crystals. Rather than having a melting point, they have a temperature range within which the molecules are almost as mobile as they Would be in a liquid, but are grouped together in an ordered form similar to a crystal. LCD consists of two glass panels, with the liquid crystal materials sandwiched in between them. The inner surface of the glass plates is coated with transparent electrodes which define in between the electrodes and the crystal, which makes the liquid crystal molecules to maintain a defined orientation angle. When a potential is applied across the cell, charge carriers flowing through the liquid will disrupt the molecular alignment and produce turbulence. When the liquid is not activated, it is transparent. When the liquid is activated the molecular turbulence causes light to be scattered in all directions and the cell appears to be bright. Thus the required message is displayed. When the LCD is in the off state, the two polarizers and the liquid crystal rotate the light rays, such that they come out of the LCD without any orientation, and hence the LCD appears transparent. When sufficient voltage is applied to the electrodes the liquid crystal molecules would be aligned in a specific direction. The light rays passing through the LCD would be rotated by the polarizer, which would result in activating/highlighting the desired characters. The power supply should be of +5v, with maximum allowable transients of 10mv. Each row or column of the display has a single electrical circuit. The pixels are addressed one at a time by row and column addresses. This type of display is called passive-matrix addressed because the pixel must retain its state between refreshes without the benefit of a steady electrical charge. As the number of pixels (and correspondingly, columns and rows) increases, this type of display becomes less

18

feasible. Very slow response times and poor contrast are typical of passive matrix addressed LCDs. A general purpose alphanumeric LCD, with two lines of 16 characters. So the type of LCD used in this project is16 characters * 2 lines with 5*7 dots with cursor, built in controller, +5v power supply, 1/16 duty cycle.

3.5.1. LCD Layout

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CHAPTER 4 MICROCONTROLLER
Basically, a microcontroller is a device which integrates a number of the components of a microprocessor system onto a single microchip. So a microcontroller combines onto the same microchip. The following components: a) CPU Core b) Memory (Both RAM and ROM) c) Some Parallel Digital I/Os The microprocessor is the integration of a number of useful functions into a single IC package. Has the ability to execute a stored set of instructions to carry out user defined tasks; also has ability to access external memory chips to both read and write data from and to the memory. Essentially, a microcontroller is obtained by integrating the key components of microprocessor, RAM, ROM, and Digital I/O onto the same chip die. Modern microcontrollers also contain a wealth of other modules such as Serial I/O, Timers, and Analogue to Digital Converters. There are a large number of specialized devices with additional modules for specific needs. E.g. CAN controllers.

4.1. ATMEL 89S52

In our project we are using microprocessor from Atmel namely AT89S52 is a low-power, highperformance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry standard 80C51 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highlyflexible and cost-effective solution to many embedded control applications.

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4.1.1. Pin Description of AT89S52

Fig. 4.1 Pin Diagram of AT89S52

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VCC - Supply voltage. GND - Ground.

PORT 0
Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull-ups are required during program verification.

PORT 1
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups Port 1 also receives the low-order address bytes during Flash programming and verification.

PORT 2
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVX @ DPTR). In this application, it uses strong internal pull- ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the highorder address bits and some control signals during Flash programming and verification.

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PORT 3
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 also serves the functions of various special features of the AT89S52 as listed below: Port 3 also receives some control signals for Flash programming and verification.

RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.

ALE/PROG
Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

PSEN
Program Store Enable is the read strobe to external program memory. When the AT8952 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.

23

EA/VPP
External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.

XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2
Output from the inverting oscillator amplifier.

4.2. OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.

24

4.2.1. Oscillator Connections

Fig. 4.2 Oscillator Connections

4.3. SPECIAL FUNCTION REGISTERS

A map of the on-chip memory area called the Special Function Register (SFR). Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. SFRs are a kind of control table used for running and monitoring microcontrollers operating. Each of these registers, even each bit they include, has its name, address in the scope of RAM and clearly defined purpose ( for example: timer control, interrupt, serial connection etc.). Even though there are 128 free memory locations intended for their storage, the basic core, shared by all types of 8051 controllers, has only 21 such registers. Rests of locations are intentionally left
25

free in order to enable the producers to further improved models keeping at the same time compatibility with the previous versions. It also enables the use of programs written a long time ago for the microcontrollers which are out of production now.

4.4. DATA MEMORY

The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct Addressing access of the SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #data Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). MOV @R0, #data Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.

4.5. TIMER\COUNTERS
The Atmel 80C51 Microcontrollers implement two general purpose, 16-bit timers/ Counters. They are identified as Timer 0 and Timer 1, and can be independently Configured to operate in a variety of modes as a timer or as an event counter. When Operating as a timer, the timer/counter runs for a programmed length of time, and then issues an interrupt request. When operating as a counter, the timer/counter counts negative transitions on an external pin. After a preset number of counts, the counter issues and interrupt request.

26

4.5.1. Timer 0 & Timer 1

Timer 0 is controlled by the four lower bits of the TMOD register and bits 0, 1, 4 and 5 of the TCON register. TMOD register selects the method of timer gating (GATE0), timer or counter operation (T/C0#) and mode of operation (M10 and M00). The TCON register provides timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0). For normal timer operation (GATE0= 0), setting TR0 allows TL0 to be incremented by the selected input. Setting GATE0 and TR0 allows external pin INT0# to control timer operation. Timers 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag, generating an interrupt request. It is important to stop timer/counter before changing mode.

4.5.2. Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle

27

CHPTER 5

SOFTWARE DESCRIPITION

5.1. EMBEDDED LANGUAGE

Embedded software is in almost every electronic device designed today. There is software hidden away inside our watches, microwave, Music system, cellular phones etc .military uses embedded software to guide smart missiles and detect enemy aircraft; communication satellites, space probes and modern medicine could be nearly impossible without it. Embedded software are developed using a different version of c called embedded c which is a different version of c to suit the programming of microcontroller.

5.2. INTRODUCTION TO MULTISIM 11

Multisim is an industry-standard, best-in-class SPICE simulation environment. It is the cornerstone of the NI circuits teaching solution to build expertise through practical application in designing, prototyping, and testing electrical circuits. The Multisim design approach helps you save prototype iterations and optimize printed circuit board (PCB) designs earlier in the process. The Multisim simulator is software simulation tools which provide an accurate simulation of digital and analog circuit operations. Multisim allows us to grasp concepts quicker and gain deeper intuition for circuits. The operating system windows XP/ Vista / 64bit Vista and windows 7 supports fully to this Multisim software. It has been designed to help hardware designers gain better understanding of circuit behavior. Since the quality of simulation results is highly dependent on applied signals as well as the methods of analyzing and displaying simulation. It helps to close gap between design and test. We can interface real world signal from inside Multisim and output data to drive real world circuitry, or display simulation data in a more suitable to our needs. Using this software we can design our project before it is executed on real components. The purpose of this paper is to explore the important features of this software by
28

giving a complete example of interfacing LCD display to 8051 microcontroller. As 8051chip and its family is extensively used in embedded system design and in many embedded applications. And LCD display is most commonly used in embedded system and other electronic devices. Microcontrollers and LCD modules are used in various embedded application s such as copiers fax machines, laser printers industrial test equipment, network equipment: routers and storage devices. We can do many experiments or projects placing various components on workplace area of Multisim software on a PC, do connections, write the assembly The

language program, debug it and run the same to see the result on output devicesconnected.

best way to learn is to experiment; there is no need to afraid to try out complicated circuits and new features in Multisim. So beginner can easy simulate complex circuits. One of the most powerful features of is its interactive nature. It enhances visualization, and makes capture easier.

Fig. 5.1 Multisim 11 screen window

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5.3. Proteus (design software)

Proteus is software for microprocessor simulation, schematic capture, and printed circuit board (PCB) design. It is developed by Labcenter Electronics. PROTUES combines advanced schematic capture, mixed mode SPICE simulation, PCB layout and auto routing to make a complete electronic design system. The PROTUES product range also includes

revolutionary VSM technology, which allows you to simulate micro-controller based design, complete with all the surrounding electronic. Intelligent Schematic Input System (ISIS) lies right at the heart of the PROTUES system and is far more than just another schematic package. It has powerful environment to control most aspects of the drawing appearance. Whether your requirement is the rapid entry of complex design for simulation & PCB layout, Or the creation of attractive Schematic for publication ISIS is the right tool for the job Product Features. VSM (Virtual System Modelling) -Proteus VSM is an extension of the PROSPICE simulator that facilities co-simulation of microprocessor based design including all the associated electronics. Furthermore, you can interact with the microcontroller software through the use of animated keypads, switches, buttons, LEDs, lamps and even LCD displays.

Fig. 5.2 Proteus main window 30

CHAPTER 6

CONCLUSION AND FEATURE

The design and development of RF based station name intimation inside train compartment have been successfully designed, fabricated and tested. With the implementation of low cost and flexibility in design, this kit can reduce our tension in journey to unknown place. This project demonstrates how RF signal along with embedded system can make our life simpler without causing any ill effect or affecting other devices. There are plenty of such examples showing how embedded system makes our life simpler and tension free. Our project has plenty of rooms for expansion like the use of GPS system instead of RF signal, interfacing with pc for different forms of output, harness of solar energy as the unit consumes very low power etc. Its use is not limited to bus stand or railway station, with suitable modification the system can be used to serve other purposes like providing assistance to blind in their homes, providing security for valuable items etc. No radio frequency interference (RFI) to the existing terrestrial wireless systems. We have used 434MHz frequency band for the data transmission, which is specially allotted for experimental purpose. Digital transmissions make more efficient use of spectrum and have better threshold margins. Digital modulations are more robust, are error free, and predictable under most conditions. Coverage range up to 100 feets.

31

REFERENCES

1. Ajay V Deshmukh (2008), Microcontrollers (Theory and Applications), Tata McGraw Hill Publishing Limited. 2. Muhammad Ali Mazidi and Janice Mazidi F (2000), 051 microcontroller and embedded system, Pearson education. 3. Ray and Bhuruchandi (2000), Advanced Microprocessor and Peripherals, Tata McGraw Hill Publishing Company Limited.

4. Websites:

1. www.atmel.com 2. www.rentron.com 3. www.scribd.com

4. www.datasheetarchive.com

32

APPENDIX
List File of the Program-

1 0087 0086 0090 0000 0000 7400 0002 F5A0 0004 90014C 0007 310F 0009 E5FF 000B F590 000D 30945B 0010 30900B 0013 1136 0015 3119 0017 2090FD 001A 3142 001C 80EF 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 001E 001E 900151 0021 3119 0023 3142 0025 900162 0028 3119 22 23 24 25 26 27

$MOD51 rs equ P0.7 en equ P0.6 vt equ P1.0 org 0000h mov a,#00h mov p2,a mov dptr,#lcd_mycmnd acall c1 mov a,0ffh mov p1,a again:jnb P1.4,project_info jnb vt,lcd_m1 acall chk_in acall d1 back:jb vt,back acall clr_dsply sjmp again

lcd_m1: mov dptr,#lcd_dsplay acall d1 acall clr_dsply mov dptr,#lcd_display1 acall d1

33

002A 3147 002C 900173 002F 3119 0031 3142 0033 80D8 0035 22 0036 0036 20910A 0039 209211 003C 209315 003F 90030B 0042 22 0043 0043 209212 0046 209316 0049 90031C 004C 22 004D 004D 209313 0050 90032D 0053 22 0054 0054 90033E 0057 22 0058 0058 20930C 005B 90034F 005E 22 005F 005F 900360

28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

acall l2 mov dptr,#lcd_dsply12 acall d1 acall clr_dsply sjmp again ret chk_in: jb P1.1,chk_b0 jb P1.2,chk_b1 jb P1.3,chk_b2 mov dptr,#lcd_dsply0 ret chk_b0: jb P1.2,chk_b3 jb P1.3,chk_b4 mov dptr,#lcd_dsply1 ret chk_b1: jb P1.3,chk_b5 mov dptr,#lcd_dsply2 ret chk_b2: mov dptr,#lcd_dsply3 ret chk_b3: jb P1.3,chk_b6 mov dptr,#lcd_dsply4 ret chk_b4: mov dptr,#lcd_dsply5
34

0062 22 0063 0063 900371 0066 22 0067 0067 900382 006A 22 006B 006B 900184 006E 3119 0070 3142 0072 900195 0075 3119 0077 3147 0079 9001A6 007C 3119 007E 3142 0080 9001B7 0083 3119 0085 3147 0087 9001C8 008A 3119 008C 3142 008E 9001D9 0091 3119 0093 3142 0095 9001EA 0098 3119 009A 3147 009C 9001FB

59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

ret chk_b5: mov dptr,#lcd_dsply6 ret chk_b6: mov dptr,#lcd_dsply7 ret project_info: mov dptr,#info1 acall d1 acall clr_dsply mov dptr,#info2 acall d1 acall l2 mov dptr,#info21 acall d1 acall clr_dsply mov dptr,#info3 acall d1 acall l2 mov dptr,#info31 acall d1 acall clr_dsply mov dptr,#info4 acall d1 acall clr_dsply mov dptr,#info5 acall d1 acall l2 mov dptr,#info51
35

009F 3119 00A1 3142 00A3 90020C 00A6 3119 00A8 3147 00AA 90021D 00AD 3119 00AF 3142 00B1 90022E 00B4 3119 00B6 3147 00B8 90023F 00BB 3119 00BD 3142 00BF 900250 00C2 3119 00C4 3142 00C6 900261 00C9 3119 00CB 3147 00CD 900272 00D0 3119 00D2 3142 00D4 900283 00D7 3119 00D9 3147 00DB 900294 00DE 3119 00E0 3142 00E2 9002A5

90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119

acall d1 acall clr_dsply mov dptr,#info6 acall d1 acall l2 mov dptr,#info61 acall d1 acall clr_dsply mov dptr,#info7 acall d1 acall l2 mov dptr,#info71 acall d1 acall clr_dsply mov dptr,#info8 acall d1 acall clr_dsply mov dptr,#info9 acall d1 acall l2 mov dptr,#info91 acall d1 acall clr_dsply mov dptr,#info10 acall d1 acall l2 mov dptr,#info101 acall d1 acall clr_dsply mov dptr,#info11
36

00E5 3119 00E7 3147 00E9 9002B6 00EC 3119 00EE 3147 00F0 9002C7 00F3 3119 00F5 3142 00F7 9002D8 00FA 3119 00FC 3147 00FE 9002E9 0101 3119 0103 3147 0105 9002FA 0108 3119 010A 3142 010C 02000D 010F 010F E4 0110 93 0111 3123 0113 3139 0115 A3 0116 70F7 0118 22 0119 0119 E4 011A 93

120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150

acall d1 acall l2 mov dptr,#info111 acall d1 acall l2 mov dptr,#info12 acall d1 acall clr_dsply mov dptr,#info13 acall d1 acall l2 mov dptr,#info131 acall d1 acall l2 mov dptr,#info14 acall d1 acall clr_dsply ljmp again c1: clr a movc a,@a+dptr acall lcd_cmdwr acall delay inc dptr jnz c1 ret d1: clr a movc a,@a+dptr
37

011B 312E 011D 3139 011F A3 0120 70F7 0122 22 0123 0123 F5A0 0125 C287 0127 D286 0129 3139 012B C286 012D 22 012E 012E F5A0 0130 D287 0132 D286 0134 3139 0136 C286 0138 22

151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173

acall lcd_datawr acall delay inc dptr jnz d1 ret lcd_cmdwr: mov P2,a clr rs setb en acall delay clr en ret lcd_datawr: mov P2,a setb rs setb en acall delay clr en ret

0139 0139 78FB 013B 79FB 013D D9FE 013F D8FA 0141 22 0142

174 175 176 177 178 179 180 181

delay: mov r0,#251 v2: mov r1,#251 v1:djnz r1,v1 djnz r0,v2 ret clr_dsply:
38

0142 7401 0144 3123 0146 22 0147 0147 74C0 0149 3123 014B 22

182 183 184 185 186 187 188 189 190 191

mov a,#01h acall lcd_cmdwr ret l2: mov a,#0c0h acall lcd_cmdwr ret

014C 014C 01380C06 0150 00

192 193 194

lcd_mycmnd: db 01h,38h,0ch,06h,00h

0151 0151 2057454C 0155 434F4D45 0159 20544F20 015D 50525443 0161 00 0162 0162 53414E47 0166 5255522D 016A 4E455744 016E 454C4849 0172 00 0173 0173 20202042 0177 55532053 017B 45525649 017F 43452020

195 196

lcd_dsplay: db ' WELCOME TO PRTC',00h

197 198

lcd_display1: db 'SANGRUR-NEWDELHI',00h

199 200

lcd_dsply12: db ' BUS SERVICE ',00h

39

0183 00 201 0184 0184 20534C49 0188 4554204C 018C 4F4E474F 0190 57414C20 0194 00 0195 0195 2046494E 0199 414C2053 019D 454D4553 01A1 54455220 01A5 00 01A6 01A6 20202020 01AA 50524F4A 01AE 45435420 01B2 20202020 01B6 00 01B7 01B7 52462042 01BB 41534544 01BF 20535441 01C3 54494F4E 01C7 00 01C8 01C8 20204E41 01CC 4D452044 01D0 4953504C 01D4 41592020
40

202 203

info1: db ' SLIET LONGOWAL ',00h

204 205

info2: db ' FINAL SEMESTER ',00h

206 207

info21: db ' PROJECT ',00h

208 209

info3: db 'RF BASED STATION',00h

210 211

info31: db ' NAME DISPLAY ',00h

01D8 00 01D9 01D9 5375626D 01DD 69747465 01E1 64204279 01E5 202D2020 01E9 00 01EA 01EA 53414348 01EE 494E204B 01F2 554D4152 01F6 204A4841 01FA 00 01FB 01FB 20202047 01FF 45432D31 0203 30353137 0207 32202020 020B 00 020C 020C 2052414A 0210 4E495348 0214 2052414E 0218 4A414E20 021C 00 021D 021D 20202047 0221 45432D31 0225 30353136 0229 31202020 022D 00
41

212 213

info4: db 'Submitted By ',00h

214 215

info5: db 'SACHIN KUMAR JHA',00h

216 217

info51: db ' GEC-105172 ',00h

218 219

info6: db ' RAJNISH RANJAN ',00h

220 221

info61: db ' GEC-105161 ',00h

022E 022E 56495645 0232 4B204B52 0236 2052414E 023A 4A414E20 023E 00 023F 023F 20202047 0243 45432D31 0247 30353137 024B 30202020 024F 00 0250 0250 50726F6A 0254 65637420 0258 47756964 025C 65202D20 0260 00 0261 0261 2045722E 0265 20534857 0269 45544120 026D 52414E49 0271 00 0272 0272 20284150 0276 20454345 027A 20444550 027E 542E2920 0282 00 0283

222 223

info7: db 'VIVEK KR RANJAN ',00h

224 225

info71: db ' GEC-105170 ',00h

226 227

info8: db 'Project Guide - ',00h

228 229

info9: db ' Er. SHWETA RANI',00h

230 231

info91: db ' (AP ECE DEPT.) ',00h

232

info10:
42

0283 50726F6A 0287 65637420 028B 436F2D6F 028F 7264696E 0293 00 0294 0294 61746F72 0298 202D2020 029C 20202020 02A0 20202020 02A4 00 02A5 02A5 2044722E 02A9 20532053 02AD 20534F44 02B1 48492020 02B5 00 02B6 02B6 28417373 02BA 6F63692E 02BE 2050726F 02C2 662E2920 02C6 00 02C7 02C7 45434520 02CB 44455054 02CF 2E20534C 02D3 49455420 02D7 00 02D8 02D8 204D722E

233

db 'Project Co-ordin',00h

234 235

info101: db 'ator ',00h

236 237

info11: db ' Dr. S S SODHI ',00h

238 239

info111: db '(Associ. Prof.) ',00h

240 241

info12: db 'ECE DEPT. SLIET ',00h

242 243

info13: db ' Mr. J SINGH ',00h

43

02DC 204A2053 02E0 494E4748 02E4 20202020 02E8 00 02E9 02E9 28417373 02ED 742E2050 02F1 726F662E 02F5 29202020 02F9 00 02FA 02FA 45434520 02FE 44455054 0302 2E20534C 0306 49455420 030A 00 248 249 030B 030B 20202020 030F 53414E47 0313 52555220 0317 20202020 031B 00 031C 031C 20202020 0320 50414E49 0324 50415420 0328 20202020 032C 00 032D 254 lcd_dsply2:
44

244 245

info131: db '(Asst. Prof.) ',00h

246 247

info14: db 'ECE DEPT. SLIET ',00h

250 251

lcd_dsply0: db ' SANGRUR ',00h

252 253

lcd_dsply1: db ' PANIPAT ',00h

032D 20202020 0331 50415449 0335 414C4120 0339 20202020 033D 00 033E 033E 20204248 0342 4157414E 0346 49474152 034A 48202020 034E 00 034F 034F 20202020 0353 204B4152 0357 4E414C20 035B 20202020 035F 00 0360 0360 20202020 0364 534F4E49 0368 50415420 036C 20202020 0370 00 0371 0371 20202020 0375 20414D42 0379 414C4120 037D 20202020 0381 00 0382 0382 2020204E

255

db '

PATIALA

',00h

256 257

lcd_dsply3: db ' BHAWANIGARH ',00h

258 259

lcd_dsply4: db ' KARNAL ',00h

260 261

lcd_dsply5: db ' SONIPAT ',00h

262 263

lcd_dsply6: db ' AMBALA ',00h

264 265

lcd_dsply7: db ' NEW DELHI ',00h

45

0386 45572044 038A 454C4849 038E 20202020 0392 00 266 267 268 END

VERSION 1.2k ASSEMBLY COMPLETE, 0 ERRORS FOUND AGAIN. . . . . . . . . . . . . . BACK . . . . . . . . . . . . . . C1 . . . . . . . . . . . . . . . CHK_B0 . . . . . . . . . . . . . CHK_B1 . . . . . . . . . . . . . CHK_B2 . . . . . . . . . . . . . CHK_B3 . . . . . . . . . . . . . CHK_B4 . . . . . . . . . . . . . CHK_B5 . . . . . . . . . . . . . CHK_B6 . . . . . . . . . . . . . CHK_IN . . . . . . . . . . . . . CLR_DSPLY. . . . . . . . . . . . D1 . . . . . . . . . . . . . . . DELAY. . . . . . . . . . . . . . EN . . . . . . . . . . . . . . . INFO1. . . . . . . . . . . . . . INFO10 . . . . . . . . . . . . . INFO101. . . . . . . . . . . . . INFO11 . . . . . . . . . . . . . INFO111. . . . . . . . . . . . . INFO12 . . . . . . . . . . . . . C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR NUMB C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR 000DH 0017H 010FH 0043H 004DH 0054H 0058H 005FH 0063H 0067H 0036H 0142H 0119H 0139H 0086H 0184H 0283H 0294H 02A5H 02B6H 02C7H
46

INFO13 . . . . . . . . . . . . . INFO131. . . . . . . . . . . . . INFO14 . . . . . . . . . . . . . INFO2. . . . . . . . . . . . . . INFO21 . . . . . . . . . . . . . INFO3. . . . . . . . . . . . . . INFO31 . . . . . . . . . . . . . INFO4. . . . . . . . . . . . . . INFO5. . . . . . . . . . . . . . INFO51 . . . . . . . . . . . . . INFO6. . . . . . . . . . . . . . INFO61 . . . . . . . . . . . . . INFO7. . . . . . . . . . . . . . INFO71 . . . . . . . . . . . . . INFO8. . . . . . . . . . . . . . INFO9. . . . . . . . . . . . . . INFO91 . . . . . . . . . . . . . L2 . . . . . . . . . . . . . . . LCD_CMDWR. . . . . . . . . . . . LCD_DATAWR . . . . . . . . . . . LCD_DISPLAY1 . . . . . . . . . . LCD_DSPLAY . . . . . . . . . . . LCD_DSPLY0 . . . . . . . . . . . LCD_DSPLY1 . . . . . . . . . . . LCD_DSPLY12. . . . . . . . . . . LCD_DSPLY2 . . . . . . . . . . . LCD_DSPLY3 . . . . . . . . . . . LCD_DSPLY4 . . . . . . . . . . . LCD_DSPLY5 . . . . . . . . . . . LCD_DSPLY6 . . . . . . . . . . . LCD_DSPLY7 . . . . . . . . . . .

C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR C ADDR

02D8H 02E9H 02FAH 0195H 01A6H 01B7H 01C8H 01D9H 01EAH 01FBH 020CH 021DH 022EH 023FH 0250H 0261H 0272H 0147H 0123H 012EH 0162H 0151H 030BH 031CH 0173H 032DH 033EH 034FH 0360H 0371H 0382H
47

LCD_M1 . . . . . . . . . . . . . LCD_MYCMND . . . . . . . . . . . P0 . . . . . . . . . . . . . . . P1 . . . . . . . . . . . . . . . P2 . . . . . . . . . . . . . . . PROJECT_INFO . . . . . . . . . . RS . . . . . . . . . . . . . . . V1 . . . . . . . . . . . . . . . V2 . . . . . . . . . . . . . . . VT . . . . . . . . . . . . . . .

C ADDR C ADDR D ADDR D ADDR D ADDR C ADDR NUMB C ADDR C ADDR NUMB

001EH 014CH 0080H 0090H 00A0H 006BH 0087H 013DH 013BH 0090H PREDEFINED PREDEFINED PREDEFINED

48