Professional Documents
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A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation of Block LMS Algorithm
WIRELESS COMMUNICATION
FFT Architectures for Real-Valued Signals Based on Radix- and Radix- Algorithms MDC FFT/IFFT Processor With Variable Length for MIMOOFDM Systems A High-Speed Low-Complexity Modified FFT radix-25 Processor for High Rate WPAN Applications BER Analysis and MAI Cancellation in CDMA Communication System Time-Multiplexed Offset-Carrier QPSK for GNSS GF(q) LDPC decoder design for FPGA implementation Efficient implementation of Convolution Encoder and Viterbi Decoder FPGA-Based 40.9-Gbits/s Masked AES With Area Optimization for Storage Area Network
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contourlet transform
The Electronic Piano Design Based on FPGA and PS2 Interface Hardware Implementation of a Digital Watermarking System for
Video Authentication
Low-Cost Low-Power ASIC Solution for Both DAB+ and DAB
Audio
Decoding
Supplying DC Loads
ASIC and FPGA Implementation of the Gaussian Mixture Model
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ARITHMETIC UNITS
Implementation of High Speed and Low Power Hybrid Adder Based Novel Radix 4 Booth Multiplier Architecture and Implementation of a Vector/SIMD MultiplyAccumulate Unit Comparative analysis for hardware circuit architecture of Wallace tree multiplier 8912-Bit Montgomery Multipliers Using Radix-8 Booth Encoding and Coded-Digit Generic modified Baugh Wooley multiplier Design of high performance 64 bit MAC unit Design of high speed hybrid carry select adder Implementation of binary to floating point converter using HDL Reconfigurable architecture for FIR filter with low power consumption Design and implementation of truncated multipliers for precision improvement
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Low-Power Digital Signal Processing Using Approximate Adders Optimized architecture for Floating Point computation Unit An efficient high speed Wallace tree multiplier Enhanced high speed modular multiplier using karatsuba algorithm An FPGA based high speed IEEE-754 double precision floating point multiplier using Verilog Low power multiply accumulate unit (MAC) for future Wireless Sensor Networks Development of optimum addition algorithm using modified parallel hybrid signed digit (MPHSD) technique
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IMAGE PROCESSING
VLSI Implementation of Enhanced Edge Preserving Impulse Noise Removal Technique High density impulse noise removal based on linear mean-median filter Least significant bit matching steganalysis based on feature analysis Satellite image enhancement using discrete wavelet transform and threshold decomposition driven morphological filter An Efficient Denoising Architecture for Removal of Impulse Noise in Images Improved low-cost FPGA image processor architecture with external line memory Fuzzy logic-based implementation of color image processing techniques in FPGA CORDIC Based Fast Radix-2 DCT Algorithm
VLSI TESTING
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Adaptive test clock scheme for low transition LFSR and external LFSR-reseeding scheme for achieving test coverage Implementation of a novel architecture for VLSI testing Efficiency improvement in RNG using a simplified algorithm The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures Multiplierless Algorithm for Multivariate Gaussian Random Number Generation in FPGAs Adaptive Low Power RTPG for BIST based test applications Hardware Trojan Insertion by Direct Modification of FPGA Configuration Bitstream
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Multi-Ternary
Digit
Adder
Design
in
CNTFET
Technology Performance analysis and simulation of two different architectures of (6:3) and (7:3) compressors based on carbon Nano-Tube Field Effect Transistors A Wide Range CMOS VCO for PLL Applications QCA Systolic Array Design Design and analysis of leakage current and delay for Double gate MOSFET at 45nm in CMOS technology A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology A novel high-performance CMOS 1 bit full-adder cell Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs.
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Dual Transform Based Steganography Using Wavelet Families and Thumbnail Selection: Delivering Digital Signage Contents to Mobile Phone Single Remote Sensing Image Dehazing Effective Watermarking Algorithm To Protect Electronic Patient Record Using Image Transform
WIRELESS COMMUNICATION
Multirate Schemes for WH-spread-CI/MC-CDMA Over Correlated Frequency Selective Channel Overlay Cognitive Radio OFDM System For 4G Cellular Networks A General Framework for BER Analysis of OFDMA and ZeroForcing Interleaved SC-FDMA over Nakagami-m Fading Channels with Arbitrary m Partial Transmit Sequence PAPR Reduction Method for LTE OFDM Systems Performance Analysis of OSTBC for Partial Relay Selection with Correlated Antennas over Nakagami-m Fading Design and Implementation of Computationally Efficient MCCDMA Transceiver and Performance Analysis in Fading hannels
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An Adaptive Conditional Zero-Forcing Decoder With FullDiversity, Least Complexity and Essentially-ML Performance for STBCs Carrier Frequency Offset Estimation in OFDMA using Digital Filtering On Higher Order Modulations for OFDM in Frequency-Selective Fading Channels A Weighted OFDM Signal Scheme for Peak-to-Average Power Ratio Reduction of OFDM Signals Audio Watermarking Via EMD Volterra Neural Analysis of Fetal Cardiotocographic Signals A New Suboptimal Selection Combining With Enhanced
Performance for BPSK Over Rayleigh Fading Channels Adaptive Wavelet Wiener Filtering of ECG Signals Adaptive Pixel Pair Matching based Steganography for Audio files.