DFT Rule #1

All internal clocks must be controlled by port level CLK signal (primary input) in scan test mode Issue :
INPUT1
D DTC10 Q

OUTPUT

INPUT2 CLK

D DTC10 CLK

CLK

Gated Clock

DFT Rule #1

Solution:
INPUT1
A

D CLK

OUTPUT

DTC10

INPUT2 CLK

D CLK

MU111

DTC10

TEST_MODE

Circuit Without Internal Clock Violation

DFT Rule #2
Avoid implementation of combination feedback circuit. If present, the feedback loop must be broken to test. Issue:
FEEDBACK SIGNAL

COMBINATIONAL LOGIC INPUT

OUTPUT

The outputs of this circuit cannot be controlled by their inputs alone.

DFT Rule #2
Solution 1:
TEST_MODE

Cannot Control (Much)

Cannot Observe (At All)

COMBINATIONAL LOGIC INPUT

OUTPUT

Issue:
The gate output is not testable for stuck-at faults as it is usually held constant during test. The feedback signal may not be testable (observable) in test mode.

DFT Rule #2
Solution 2:
TEST_MODE
B
MU111

FF

COMBINATIONAL LOGIC INPUT

OUTPUT

Solve the controllability and observability limitation at the cost of increased complexity

DFT Rule #3
Asynchronous SET/RESET pins of flip-flops must be controlled by a port level RESET (primary input) in scan test mode
Test_mode

Issue :
Combinational Logic OR

R D Q

CLK

DFT Rule #3
Solution :
Test_mode RESET from port
1

Combinational Logic

R D Q

CLK

DFT Rule #4
Gated clock must be enabled in scan test mode Issue:

Gated clocks can block the scan chain from shifting

DFT Rule #4
Gated clock must be enabled in scan test mode Solution:

The muxed scan flip-flop observer is not required if the HOLD signal is directly issued from a scan flip-flop.

DFT Rule #5
Latches have to be avoided as much as possible. If present, make it transparent in scan test mode Issue : In an edge-triggered design, it is difficult to put latches on a scan chain because the library does not contain their edgetriggered scan equivalents. If they are not part of a scan chain, their outputs will be difficult to control. The fault coverage will therefore be very low.

DFT Rule #5
Solution :

Process(DATA,ENABLE,TEST) begin if (ENABLE = 1 or TEST = 1) then latch_signal <= DATA; endif; end process;

DFT Rule #6
Do not replace flip-flops of the shift register structure by equivalent scan flipflops. For efficient area purposes, the flip-flops of the shift register structure will not be replace by equivalent scan flip-flops. The SCAN_EN signal have to be added in your VHDL RTL code of the shift register to allow the shift of scan patterns in scan mode. Process(CLK) begin if (CLKEVENT and CLK = 1) then if (RESET = 1 and SCAN_EN = 0) then shifter_bus <= (others => 0); elsif (ACTIVE_SHIFT = 1 or SCAN_EN = 1) then shifter_bus(16 downto 1) <= shifter_bus(15 downto 0); shifter_bus(0) <= DATA_IN; endif; endif; end process;

DFT Rule #7
Clock should not be used as data in scan test mode Issue: For ATPG to be successful, there should be minimal coupling between the clocks and data. When there is any coupling between clock and data, the ATPG tool will have a set of conflicting requirements to satisfy at the same time. This results in loss of test coverage. When the clock pulses, it can create race conditions too. DATA_IN <= DATA AND (CLK OR TEST); Process(CLK) begin if (CLKEVENT and CLK = 1) then D <= DATA_IN; endif; end process;
This can result in a loss of test coverage on combinational logic.

DFT Rule #7
Clock should not be used as data in scan test mode Solution:You must change your VHDL RTL code as shown below

CLK_TEST <= CLK (when TEST = 0) else NON-CLOCK SIGNAL ;

DFT Rule #8
Bypass the Memory in scan test mode Issue:
All the paths ending at Memory cell are not observable All the paths starting from Memory cell are not controllable

Solution:
Write Data Memory Address/ Control Read Data

DFT Rule #9
The SCAN_ENABLE signal must be buffered adequately. Issue:
The scan enable signal that causes all flip flops in the design to be connected to form the scan shift register, has to be fed to all flip flops in the design. This signal will be heavily loaded. The problem of buffering this signal is identical to that of clock buffering. The drive strength of scan enable port on each block of the design must be set to a realistic value when the design is synthesized. If this port is left unconstrained during synthesis, it could result in silicon failure.

DFT Rule #10

Negative edge flops should also be triggered at the same clock edge as positive edge triggered in scan test mode Issue : For ATPG tool to work,in one clock cycle only one capture/shift should happen. With negative edge flip-flops it is not possible.

DFT Rule #10

Solution : Invert the clock for negative edge triggered flip-flops in scan test mode
D Q
0

CLK
1

CLK

Test_mode