2006 IEEE COMPEL Workshop, Rensselaer Polytechnic Institute, Troy, NY, USA, July 16-19, 2006

D-Q-0 Synchronous Frame Average Model for Three-Phase Arrays Of Single-Phase PFC Converter Loads
Bin Huang, Rolando Burgos, Fred Wang, Dushan Boroyevich
Center for Power Electronics Systems The Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg, VA 24061 USA
AbstractThe small-signal modeling of single-phase Power Factor Correction (PFC) converters is limited by the fact that it must deal with time varying ac variables; thus becoming a hindrance for controls design and dynamic interaction analysis. This paper proposes a modeling approach for the analysis of multiple single-phase PFC converters, achieved by aggregating them into a single equivalent three-phase load. This equivalent model may then be readily converted into the d-q-0 synchronous frame where formerly time-varying state variables become dc quantities in steady state. From the resultant average model small-signal analysis may then be easily performed by either analytic or numerical methods. This paper presents the complete derivation of the proposed d-q-0 average model for multiple single-phase PFC converters, using time-domain simulations for verification, exploring as well its small-signal analysis capability by studying the converters input impedance on all three d-q-0 channels. From these results the excellent performance and great usefulness of the model is verified.

I. INTRODUCTION The boost-type three-phase power factor correction (PFC) rectifier is widely used to achieve high power factor with regulated output voltage. This kind of structure however calls for complex circuitry and control [1]. Many other approaches have been sought for the realization of threephase power factor correction [1-3], although few have explored the case of feeding different loads per each input phase. This is required when multiple low power supplies are fed from a three-phase network, as in telecom applications for instance [4-5]; hence single-phase PFC converters may be used to feed the load instead of a single three-phase unit. A benefit of this approach is that the use of multiple singlephase PFCs provides modularity, redundancy, and simple scalability to higher power levels if desired. The modeling of single-phase PFC converters has primarily focused on the development of average models. Small-signal models for these converters have lagged behind given the time varying nature of their AC input voltage and current. Quasi-stationary small-signal models have been
This work was supported primarily by the ERC Program of the National Science Foundation under Award Number EEC-9731677.

proposed trying to capture the small linear behavior at different input line conditions; however with somewhat limited results [8]. In [9] a method to derive the small-signal model of a single phase PFC converter was presented, limited nonetheless to the high frequency range. This paper proposes an alternative approach to model single-phase PFC converters, consisting of grouping all single-phase PFC converters into an array representing a single three-phase load. This three-phase equivalent model may then be transformed into the synchronous d-q-0 frame, which basically converts ac-varying state variables into dc quantities. The resultant model is thus suitable for linearization and small-signal analysis throughout the complete frequency range (up to half of switching frequency). The paper presents the complete derivation of the threephase equivalent large signal average model for single-phase PFC converters loads, as well as the d-q-0 frame and smallsignal models. Key modeling issues are addressed, giving emphasis to their frequency response, commenting as well on previously developed models [6-9]. Finally, simulation results are used to verify the correctness of the model. II. THREE-PHASE ARRAY OF SINGLE -PHASE LOADS In many applications, multiple low power single-phase loads need to be fed from three-phase networks. In this case, the usage of single-phase boost-type PFC converters represents a good solution for feeding these multiple loads independently. Fig. 1 shows a three phase voltage source supplying different single-phase loads through a distribution transformer. Since modeling many single-phase PFC loads has many limitations and especially so for small-signal analysis, this papers proposes to model this array of PFCs as a single equivalent three-phase load as shown in Fig. 2. A standard transformation may then be used to convert all the abc variables into the d-q-0 synchronous frame. In this frame the model state variables become dc quantities and as

0-7803-9724-X/06/$20.00 2006 IEEE. IEEE. 0-7803-9725-8/06/$20.00 2006 83

Fig. 1. Three phase system with single-phase PFC loads

transformation to the d-q-0 frame cannot be performed in the frequency domain. A similar but large-signal model valid in the low frequency range is shown in [7]. This large signal model however is not suitable either for deriving the d-q-0 equivalent model due to the presence of a nonlinear power term in the model. This model is also limited in the sense that it can only predict the low frequency characteristics of boosttype PFC, usually ten times lower than the line frequency. In [9], the high frequency range of single-phase PFCs was modeled showing as well the input impedance characteristics, which is repeated here in Fig. 5. This reference also presents a good method to eliminate the diode rectifier in the largesignal model: change the current reference from rectified sinusoidal wave to sinusoidal wave. The model is also shown in Fig.6.

Fig. 2. Three phase system with single-phase PFC grouped

Fig. 4. Low frequency average model of single-phase PFC

Fig. 3. Three single-phase PFC

such operating points may be readily defined and extracted for the development of small-signal models. In Fig.3, a detailed circuit is also presented of the equivalent three-phase load comprised of single-phase PFC circuits. For the sake of simplicity, the distribution transformer is not considered since its only purpose is to enable the single-phase power distribution by providing a neutral for the loads return. Naturally this does not affect the actual modeling of the single-phase PFC converters. The next section presents a survey and evaluation of several single-phase PFC converters models, from where the most appropriate model will be chosen for its aggregation into a three-phase equivalent one. III. SINGLE -PHASE BOOST-TYPE PFC MODEL DEVELOPMENT Many papers have discussed various models of singlephase PFC converters, especially boost-type PFCs. In [6] a small-signal model of a single-phase PFC was proposed showing the low frequency negative incremental input impedance presented by these converters. This approach however is not applicable for multiple loads, since the

Fig. 5. Input impedance characteristics of PFC model from [8]

Fig. 6. High frequency average model of single-phase PFC

Fig. 7. Proposed average model for single-phase PFC

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The duty cycles d i ( i = a , b , c ) in these equations are actually the off-time duty cycle for dc-dc boost converters; however for simplicity and for equivalence with the threephase boost PFC converter this alternative definition is used instead. Before we can apply the frame transformation to the above equations, one important issue should be addressed. That is the transformation of the product of duty cycles and inductor currents, or the product of duty cycles and output voltages. In conventional three-phase PFC rectifiers, for the AC port modeling, the dc bus voltage is usually assumed a constant dc value. With this assumption the frame transformation is quite simple and direct. For the DC port, there is actually just one equation:
Fig. 8. Three single-phase PFC average model in ABC frame

d a iLa + d b iLb + d c iLc = Co

dvbus vbus + dt RL

(3)

Based on this model, we developed a large-signal model for PFC which will be used in deriving the d-q-0 model for the three signal-phase PFC rectifiers. This model is shown in Fig. 7, illustrating how the switch is replaced by a simple PWM switch model comprised of two controlled sources. This is based on the averaging technique proposed in [10]. The rectifier is then removed because both the input voltage applied and the input current produced is sinusoidal. The model described in Fig. 7 just applies the averaging method to remove the switching frequency ripple, so it is valid up to half of the switching frequency theoretically. Another benefit obtained by removing the diode rectifier is the overall simplification attained modeling-wise. The next section presents the derivation of the d-q-0 average model for three single-phase PFC converters based on this model.
IV.

The transformation is then applied only on the left side of this equation by replacing the three-phase variables by the product of the inverse transformation with their equivalent dq-0 frame variables. However, in the case of three singlephase PFC rectifiers this simplicity is not such since there are three independent dc voltages instead. These voltages are pulsating having a second harmonic component as shown in Fig. 9, which depicts the ratio between the second harmonic magnitude and the desired output voltage over the singlephase PFC power level. To analyze the DC ports park transformation, lets first write equation (2) in the following way.

d [vdc ]abc = diag{di }i =abc[i]abc diag 1 R [vdc ]abc (4) i i =abc dt

Then perform park transformation on both sides and get,

DEVELOPMENT OF THREE-PHASE EQUIVALENT SINGLE-PHASE

PFC CONVERTER MODEL

C [ ][vdc ]dq 0 + C

d [v dc ]dq 0 = T diag {d i }i =abc T 1 [i ]dq 0 dt

A. Full-Order Model

Fig. 8 presents the schematic of the equivalent three-phase model using single-phase PFC converters. If we assume a balanced resistor load case, as shown in Fig.8, then the following AC port and DC port equations can be written: AC port equations: d i La + d a v oa va = L dt d i Lb + d b v ob vb = L dt d i Lc + d c v oc vc = L dt DC port equations: dv oa v d a i La = C o + oa dt RL dv ob v d b i Lb = C o + ob dt RL dv oc v + oc d c i Lc = C o dt RL

T diag { 1 }i = abc T 1 [vdc ]dq 0 Ri

(5) Usually we will use the duty cycles in d-q-0 coordinate because those values are constant in steady-state, which gives us the operating point to linearize the large-signal model.

(1)

(2)

Fig. 9. Normalized second harmonic voltage magnitude

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Hence the diagonal duty cycles matrix is rewritten in the following form for convenience:
d a diag{d } = 0 0 0 db 0 0 d a 0 = d b dc dc 0 0 0 0 0 + d b 0 0 0 0 db 0 0 0 0 + 0 0 d c 0 0 0 dc 0 0

2 1 0 -1

Phase A inductor current

(6) Then we can apply the frame transformation to this equation which yields

[T ]diag {di }i = abc [T ]1

d d = dq d0

+ [0 0 1][T ] [d ]dq 0
1

0 0 0 0 0 1 1 1 1 0[T ]1 0 0 T 0 1 0 T d T [ ] [ ][ ] [ ] [ ] + dq 0 0 0 0 0 0 0 0 0 1 [T ] 0 0 0[T ] Df ([d ]dq 0 , [T ]) 1 0 1

-2 1.95 1.951 1.952 1.953 1.954 1.955 1.956 1.957 1.958 1.959 1.96

200 100 0 -100

Phase A input voltage

(7) Based on above analysis and derivation, we can finally obtain the d-q-0 average model for the dc port of the three single-phase PFC model as follows.

-200 1.95 1.951 1.952 1.953 1.954 1.955 1.956 1.957 1.958 1.959 1.96

C [ ][v dc ]dq 0 + C Df ([ 1 Ri

d [v dc ]dq 0 = Df ([ d ] dq 0 , [T ]) [i ]dq 0 dt
2

Fig. 11. One phase input voltage and inductor current

D-Q-0 inductor current

], [T ]) [v dc ]dq 0
id

(8) For the ac port we can use the same approach; the resultant equation is shown below.

0 -2 1.95 1.951 1.952 1.953 1.954 1.955 1.956 1.957 1.958 1.959 1.96

[vs ]dq0 = L d [i]dq0 + L[][i]dq0 + Df ([d ]dq0 ,[T ]) [vdc ]dq0 dt (9) K The model is shown in Fig. 10. Where, {D f idq 0 }dq 0 are G the components of the product Df ([d ]dq 0 , [T ]) iL .
After designing the controllers for each single-phase PFC converter closed-loop simulations could be run with the model in order to verify its accuracy. Fig. 11 shows the input voltage and current in one phase, Fig. 12 shows inductor current in the d-q-0 frame, and Fig. 13 shows the output voltage from start-up of one of the single-phase PFCs.

iq

0 -2

X: 1.955 Y: -1.509

1.95 1.951 1.952 1.953 1.954 1.955 1.956 1.957 1.958 1.959 1.96

i0

0 -2 1.95 1.951 1.952 1.953 1.954 1.955 1.956 1.957 1.958 1.959 1.96

Fig. 12. Inductor currents in DQ0 frame

Output voltage
500 450 400 401 350 300 250 200 150 399 100 50 0 398.5 398 1.955 1.956 1.957 1.958 1.959 400.5 400 399.5 402 401.5

0.5

1.5

Fig. 13. Output voltage of one single-phase PFC converter

From the above simulations, it is clear that the d-q-0 model is valid and can predict the time-domain behavior for the three single-phase PFC converters.
Fig. 10. Three single-phase PFC average models in DQ0 frame

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B. Reduced-Order Model

iq/vq -30 -40 -50 -60 -70 -80 -90 180 90 0 -90 -180 -2 10

If we observe again Fig. 9, it is clear that the second harmonic voltage magnitude is quite small comparing with the desired output voltage, 400 Volts. Even for the 30KW single phase PFC, the output second harmonic voltage is still less than 20%. Based on this observation, and assuming the three PFC converters feed balance single-phase loads, we can perform a simplification to the proposed model. In (9), instead of using the d-q-0 components of three phase output voltages, we can directly use the dc voltage, ignoring the second harmonics: (10) [vs ]dq0 = L d [i]dq0 + L[][i]dq0 + [d ]dq0 vdc dt In this case, the [T ]diag {d i }i = abc [T ] 1 will be reduced to [d ]dq 0 , saving a lot computations. The simplified model is shown in figure 14. Another argument for this simplification is that we are truly concerned about the low frequency characteristics of the output voltage, which due to the size of the output capacitor and load resistor possesses a reduced second order harmonic. This harmonic has therefore little influence on the model accuracy and may be readily neglected in the case of feeding a balance three-phase load.
V.

10

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Frequency (H z) a) Input admittance iq/vq

-30 M a g n itu d e ( d B ) Ph as e (deg) -40 -50 -60 -70 -80 -90 45

SMALL-SIGNAL ANALYSIS

An advantage of the proposed modeling approach for multiple single-phase PFC converters is the capability to transform the average model into the d-q-0 synchronous frame, where the model can be readily linearized for small signal analysis. This analysis is used primarily for controls design and for the study of possible interaction between converters and filtering stages [8][11]. For the small-signal input impedance, two normal ways may be used to obtain it, namely analytically or through simulations using appropriate design tools. In this paper, the second method is utilized using Matlab/Simulink linear analysis tool. Fig. 15 shows for instance the input admittance obtained.

-45 -90

-135 10
-1

10

10

10

10 (Hz)

10

10

10

b) Input admittance id/vd Fig. 15. Input admittance (Q-channel alignment)

Fig 14. Simplified Model

This figure shows that that the input admittance of the qchannel displays the negative incremental impedance characteristic since the calculation is aligned with the q-axis, i.e., the d-channel voltage is zero. This characteristic is present at very low frequency, where the voltage loop regulates, but then becomes a resistor once it loses effect and the only loop in action is the PFC current loop. Once this action fades the admittance resembles that of the inductor. The d-channel input admittance on the other side simply shows the current-loop action and the power stage components at higher frequencies. To illustrate this concept, the admittance is now obtained but using a d-channel alignment instead. It is quite clear that now the power transferring channel becomes the d-channel.

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Bode Diagram iq/vq -30 -40 Magnitude (dB) -50 -60 -70 -80 -90 45

The 0-channel input admittance is depicted in Fig.17, which has a similar characteristic to that of the d-channel (for q-axis alignment). VI. CONCLUSION This paper proposed an average model for a three-phase equivalent load composed of single-phase PFC converters. The advantage of this approach is that in d-q-0 coordinates all state variables become dc quantities and hence may be readily linearized in order to obtain the small-signal model of the PFC converters. Time domain simulations were presented to verify the correctness of this model, as well as the input admittance obtained through the linearization of the average model. The proposed model then effectively captured the small-signal behavior of PFC converters throughout the entire frequency range up to half the switching frequency. ACKNOWLEDGMENT The authors would like to thank The Boeing Company for the financial support of this research work.

0 Phase (deg)

-45 -90

-135 10
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Frequency (Hz)

a) Input admittance iq/vq

Bode Diagram -30 -40 Magnitude (dB) -50 -60 -70 -80 -90 180 90 Phase (deg)

id/vd

REFERENCES
[1] G. Spiazzi and F. C. Lee, Implementation of Single-Phase Boost Power Factor Circuits in Three-phase Applications, in Proc. VPEC94, pp. 189-194. [2] Y.K.E.Ho, S.Y.R. Hui and Y.S. Lee, Characterization of Single Stage 3 Phase Power Factor Correction Circuit Using Modular Single Phase PWM DC-to-DC Converters, IEEE 1999 [3] Jaehong Hahn, Prasad N. Enjeti, Ira J. Pitel, A New Three-Phase Power-Factor Correction (PFC) Scheme Using Two Single-Phase PFC Modules, Trans. On Industry Applications, VOL. 38, NO. 1, 2002 Jan/Feb [4] Sangsun Kim, and Prasad N.Enjeti, A Modular Single-Phase PowerFactor-Correction Scheme With a Harmonic Filtering Function, IEEE Trans. On Industrial Electronics, VOL. 50, No. 2, April. 2003 [5] Rich Bachik, Art Brockschmidt, Curtis Epperson, King Yuen, Practical Aspects of Line-line and Line-ground Single Phase PFC, IEEE 1999 [6] R. B. Ridley, Average Small-signal Analysis of The Boost Power Factor Correction Circuit, in Proc. VPEC94., pp. 79-91, 1994 [7] Aleksandar Prodic, Dragan Maksimovic, Stability of the Fast Voltage Control Loop in Power Factor Correctors, in Proc. IEEE PESC04 annual meet., pp. 2320-2325, 2004 [8] A. Uan-Zo-li, and F.C. Lee, Modeling, Analysis and Control of SingleStage Voltage Source PFC Converter, IEEE PESC05, pp.1408-1414, June 2005. [9] Jian Sun, Input Impedance Analysis of Single-Phase PFC Converters, IEEE 2003, pp. 361-368 [10] R. Tymerski, V. Vorperian, F.C..; Lee, and W. Baumann, Nonlinear Modelling of the PWM switch, IEEE PESC 1988, vol. 2, pp. 968-976, Apr. 1988. [11] R.D. Middlebrook, Input Filter Considerations in Design and Application of Switching Regulators, IEEE IAS76, pp. 366-382, 1976.

0 -90

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Frequency (Hz)

b) Input admittance id/vd Fig. 16. Input admittance (D-channel alignment)

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Fig. 17. 0-channel input admittance i0/v0

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