Sourcing and Sinking Currents

Dc input modules can either be sources or sinks for dc current. This depends on the the transistor used in the input card and the polarity of the dc supply Sinking

NPN sinking current to ground Sourcing equivalent circuit PNP switch sources current switch sinks load current

transistor sources current to load

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Sourcing And Sinking Currents

NPN transistors are open collector I-sinking devices Interfaces with sourcing input modules PNP transistors are open collector I-sourcing devices Interfaces with sinking input module
Sourcing sensor and sinking input module

sinking sensor with sourcing module note: polarity of dc supply

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Sourcing and Sinking Output Modules

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Relationship Between I/O Hardware and Memory

Field I/O device is considered load. Must provide sources of potential for I/O I/O points mapped to memory by PLC software Users must specifiy address when programming Determined by I/O hardware addressing

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PLC Data File Structures

Typical structure Allen-Bradley SLC500 Series Memory structure
System Memory Application memory

ROM holds PLC Operating system

RAM Holds user programs and data files I/O maps, programs battery back-up

File ID number

0 1 2 3 4 5 6 7 8 9

Output Image Input Image Status Bit Timer Counter Control Integer Reserved Network Comm. User defined

Bit, timer, counter, integer data defined by user

10-255
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AB SLC 500 Data File Identifiers File type Output status Input status Process status Bit file Timer Counter Control Integer Float-pt Interface File ID O I S B T C R N F File Number 0 1 2 3 4 5 6 7 8 9

File 0 - Output image single memory words

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

addr.

Address depends on slot location of the Output card and number of points
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Output Image File

15 x Invalid x Invalid x x 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 addr. O:2 O:5 O:6 O:7

PLC has an 16 ouput card in slot 2 a 8 output card in slot 5, a 16 output card in slot 6 and a 8 output card in slot 7 Each card assigned a word, unused bits are not addressable

File 1 - Input image single memory words

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 addr. I:0 I:3 I:4

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File 2 - Processor Status File

Contains information about how PLC and its operating systen is functioning Typical Information monitoring and clearing hardware and software faults setting of watchdog timer value runtime errors I/O errors average scan times

File 3 - The Bit File Bit files used to represent control relays that were used in electromechanical systems
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 addr. B3:0 1 0 B3:1 B3:2 B3:3

B3:1/9
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B3:2/8

Identifying individual bits

Timer File Structure and Addressing

File 4 - Timers. Each timer requires 3 words of data file Word 0 - control word I/O bits and Internal control Word 1 - preset value Word 2 - accumulated value
15 EN 14 TT 13 DN INTERNAL USE ONLY Preset Value (PRE) Accumulated Value (ACC) 0 0 1 2

EN - timer enabled bit TT - timer timing bit DN - timer done bit Data Structure is the same for on-delay and off-delay timers

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Addressing Timer File Data

15 EN 14 TT 13 DN INTERNAL USE ONLY Preset Value (PRE) Accumulated Value (ACC) 0 0 1 2

General form

Tf:e.s/b

bit

Examples

timer file # element default 4

sub-element

T4:0/15 = C5:0/EN

timer 0; timer enabled bit

T4:1.ACC or C5:1.2 accumulated value of counter T4:5/DN timer 5 done bit T4:5.ACC/1 bit one of accumulated value of timer 5 T4:2/TT timer timing bit for counter 2 T20:2.PRE preset of a timer defined in a user defined file area
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Counter File Structure

File 5 - Counters Each counter defined by three words in data file Word 0 - control word I/O bits and Internal control Word 1 - preset value Word 2 - accumulated value
15 CU 14 CD 13 DN OV UN UA INTERNAL USE ONLY 0 0 1 2

Preset Value (PRE) Accumulated Value (ACC)

CU - counter up enabled bit CD - counter down enabled bit DN - counter done bit OV - counter overflow bit UN - counter underflow bit UA - update accumulated value (only certain models) PRE - preset value ACC -acculumulated value
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Addressing Counter Data

15 CU 14 CD 13 DN OV UN UA INTERNAL USE ONLY 0 0 1 2

Preset Value (PRE) Accumulated Value (ACC)

General form

Cf:e.s/b

bit

file # default 5 Examples

element

sub-element

C5:0/15 = C5:0/CU

counter 0; count up bit

C5:1.ACC or C5:1.2 accumulated value of counter C5:5/DN counter 5 done bit C5:5.ACC/1 bit one of accumulated value of counter 5 C5:2/CD count down enable bit for counter 2 C20:2.PRE preset of a counter defined in a user defined file area
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Control File And Integer Files

File 6 -Control File Used to store status information for bit operations and stack control operations File 7 - Integer File Stores Integer data - one file location = one word range depends on data type (signed or unsigned)
9 8 45 129 7 6 5 4 3 2 1 0 addr. N7:0 N7:10 N7:20

N7:0/8

N7:10/7

File 8 - Float-point number data. numbers stored in scientific notation in memory locations similar to integer data. Only available on certain models

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Basic Concept of PLC Ladder Logic

PLC ladder logic based on logical continuity Symbols represent bits in data maps All input symbols must test true for the output symbol to be true

Boolean Equation ((1PB 2CR) + 3LS) 4CR 5CR = SOL A Could program PLC in verbose language or use ladder logic symbols. Ladder logic used to reduce training of maintenance personnel
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Basic PLC Programming Instructions

Bit or Relay Instructions

Examine if closed: XIC examines an input for closed condition

Examine if open: XIO examines an input for an open condtion

Logic of XIC
Input bit = 1 Evaluates TRUE pass logical continuity Evaluates FALSE block logical continuity

Input bit = 0

Logic of XIO
Input bit = 1 Evaluates FALSE block logical continuity Evaluates TRUE pass logical continuity

Input bit = 0
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Output Instructions
Output Energize (OTE) Instruction becomes true when all instructions to rung become true Output latch and Output unlatch Output latch become TRUE when input rung instructions become TRUE remains TRUE after rung becomes FALSE Ouput unlatch is used to reset the ouput latch instruction One Shot Instruction Input that allows an event to occur only once during a program scan Instruction only responds to rising hardware input signal

OSR

Responds to only FALSE to TRUE transitions

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Rung Examples
What is the condition of the output instruction (T/F) I:0 O:2

0 1746-IA8
15 14 13 12 11 10 9 8 7 6 5 4

1 1746-OB16
3 2 1 0

addr.

0 I:0 I:3 I:4

Input image table shows a 0 bit, so XIC evalues to a FALSE rung is FALSE so OTE is FALSE This gives 0 in output image
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 addr. O:0 0 O:2 O:4

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