Lab Exercise: Filter Design

Finite Impulse Response (FIR) filters are a typical DSP application requiring hardware implementation. Some of the issues that arise in the course of implementing such a system include designing the coefficients, quantizing and optimizing the number of bits required, implementing and simulating a HDL description, and finally synthesizing and testing it on hardware. In this lab, we will go through these steps. The software tools used here are not the only tools capable of being used here, but are fairly common. The process involves the following steps: Computing coefficients based on filter specifications Quantization of coefficients Verilog implementation and simulation Synthesis for FPGA target Testing on FPGA evaluation board

FIR Filter coefficients and Quantization

Design a low pass FIR filter with the following characteristics Unity gain in pass band At least 30 dB attenuation in stop band Pass band from 0 up to fs/8, transition band up to fs/4 The input fed to the filter will be quantized to 8 bits. We want to also quantize the filter coefficients to as few bits as possible so that the required attenuation is obtained. We will use Matlab to design the coefficients. Type the command matlab to start the Matlab interpreter. The rest of the commands can either be typed in directly to the interpreter, or collected in a script file that can be used. The procedure we will follow is: Use the firpm command to design the filter coefficients. Use fvtool to visualize the filter frequency response. b=firpm(20, [0 0.25 0.5 1], [1 1 0 0]) will try to design a filter with 21 taps, where the pass band gain (0 to 0.25 fs/2) is 1, and stop band (0.5 fs/2 to fs/2) is as close to 0 as possible (in practice it can never become exactly 0). Use the round command to quantize and check whether conditions are still satisfied. bq = round(b*2^(7))/2^8 will round the coefficients to 8 bits (ideally n n +1 should be mapped to 2 -1 instead of 2 , but we are making an approximation here). fvtool(bq) can be used to visualize the frequency response of the output plot(b) or plot(bq) can be used to see the impulse response of the FIR filter. As expected, it looks similar to a sinc function. Generate a test input consisting of the sum of two sine waves, one in the pass band, one in the stop band. Run this through the filter and plot the frequency response of the output to check whether suitable attenuation is seen. t = (1:1000)/1000; generates a time base for samples at the rate of 1000 samples per second, for one second. Note the ';' at the end of the command, otherwise Matlab will print out all 1000 samples on screen.

 x = 0.5*sin(2*pi*75*t)+0.5*sin(2*pi*300*t); will generate a sum of two sine waves, one in the pass band (75 Hz) and other in the stop band (300 Hz). The 0.5 amplitude is used so that the final sum is still in the range (-1, +1). xq = round(x*2^7)/2^8; will quantize to 8 bits. y = filter(bq, 1, xq); will compute the filtered output. plot(t, xq, t, y) can be used to visualize the input and filtered output It is possible to play around with the number of taps, number of bits etc. In practical VLSI design, we would like to optimize both of these as much as possible, so that the overall size of the result can be minimized. For this lab session we will move on to the next stage, implementation.

Verilog and Simulation

FIR filters require the following hardware components: registers, adders and multipliers. We will use the Verilog hardware description language in order to implement the filter. Adders and shift registers can be implemented directly using Verilog HDL constructs. For the multiplier, we will use radix-4 Booth encoded multipliers. The code for the Booth multiplier is given in Verilog format. It is implemented as an 8x8 multiplier that takes 2's complement numbers as inputs and generates a 16 bit 2's complement number as output. Using the Booth multiplier, the FIR filter can be implemented by using a simple direct form I implementation. No attempt has been made in this implementation to optimize for speed. The software used for Verilog simulation is Modelsim from Mentor graphics. The tool is started using the command vsim. The required verilog files need to be read in (create a new project), compiled, and then simulated. A test bench is provided for the filter that can read in data from a file, run it through the filter, and view the filtered output. Suitable inputs can be generated from Matlab by using the dec2bin command. An example input file has been provided (file name input.list).

Hardware Implementation
After the filter has been verified in simulation, it needs to be converted to hardware. We use the Xilinx ISE software for this. The command to start the tool is ise. A sample project has been provided that has all the files required for implementing on the FPGA eval board. The reason for the extra files is that the eval board we use in the lab uses serial ADC and DACs, so that some extra logic is required to collect the data and send out the data after filtering. The filter that was designed in the earlier section can be dropped into the project, provided that the input and outputs match what is used in the design (8 bit input, 8 bit output, 1 bit clock input). In this way, you can modify your filter in any way you want and plug it in to this design. The design must be first synthesized. This generates a synthesis report where you can identify certain important characteristics of the design. For example:

 Are any hardware multipliers inferred, or is the Booth multiplier implemented using logic only? How are the adders implemented in hardware? How many flip-flops are inferred? Does this match what you expect from the filter implementation? What is the maximum speed at which the system can operate? After synthesis, the design needs to be converted into a programming file (bit file) that can be downloaded to the FPGA. Once this is done, the filter is actually operational, and can be tested by feeding in suitable input and verifying the output. Note that the filter cutoff frequency depends on the sampling frequency that is used. Because of the serial nature of the ADC, the actual sampling rate is 50MHz/(64*4) = 195 kHz. Hence the passband and stopband frequencies are also determined with respect to this sampling frequency.

Summary
The purpose of this lab exercise was to go through all the steps involved in the hardware implementation of a simple DSP application (FIR filter). All the main steps, starting from the mathematical modeling and refinement, through HDL modeling and simulation, to synthesis and implementation on hardware evaluation board, have been followed. The exercise can be modified in several ways, such as trying different types of filters, different types of implementations, multiplier and hardware changes, pushing the implementation so that it is close to the speed limits of the hardware and so on.