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2013-1087 (Reexamination Nos. 95/001,108 & 95/001,154)

IN THE UNITED STATES COURT OF APPEALS FOR THE FEDERAL CIRCUIT ___________
RAMBUS, INC., Appellant, v. MICRON TECHNOLOGY, INC., Appellee. ___________ Appeal from the United States Patent and Trademark Office, Patent Trial and Appeal Board. ___________ REPLY BRIEF FOR APPELLANT RAMBUS INC. ___________ J. Michael Jakes James R. Barney Molly R. Silfen Aidan C. Skoyles FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER, LLP 901 New York Avenue, NW Washington, DC 20001 (202) 408-4000 July 22, 2013 Attorneys for Appellant Rambus Inc.

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TABLE OF CONTENTS I. II. Introduction......................................................................................................1 Argument .........................................................................................................3 A. The Board Is a Reviewing Body Whose Factual Determinations Must Be Supported by Substantial Evidence and Whose Ultimate Conclusion of Obviousness Is Reviewed De Novo ................................................................................3 The Examiners Undisputed Findings Negate the Boards Conclusion That the Claimed Operation Code Including Both a Write Instruction and Automatic Precharge Instruction Was Obvious in 1990 ..........................................................5 1. 2. 3. C. Microns Arguments Are Based on a Fundamental Misunderstanding of Wicklund and Bowater .............................5 The Unrebutted Record Evidence Does Not Support Obviousness Based on Bennett in View of Wicklund ..............11 The Unrebutted Record Evidence Does Not Support Obviousness Based on Bennett in View of Bowater ................16

B.

The Board Erred in Finding that Synchronous DRAMs Would Have Been Obvious in 1990 in View of Bennett ....................18 1. Micron Waived Its Untimely Construction of Synchronous Dynamic Random Access Memory Device Because It Never Challenged the Examiners Construction of that Term on Appeal .......................................18 The Boards Finding That Bennett Renders Synchronous DRAMs Obvious Is Unsupported by Substantial Evidence .................................................................22

2.

D. III.

Microns Alternative Ground for Invalidity Based on JEDEC and Park Contradicts this Courts Prior Decisions.................26

Conclusion .....................................................................................................31

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TABLE OF AUTHORITIES

Page(s) FEDERAL CASES Ariad Pharms., Inc. v. Eli Lilly & Co., 598 F.3d 1336 (Fed. Cir. 2010) (en banc) ..........................................................28 Assoc. of Data Processing Service Orgs., Inc. v. Board of Governors of the Federal Reserve System, 745 F.2d 677 (D.C. Cir. 1984) ..........................................................................3, 4 Brand v. Miller, 487 F.3d 862 (Fed. Cir. 2007) .............................................................................. 5 Celsis in Vitro, Inc. v. CellzDirect, Inc., 664 F.3d 922 (Fed. Cir. 2012) ............................................................................25 Conoco, Inc. v. Energy & Envtl. Int'l, L.C., 460 F.3d 1349 (Fed. Cir. 2006) ..........................................................................20 DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc., 567 F.3d 1314 (Fed. Cir. 2009) ..........................................................................18 Ex Parte Frye, 94 USPQ2d 1072 (BPAI 2010) ............................................................................3 Ex Parte Horito and Brown, 2012 WL 4842863 (BPAI Sep. 27, 2012) ............................................................ 4 Hynix Semiconductor Inc. v. Rambus Inc., 645 F.3d 1336 (Fed. Cir. 2011) ...................................................................28, 29 ICU Medical, Inc. v. Alaris Medical Systems, Inc., 558 F.3d 1368 (Fed. Cir 2009) .....................................................................29, 31 In re Berger, 279 F.3d 975 (Fed. Cir. 2002) ............................................................................20 In re Caveney, 761 F.2d 671 (Fed. Cir. 1985) .............................................................................. 4

ii

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In re Gartside, 203 F.3d 1305 (Fed. Cir. 2000) ............................................................................ 3 In re Gordon, 733 F.2d 900 (Fed. Cir. 1984) ............................................................................14 In re Jolley, 308 F.3d 1317 (Fed. Cir. 2002) ............................................................................5 In re Lee, 277 F.3d 1338 (Fed. Cir. 2002) ............................................................................4 In re Zurko, 258 F.3d 1379 (Fed. Cir. 2001) ............................................................................4 LizardTech, Inc. v. Earth Resource Mapping, Inc., 424 F.3d 1336 (Fed. Cir. 2005) ..........................................................................29 Nelson v. Adams USA, Inc., 529 U.S. 460 (2000) ............................................................................................22 Powell v. Home Depot U.S.A., Inc., 663 F.3d 1221 (Fed. Cir. 2011) ..........................................................................15 Rambus Inc. v. Infineon Techs. AG, 318 F.3d 1081 (Fed. Cir. 2003) ....................................................................28, 29 Rambus, Inc. v. Micron Technology, Inc., Appeal No. 2013-1228 (Fed. Cir.) ......................................................................27 Rambus Inc. v. Rea, No. 2012-1480, slip. op. (Fed. Cir., June 28, 2013) .......................................6, 11 Sage Prods., Inc. v. Devon Indus., Inc., 126 F.3d 1420 (Fed. Cir. 1997) ............................................................................ 4 Tec Air, Inc. v. Denso Mfg. Michigan Inc., 192 F.3d 1353 (Fed. Cir. 1999) ..........................................................................16 Unigene Labs., Inc. v. Apotex, Inc., 655 F.3d 1352 (Fed. Cir. 2011), cert. denied, 132 S.Ct. 1755 (2012) ............... 25

iii

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Yee v. City of Escondido, Cal., 503 U.S. 519 (1992) ............................................................................................15 FEDERAL STATUTES 35 U.S.C. 315(b) (2002) .......................................................................................27

iv

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I.

INTRODUCTION Micron has failed to demonstrate that substantial evidence supports the

Boards rejection of claim 34. Instead, much of Microns responsive brief is either factually wrong, legally irrelevant, or both. For example, Micron repeatedly

argues that Bowater and Wicklund disclose automatic precharge, as per the claim-at-issue. (Micron Br. 9-11, 23, 24, 45-47.) But this is incorrect, as Micron tacitly concedes by citing only to the 037 patent rather than Wicklund or Bowater for this proposition. (See, e.g., Micron Br. 9.) In fact, Wicklund and Bowater use conventional asynchronous DRAM signaling, which, as the examiner found, is incompatible with the claimed automatic precharge feature. (A1513 (Wicklund precharges prior to the writing of data that is at a new address and not automatically after data is written.) (emphasis added).) Micron further contends that Rambus does not dispute that the single chip memory device in Bennett is connected to a synchronous Versatile Bus. (Micron Br. 14, citing Rambus Br. 34.) This, too, is incorrect. As explained in Rambuss principal brief, Bennett does not disclose a single chip memory (Rambus Br. 58), and it certainly does not disclose a single-chip DRAM connected directly to a synchronous bus (id. at 34-35; 56-60). Indeed, Microns own expert in a prior litigation admitted that Bennetts large memory would have been composed of multiple chips. (A1686 (emphasis added).) And Samsung similarly conceded 1

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that Bennetts large memory would be comprised of DRAM chips. (A1842 (emphasis added).) Tellingly, Microns brief is silent about these admissions. In the same vein, Micron spends much of its brief rebutting straw men. For instance, Micron contends that a repeated flaw in Rambuss brief is the assertion that each limitation must be disclosed by a single prior art reference in order to constitute . . . obviousness. (Micron Br. 32.) Of course, Rambus never made any such argument. What Rambus actually arguedand what Micron fails to

addressis that the examiners finding of nonobviousness was based on the noted deficienc[ies] of Wicklund and Bowater themselves, such that even combining them with Bennett would not yield a prima facie case of obviousness. (Rambus Br. 30-31; 47-48.) Another straw man that Micron attacks is the alleged Rambus assertion that the Board is bound by [the examiners] findings. (Micron Br. 36.) What Rambus actually argued, however, is that because the Board did not find error with the examiners findings, those findings remain part of the undisputed record and the Boards conclusion of obviousness therefore lacks substantial evidence. As an alternative ground for affirmance, Micron argues that the Board should have found that the 037 patent was not entitled to its priority date and that JEDEC and Park therefore render claim 34 invalid. Micron, however, is not entitled to raise this argument because it was not part of its reexamination request. 2

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Moreover, the examiner and the Board properly found that the 037 patent is entitled to its priority date. II. ARGUMENT A. The Board Is a Reviewing Body Whose Factual Determinations Must Be Supported by Substantial Evidence and Whose Ultimate Conclusion of Obviousness Is Reviewed De Novo

The examiners factual findings form part of the record, and contrary to Microns assertions (Micron Br. 35-36, 38-39, 47) the Board may not simply disregard them when they prove inconvenient. See In re Gartside, 203 F.3d 1305, 1312-14 (Fed. Cir. 2000) (Court must examine the record as a whole, taking into account evidence that both justifies and detracts from the Boards decision) (emphases added). In asserting otherwise, Micron relies on a Board decision that itself refers to its review of the examiners findings and conclusions. (Micron Br. 34-35 (quoting Ex Parte Frye, 94 USPQ2d 1072, 1077 (BPAI 2010)).) Thus, regardless of the standard of review the Board uses when reviewing the examiner, the Boards decision must be supported by substantial evidence in the closed record, which includes the evidence presented by the parties and the examiners findings. Gartside, 203 F.3d at 1315 ([S]ubstantial evidence [must] be found within the record of closed-record proceedings to which it exclusively applies. (quoting Assoc. of Data Processing Service Orgs., Inc. v. Board of Governors of the Federal Reserve System, 745 F.2d 677, 684 (D.C. Cir. 1984)). 3

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Micron contends, incorrectly, that the Board reviews de novo the examiners determinations, i.e., without deference. (Micron Br. 47; see also id. 34-35, citing Ex parte Frye, 94 USPQ2d at 1077 and a USPTO blog entry). To the contrary, [t]he Board reviews facts found by the Examiner to determine whether those facts are supported by a preponderance of the evidence. Ex Parte Horito and Brown, 2012 WL 4842863 *2 (BPAI Sep. 27, 2012) (citing In re Caveney, 761 F.2d 671, 674 (Fed. Cir. 1985)). A preponderance-of-the-evidence review is not the same as a de novo review. Regardless, the Boards review cannot simply dismiss the examiners findings, as Micron erroneously asserts. Sage Prods., Inc. v. Devon Indus., Inc., 126 F.3d 1420, 1426 (Fed. Cir. 1997) (No matter how independent an appellate courts review of an issue may be, it is still no more than thata review.). Even though, as Micron states (Micron Br. 36), the Board may issue a new rejection based on its own factual findings, that is different from ignoring existing findings of the examiner. As this Court has explained, the Board must set forth its findings and the grounds thereof, as supported by the agency record, and explain its application of the law to the found facts. In re Lee, 277 F.3d 1338, 1342 (Fed. Cir. 2002); see also In re Zurko, 258 F.3d 1379, 1385-86 (Fed. Cir. 2001) (explaining that, with respect to core factual findings, Board cannot simply reach conclusions based on its own understanding or experience); Brand v. Miller, 487 4

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F.3d 862, 869 (Fed. Cir. 2007) ([I]n the context of a contested case, it is impermissible for the Board to base its factual findings on its expertise, rather than on evidence in the record, although the Boards expertise appropriately plays a role in interpreting record evidence.). B. The Examiners Undisputed Findings Negate the Boards Conclusion That the Claimed Operation Code Including Both a Write Instruction and Automatic Precharge Instruction Was Obvious in 1990

Micron contends this is merely a situation where the evidence in the record will support several reasonable but contradictory conclusions. (Micron Br. 34, citing In re Jolley, 308 F.3d 1317, 1320 (Fed. Cir. 2002).) But as Rambus

explained in its opening brief, this is not such a situation because the examiners specific findingswhich remain unrebutted by the Boardcan only support nonobviousness. The references, taken in combination, fail to teach or enable a

synchronous DRAM device, let alone one that can accept and respond to a write command that also includes an automatic precharge instruction. There is no

reasonable conclusion of obviousness for claim 34 that can be drawn from the present record. 1. Microns Arguments Are Based on a Fundamental Misunderstanding of Wicklund and Bowater

Microns argument that an operation code containing both a write instruction and an automatic precharge instruction would have been obvious in 1990 (Micron

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Br. 26) is based on a faulty understanding of the prior art. As Rambus explained in its opening brief, in prior-art asynchronous DRAMs, such as those used by Wicklund and Bowater, read and write operations were based directly on the transition timing of control signals from a memory controller. (Rambus Br. 7, 4445; see also Rambus Inc. v. Rea, No. 2012-1480, slip. op. at 3 (Fed. Cir., June 28, 2013) (discussing asynchronous DRAMs).) In these systems, the memory

controller uses transitions on one signal line (Row Address Strobe or RAS) to open and close rows in the DRAM, and transitions on another signal line (Column Address Strobe or CAS) to control column access operations (i.e., read and write) in an open row. Annotated Figure 2 from Bowater illustrates this process:

Open Row

Read COL 0

Read COL 1

Close Row, Precharge

(A1450 (annotated).) Figure 2 shows row and column control inputs for two banks of DRAM devices A and B (both banks operate similarly, so it suffices to look only at bank 6

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A). At transition 41, the controller transitions RAS A low, causing a row at address ROW to be opened. After allowing enough time for the sense amplifiers to sense the row data, the controller transitions CAS A low, causing a read at address COL 0 of ROW and data 0 to be output onto the DATA lines. The controller then transitions CAS A high, causing data 0 to no longer be driven onto the DATA lines. The controller later transitions CAS A low again, causing a second read at address COL 1 of ROW and data 2 to be output. The controller then transitions CAS A high, causing data 2 to no longer be driven onto the DATA lines. Finallyand only after the column accesses for the open row are completethe controller transitions RAS A high, closing ROW and precharging the sense amplifiers. Notably, the controller in a prior-art, asynchronous system must hold RAS low throughout the entire time that column operations are performed, or else the DRAM will precharge its sense amplifiers prematurely and the column operations will not be performed correctly. Thus, because a read or write operation requires that RAS be held low so that the accessed row remains open throughout, it would be impossible to also simultaneously signal a precharge operation (which closes the row immediately) by driving RAS high. In other words, asynchronous DRAM devices like those used by Wicklund and Bowater require that the controller hold RAS low and that no precharge signaling be initiated until after any current 7

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column operations are completed. Neither Wicklund nor Bowater discloses any modification to this conventional asynchronous signaling scheme, which renders the concept of signaling a write with autoprecharge impossible. The memory device recited in claim 34 of the 037 patent operates differently from the prior art. As Rambus explained, the 037 inventors freed up the bus by abandoning the prior-art asynchronous system and instead utilizing an operation code that preschedules a read/write operation and subsequent precharge at the same time. (Rambus Br. 7-8, 15-17.) Thus, as soon as the operation code is sent, the DRAM already knows whether or not to perform an automatic precharge after the read/write operation, without the need for a separately timed controller signal as was required in the prior art. (A83-84[10:4611:53]; see A1602-03[25] (Mr. Murphy explaining that claimed operation code with auto-precharge helps free up control bandwidth, whereas a dedicated precharge command consumes additional bandwidth).) Because of the wholly different system of asynchronous prior-art DRAMs, an operation code that contains a write instruction and a precharge instruction did not exist; rather, the bus was tied up with a dont-precharge RAS signal throughout a DRAM write operation. Microns argument that an operation code containing both a write instruction and a precharge instruction would have been obvious based on the teachings of Wicklund and Bowater (Micron Br. 26) is therefore based on a faulty 8

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premise. Neither reference proposes or suggests any capability for signaling a precharge to a DRAM prior to the actual time that the precharge is desired. Micron is also incorrect that the normal mode and page mode disclosed in Wicklund operate the exact same way as the typical settings for precharge described in the 037 patent. (Micron Br. 9-10.) While Wicklund and the 037 patent both allow a controller to select a normal mode or a page mode of operation (see Micron Br. 18, 23, 29, 41-42), the 037 invention requires only one short bus access to schedule both a write and a subsequent precharge. In contrast, Wicklund requires the bus to be tied up with a hold-the-row-open (RAS held low) signal for the entire write process and thus requires three temporally separate controller signalsa write signal (CAS taken low while RAS held low), a write-data-ready signal (CAS taken high while RAS still held low), and finally a precharge signal (RAS taken high). (See Micron Br. 37 (conceding that Wicklund alone does not disclose claim 34).) The same is true for Bowater. (A1450 (Bowater showing typical prior-art RAS/CAS system with precharge signaled by controller transition of RAS); see also Micron Br. 38.) Moreover, only in the 037 patent does the memory device know in advance, i.e., when the write request is initially received, whether precharging will be required after the operation, and only in the 037 patent is control of precharge timing transferred from controller to DRAM in advance, via the write/precharge command. In both Wicklund and Bowater, the 9

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precharge timing determination is instead made by the controller independently of the signal transitions controlling a write, and any subsequent DRAM precharging can only be accomplished with a separate controller signal. In the context of a high-speed memory device, these are not minor differences. Micron is also wrong when it asserts that, in Wicklund, a normal mode operation is followed by an automatic precharge operation. (Micron Br. 9 (citing A83[10:47-50].) This is simply incorrect, as the examiner explicitly found.

(A1513 (Wicklund precharges prior to the writing of data that is at a new address and not automatically after data is written.) (emphasis added).) In Wicklund, precharging does not automatically follow any read or write operation. (Id.) Instead, after each memory operation is completed, a prediction is made by the controller as to whether the next memory transaction will be in normal mode or page mode. (A1444[4:4-21].) Only then, if it is determined that the next access will likely be in normal mode, will the controller signal the DRAM to take RAS high, resulting in a precharge. (Id.) Otherwise, the system will remain in page mode (with the controller continuing to hold RAS low) and the DRAM will accordingly not precharge its sense amplifiers. Tellingly, on this particular point, Micron does not cite to anything in Wicklund but, instead, cites only to the 037 patent. (Micron Br. at 9, citing A83[10:47-50].)

10

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2.

The Unrebutted Record Evidence Does Not Support Obviousness Based on Bennett in View of Wicklund

Regarding Wicklund, the examiner fully considered that the Wicklund controller precharges the DRAM some time after writing in the normal mode, but this is only in preparation for RAS being driven high in advance of a new read or write operation, and only in response to a separate prediction algorithm specifying that the next access should be in normal mode, not something that is commanded to occur automatically in the DRAM following a current write request, as in claim 34. (A1498; A1513.) As Wicklund explains: The most practical method would be to automatically turn page mode on or off based on a prediction of whether or not the next access will be at the same DRAM row address as the last one. If the prediction is correct, the memory access will require less time than if the prediction is incorrect . . . . One of the most useful methods of predicting page mode hits is to assume that future performance will closely match the past performance. Therefore, the controller will monitor some past period of time and measure the page hit/miss ratio and use that to predict whether or not to expect the next access to be a hit or a miss. (A1444[4:4-21].) Thus, when a controller initiates a write signal in Wicklund, neither the memory device nor the memory controller knows at that time whether precharging will be necessary at the end of the write operation (in fact, in the Wicklund asynchronous system, there is no physical way for the controller to signal a precharge early to a DRAM, as explained above). That determination 11

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depends, instead, on the result of a prediction algorithm in the controller that does not come into play until after the write operation is completed. Thus, as the examiner correctly found, at best, Wicklund discloses that precharging occurs some time after the writing of data, however this does not disclose automatically precharging after writing data and wherein this precharging instruction came within the same operation code as the specifying of the sampling of the data to be written. (A1498.) The Board did not rebut this specific finding but instead accused the examiner of failing to consider that the controller signals a precharge on the DRAMs after writing in the normal mode and that the controller signals a precharge after shifting from the page mode to the normal mode and writing to a new row pursuant to the shift. (A32-33.) But, as explained in Rambuss opening brief (and as Micron does not dispute), the examiner did fully consider these facts and nevertheless concluded that this does not satisfy or render obvious the claimed precharge requirement. (Rambus Br. 45-46.) Indeed, the sentence from the

examiner quoted above shows that the examiner considered precisely these facts. Alternatively, the Board reasoned (and Micron argues on appeal) that Wicklund also teaches that if a DRAM is in page mode for too long, as determined by a counter, it must be closed and refreshed (i.e., precharged). (A31; Micron Br. at 29-30.) Yet the examiner duly considered the use of page-mode 12

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counters in the prior art and concluded that they teach away from the claimed operation code including both a write instruction and an automatic precharge instruction. As the examiner correctly found, referring to the page-mode counter in Bowater, this [precharge] indication is based on a counter and there is no support for including this information along with write request since that would defeat the purpose of the essential counter. (A1501 (emphasis added).) Neither the Board nor Micron in this appeal has rebutted this specific finding by the examiner that page-mode counters, like those in Bowater and Wicklund, teach away from the claimed invention. In re Gordon, 733 F.2d 900, 902 (Fed. Cir. 1984) (finding no suggestion to modify a prior art device where the modification would render the device inoperable for its intended purpose). Moreover, as Rambus explained, there are other reasons one of ordinary skill would not have combined a write instruction and a precharge instruction into one operation code, even in light of Bennetts teachings.1 (Rambus Br. 54-55.) For

Contrary to Microns assertion, Bennetts read-modify-write instruction is not a multi-function operation code. (Rambus Br. 27; A1590-91.) Regardless, Mr. Murphys unrebutted expert testimony (A1629[ 105]) and the examiners unrebutted teaching-away finding (A1501-01) preclude a prima facie case of obviousness. Moreover, whereas Micron claims it raised Bennetts read-modifywrite instruction in its appeal briefing (Micron Br. 25 (citing A10375)), it did so only in its reply brief, in a parenthetical, and only to point out that Bennett generally discloses operation codes, not to argue that Bennetts read-modify-write request comprises multiple functions. 13

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instance, as Mr. Murphy explained in an unrebutted declaration, 2 those two requests would have been generated from different sources in Bennett and would have been generated at different times. (A1629[ 105].) Micron provides no evidence to contradict this point but instead claims Rambus waived the argument because it allegedly never relied on this paragraph ( 105) during its appeal to the Board. (Micron Br. 43.) Micron is mistaken. Rambus specifically relied on paragraph 105 of Mr. Murphys declaration on page 14 of its appeal brief. (A1590 (citing Murphy Decl. at 90-105 and Id. at 105-106).) Moreover, Rambus made this specific argument to the Board in its appeal brief (A1594), during oral argument (A1022), and in its petition for rehearing (A4109-10), and it relied extensively on Mr. Murphys declaration throughout. Accordingly, waiver is not applicable. See Yee v. City of Escondido, Cal., 503 U.S. 519, 534-35 (1992); Powell v. Home Depot U.S.A., Inc., 663 F.3d 1221, 1230-31 (Fed. Cir. 2011). Microns fallback response to Mr. Murphys point is that Bennett allegedly discloses a Versatile Bus Interface and memory on the same chip, such that the two instructions allegedly would have been generated from the same source, e.g., a processor. (Micron Br. 43-45.) This argument, however, is based on Microns conflation, discussed infra, II.C, of DRAM memory chips and VLSICs. Bennett only discloses attaching one kind of chip, a VLSIC, directly to its primary bus, and
2

Micron submitted no expert testimony in this reexamination. 14

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that chip does not necessarily include memory at alland certainly not DRAM. (Micron Br. 44 (citing A1350[101:50-54] (simply showing Bennetts use of a synchronous bus connected to its Users, but none of those Users is a DRAM or even a memory chip)); A1628[100, 102].) Micron relies on a sentence in Bennett that suggests that Bennett is versatile enough to handle even a trivial passing of a single bit of data between two unspecified master and slave devices. (Micron Br. 44, 50 (citing A1307[15:4253] and A1328(57:54-59).)) As Microns own expert in a prior litigation

conceded, however, to the extent Bennetts slave memory comprised DRAM, it would have taken the form of a memory card containing multiple DRAM chips and a memory controller. (A1686; see also A1633[116] (Mr. Murphy explaining same).) Such a memory card could, indeed, handle a trivial passing of a single bit of data, but that does mean it would be anything other than the known, prior-art DRAM array configuration, containing multiple chips. There is absolutely no expert testimony in the record, nor any findings by the examiner, to support Microns argument that its imagined integrated DRAM chip was disclosed by Bennett, let alone that such a device would inherently receive both write instructions and precharge instructions across a Versatile Bus in a single operation code. In contrast, there is unrebutted expert testimony in the record to support Rambuss position. (A1629[105].) 15

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3.

The Unrebutted Record Evidence Does Not Support Obviousness Based on Bennett in View of Bowater

Regarding Bowater, the examiner found that Bowater teaches away from the claimed invention, i.e., that combining it with Bennett in the proposed manner would render the essential timer feature of Bowater inoperable. (A1501-02.) This finding was never rebutted by the Board, nor does Micron address it on appeal. With this unrebutted finding as part of the closed record, there simply cannot be substantial evidence to support obviousness based on the combination of Bennett and Bowater. Tec Air, Inc. v. Denso Mfg. Michigan Inc., 192 F.3d 1353, 1360 (Fed. Cir. 1999) (There is no suggestion to combine . . . if a reference teaches away from its combination with another source.). While steadfastly ignoring the examiners teaching-away finding, Micron asserts it would have been obvious based on Bowaters page-mode timer to combine an automatic precharge instruction and a write instruction into a single operation code in Bennett. 3 But as the examiner correctly found (and the Board ignored), the precharge instruction in this proposed combination would defeat the very purpose of Bowaters counter because the counter could then be overridden

Indeed, Micron goes so far as to assert that Bowaters counter is the same as the time period embodiment for precharge described in the 037 Patent. (Micron Br. 11 (citing only the 037 patent at A83[10:50-55].) Of course, this is simply a red herring because the so-called time period embodiment is not what is claimed in claim 34. 16

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by the operation code. (A1502 (examiner explaining that [i]f Bowater provides precharge information that will automatically precharge after writing data, Bowater would not be able to change the time since the instruction would have already been sent).) In other words, if the operation code controls precharging, then the

counter feature (which ensures that the controller generates a refresh after a certain number of consecutive page-mode operations) is either lost, or there still must be a counter somewhere in the modified system, in which case, what motivation is there in Bowater to create the claimed operation code in the first place? Put differently, the page-mode counter of Bowater cannot be the motivation to create the claimed operation code because the claimed operation code does not perform the function of Bowaters counter. DePuy Spine, Inc. v. Medtronic

Sofamor Danek, Inc., 567 F.3d 1314, 1326 (Fed. Cir. 2009) (An inference of nonobviousness is especially strong where the prior arts teachings undermine the very reason being proffered as to why a person of ordinary skill would have combined the known elements.). Micron also contends, erroneously, that in Bowater, information is received as part of the memory request which sets a counter to automatically trigger the sense amplifiers to store the data back into the array and precharge. (Micron Br. 11 (emphasis added), citing A1462[7:62-65]; A1457.) This is simply false, as Bowater does not teach modifying the conventional DRAM or DRAM interface in 17

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any way. As such, Bowater does not disclose or even suggest a memory request that contains information . . . which sets a counter or any precharge information. Instead, Bowater employs the same RAS/CAS transition-based signaling as described above, whereby a write operation is triggered by a voltage transition on the CAS line. (See A1462[8:14-20] (describing the content of control signals 304).) This CAS transition does not carry any additional information, such as an instruction to set a counter. Moreover, as the examiner correctly found (and the Board failed to rebut), the use of a page-mode-counter on a controller is entirely different from the claimed operation code containing both a write request and an automatic precharge instruction, and, indeed, the page-mode-counter concept teaches away from the claimed invention. (A1501-02.) C. The Board Erred in Finding that Synchronous DRAMs Would Have Been Obvious in 1990 in View of Bennett 1. Micron Waived Its Untimely Construction of Synchronous Dynamic Random Access Memory Device Because It Never Challenged the Examiners Construction of that Term on Appeal

Micron newly asserts that the examiner erred in his claim construction of synchronous dynamic random access memory device (synchronous DRAM device). (See Micron Br. 13-14 (Micron arguing that synchronous DRAM device can be a composite device that has multiple DRAMs).) Micron waived

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this claim-construction argument, however, because it never raised it on appeal to the Board. Specifically, the examiner construed synchronous DRAM device to mean a synchronous DRAM chip, hence requiring the memory to be on a single integrated memory chip. (A1480 (emphases added).) In doing so, the examiner specifically rejected the very argument Micron is now making, i.e., that a synchronous DRAM device can be a collection of DRAM chips connected to a memory controller, as would be encompassed by this Courts construction of the broader term synchronous memory device: The Examiner disagrees with the Requester and his previous position. First while [t]he Examiner agrees that synchronous does not insert a single chip requirement, the term DRAM does since a DRAM has only been shown within the prior art and the 037 patent specification as a single memory chip. While the Examiner notes that the term memory device is not bound to a single-chip, the Examiner notes that the term DRAM in itself entails a single-chip construction. (A1481 (emphases in original).) On appeal to the Board, Micron could have challenged the examiners construction of synchronous DRAM device but chose not to. Instead, Micron framed all of its Bennett arguments around the examiners construction, arguing to the Board that Bennett discloses a memory chip having a synchronous interface. (A1740 (emphasis added).) In considering these arguments, the Board implicitly 19

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applied the same construction as the examiner, requiring a synchronous DRAM chip. (A29.) Having never challenged the examiners construction on appeal to the Board, Micron cannot belatedly challenge it now. In re Berger, 279 F.3d 975, 984 (Fed. Cir. 2002) (finding waiver where applicant presented argument to the examiner but not the Board); Conoco, Inc. v. Energy & Envtl. Int'l, L.C., 460 F.3d 1349, 1358-59 (Fed. Cir. 2006) ([A] party may not introduce new claim construction arguments on appeal or alter the scope of the claim construction positions it took below.). Moreover, the record fully supports the examiners construction of synchronous DRAM device. Specifically, the examiner relied on the

specification and prior arts consistent use of DRAM memory as referring to a DRAM memory chip. (A1480 (emphasis in original).) The examiner cited a portion of the specification that describes the DRAM chips of a memory system. (A1481 (citing A80[3:46-49]).) The specification also uses DRAM and chip interchangeably. (A80[4:25-33]; see also A1480 (quoting A80[4:30-33], which describes the internals of prior art DRAM devices).) Thus, unlike synchronous memory device, which under this Courts construction can consist of multiple chips, a synchronous DRAM device is required by the specification to be a single chip. (See Rambus Br. 9-10.) 20

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Micron asserts that Rambus has also raised a new argumentnamely that it was unknown in the art to operate the secondary bus (the bus between the memory controller and the DRAM chips) synchronously. (Micron Br. 13 n.2.) Yet this is hardly a new argument. During the proceedings before the examiner, the parties disputed the construction of synchronous DRAM device precisely because, in prior-art DRAM arrays, even if the primary bus included a clock, the individual DRAM chips themselves were still controlled asynchronously because there was no clock signal on the secondary bus. (See, e.g., A1586-88; A1612-16[54-63].) Indeed, a major thrust of Rambuss argument to the examiner and the Board was that a prior-art, single-chip DRAM could not meet the synchronous DRAM device limitation because it would not receive a clock signal. (See, e.g., A1558 (arguing that Bennetts memory cards contained a collection of asynchronous memory devices . . .) (emphasis added); A1610-11[ 48, 50].) Accordingly, there is no waiver. See Nelson v. Adams USA, Inc., 529 U.S. 460, 469-70 (2000) (explaining that waiver principle does not demand the incantation of particular words; rather, it requires that the lower court be fairly put on notice as to the substance of the issue).

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2.

The Boards Finding That Bennett Renders Synchronous DRAMs Obvious Is Unsupported by Substantial Evidence

As Rambus explained in its opening brief, no prior-art reference discloses the claimed synchronous DRAM device. In an apparent attempt to rebut this fact, Micron cites an Intel reference and baldly asserts (via attorney argument) that synchronous DRAMs were known at least as early as 1972. (Micron Br. 15.) Yet, tellingly, Micron never relied on that reference as part of any proposed rejection in the reexamination. Indeed, the Intel reference does not disclose the claimed synchronous DRAM, let alone synchronous DRAM with the autoprecharge features recited in claim 34. (See A10349 (not showing how any clock signal is used to interleave requests); A10351-52 (not showing how precharge would be accomplished).) Micron also asserts that Rambus mischaracterized Bennett as being unconcerned with interconnecting memory devices and as disclosing only a mainframe computer. (Micron Br. 4.) But Rambus never stated that Bennett is unconcerned with interconnecting memory devices. Rather, Rambus explained that any large memory used in Bennett in 1990 would have necessarily comprised a multi-chip memory card. (Rambus Br. 57.) And it is abundantly clear that Bennett is primarily concerned with mainframe computer systems. (See, e.g., A1305[11:36-50] (discussing as an example using a one meter bus, thus 22

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describing a very large computer); A1306[13:50-67] (preferred embodiment includes 20 devices and up to one meter of bus); A1302[6:41-47] (explaining that VLSI may involve development costs of up to ten times what implementation of the same function would cost on PC cards and that it is desirable to amortize these costs over several production units, implying that only several production units would be built); A1045 (showing that Bennett is assigned to Sperry Corporation, a company that dealt with mainframe computers).) In any event, Bennett does not disclose DRAM at all, which Micron does not dispute. Rather, Micron only asserted below that Bennetts large memory would have rendered DRAM obvious. As Rambus explained, however, and as Microns own expert in a prior litigation conceded (Rambus Br. 57-58), Bennetts large memory, if it could be DRAM at all, would necessarily have been a multichip memory card in which the DRAMs operated asynchronously. Micron now conflates Bennetts large memory with Bennetts separate VLSICs, arguing that because a VLSIC is a chip connected directly to a bus, Bennett allegedly renders obvious a synchronous DRAM chip connected directly to a primary bus. (Micron Br. 4-6, 14-15, 16 (asserting that Bennett discloses the Versatile Bus Interface and the User Memory are part of a single integrated chip but citing only references to VLSICs, not memory), 27 (making similar statement, but citing only Board opinion (A26-27[B1]), which cites only points that were addressed at Rambus Br. 23

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58 and unrebutted by Micron), Micron Br. 50-51 (same, and incorrectly stating that it is undisputed that the single chip containing the Versatile Bus Interface and the memory in Bennett received a synchronous signal).) But, in asserting that

DRAMs were ubiquitous in 1990 and that Bennett disclosed synchronous chips (albeit not necessarily memory (see Rambus Br. 58)), Micron proves Rambuss point; namely, if it were so obvious to create a synchronous DRAM, someone would have made such a device from known parts before 1990. This is different from a situation in which different references each show different limitations of a claim. (See Micron Br. 48.) Here, a single limitation, synchronous DRAM, is not shown in any reference. The situation in Celsis in Vitro, Inc. v. CellzDirect, Inc., 664 F.3d 922, 92728 (Fed. Cir. 2012) is instructive. There, this Court addressed whether the claim limitation multi-cryopreservation would have been obvious. The district court had acknowledged a vast proliferation of authors and articles dealing with . . . cryopreservation. Id. at 927. And this Court recognized that the art was a crowded field and that it would have been known to try to freeze cells multiple times. Id. at 928. But because one would have expected multiple rounds of freezing to damage more cells than a single freezing, the Court agreed with the district court that there was no teaching in the relied-upon prior-art reference that multiple rounds of freezing would improve results. Id. Similarly, here, although 24

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it was known to use a clocked bus for other purposes and DRAMs were common, the idea of a synchronous DRAM was counterintuitive because it added complexity and slowed down each individual transaction. A1642[9-10].) (Rambus Br. 7;

Thus, the single limitation, a synchronous DRAM, is not

rendered obvious by showing that the noun (DRAM, like cryopreservation) and the modifier (synchronous, like multi-) both existed in the prior art, since they were not believed to be useful together. Id.; see also Unigene Labs., Inc. v. Apotex, Inc., 655 F.3d 1352, 1361 (Fed. Cir. 2011), cert. denied, 132 S.Ct. 1755 (2012) (To render a claim obvious, prior art cannot be vague and must collectively, although not explicitly, guide an artisan of ordinary skill towards a particular solution.). Finally, Micron compares Figure 1 of Bennett with Figure 2 of the 037 patent and asserts they are nearly identical, allegedly because Bennetts User device corresponds to the 037 Patents CPU, ROM, and DRAM . . . (Micron Br. 6.) Yet, aside from the superficial fact that both figures illustrate devices

connected to a bus, even a cursory comparison reveals a major difference. Bennetts Figure 1 shows a VLSI Circuit User Device connected to the Versatile Bus, and there is no disclosure in Bennett that this VLSI device can be an individual DRAM chip. In contrast, Figure 2 of the 037 patent illustrates a synchronous DRAM chip.

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Excerpts from Fig. 1 of Bennett (left) and Fig. 2 of the 037 patent (right)

D.

Microns Alternative Ground for Invalidity Based on JEDEC and Park Contradicts this Courts Prior Decisions

Without even addressing the merits of the references, Micron argues that JEDEC and Park render claim 34 invalid. As an initial matter, because that argument was not part of Microns request for reexamination, Micron does not have standing to raise it. Instead, Samsung (another requester) raised that

argument in its request for reexamination, and Micron is now attempting to adopt Samsungs reexamination as its own, which is improper. 4 See 35 U.S.C. 315(b) (2002) (contemplating appeal only of issues raised by that requester), 317(a)

This argument was more fully explained in the briefing in two co-pending cases before this Court. See Rambus, Inc. v. Micron Technology, Inc., Appeal No. 20131224 (Fed. Cir.) (brief for Rambus filed June 27, 2013); Rambus, Inc. v. Micron Technology, Inc., Appeal No. 2013-1228 (Fed. Cir.) (brief for Rambus filed June 28, 2013). 26

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(prohibiting third-party requester from concurrently pursuing two inter partes reexaminations of the same patent). Moreover, as the examiner and the Board correctly concluded, Rambus is entitled to its priority date, such that JEDEC and Park are not prior art. (A1477-78 (relying on A4122-26); A1526; A39.) Micron contends claim 34 is overbroad because it is not limited to one particular type of bus, a multiplexed bus, even though the claim is directed exclusively to features other than the bus. As the examiner and the Board correctly found, however, the original disclosure of the 898 application is not limited to a multiplexed bus. (A37-38.) Indeed, this Court has already concluded the same thing, a decision that is stare decisis on this issue. In Rambus Inc. v. Infineon Techs. AG, 318 F.3d 1081, 1091-95 (Fed. Cir. 2003), in the context of claim construction, this Court analyzed whether the disclosure of the 898 application was limited to a multiplexed bus and found that a multiplexing bus is only one of many inventions disclosed in the 898 application. Id. at 1095. Micron asserts this Courts analysis of the disclosure was eclipsed by a later hypothetical statement by this Court in Hynix Semiconductor Inc. v. Rambus Inc., 645 F.3d 1336, 1352-53 (Fed. Cir. 2011). (Micron Br. 53-55.) But Micron misreads the Hynix decision. In Hynix, this Court held that a jury was reasonable in finding that Rambuss claims do, in fact, meet the written-description requirement without requiring a multiplexed bus. Hynix, 645 F.3d at 1351-53. 27

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Thus, the jurys determination and this Courts affirmance of it are themselves compelling evidenceand certainly provide substantial evidence to support the Boards determinationthat the claims meet the written-description requirement and are therefore entitled to their priority date. See Ariad Pharms., Inc. v. Eli Lilly & Co., 598 F.3d 1336, 1350-51 (Fed. Cir. 2010) (en banc) (written description requirement is a question of fact reviewed for substantial evidence). Indeed, this Court determined in Hynix, 645 F.3d at 1352-53, that the jurys fact-finding overcame any analogy to either ICU Medical or LizardTech, an analogy the Board similarly addressed and rejected (A37 (citing ICU Medical, Inc. v. Alaris Medical Systems, Inc., 558 F.3d 1368 (Fed. Cir 2009), and LizardTech, Inc. v. Earth Resource Mapping, Inc., 424 F.3d 1336, 1344 (Fed. Cir. 2005))). Thus, each of this Courts statements about the written description of the 898 application supports the examiners and the Boards holding. Contrary to Microns argument (Micron Br. 58-62), the original disclosure describes inventions that do not necessarily require a multiplexed bus, including synchronous memory devices, controllers for controlling such devices, and systems that include such devices. (A80-81[3:26-52, 4:42-46, 5:59-63]; A1605.) The specification goes on to describe numerous object[s] of this invention, only one of which is to a multiplexed bus. (A80[3:27-52] (referring to a relatively narrow bus).) For example, the specification discusses a bus interface for large 28

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blocks of data (A80[3:26-30]), or a clocking scheme allowing for high speed clock signals to be sent along the bus with minimal clock skew (A80[3:31-33]), neither of which necessarily requires a multiplexed bus. See also Infineon, 318 F.3d at 1905 (noting that a multiplexing bus is only one of many inventions disclosed in the 898 application). The specification refers repeatedly and generically to a bus, without indicating whether the bus is multiplexed or not. (See, e.g., A80[4:43-44] (bus lines are controlled-impedance, double-terminated lines); A81[5:58-63] (a bus [is connected] to an independent cache memory).) Although the specification describes a byte-wide, multiplexed data/address/control bus, it is described simply as the preferred bus architecture. (A82[8:23-32].) The specification never limits further bus discussion to this preferred multiplexed architecture. And, as the Board recognized, one of skill in the art would recognize that it is not so limited and that other important touted features in Rambuss disclosure, including synchronous operation and writing a block of a group of data, could have been practiced on generic buses without multiplexing. (A37-38; see A1605-06[3135].) The original claims of the 898 application also demonstrate that the inventors were in possession of generic bus claims. The Board correctly

recognized that certain original claims (73 and 91) required only a generic bus; not 29

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necessarily a multiplexed bus. (A38.) Claim 73, for example, required only a bus subsystem (A1986-87) and claim 91 required a plurality of external bus lines (A1996), but both were silent as to whether the claimed bus is multiplexed. Micron essentially complains that neither of these claims was directed to the bus itself (Micron Br. 60-61), but that assertion applies even more strongly to claim 34 on appeal, since it also does not recite a bus. (See A39 (distinguishing ICU Medical because here claim 34 does not require a bus at all).) Micron similarly states that only one prior-art reference (U.S. Patent No. 4,247,817 to Heller) discussed in the specification does not discuss a multiplexed bus and asserts that Heller is distinguishable because it is directed to parts of the invention other than the bus. (Micron Br. 62.) But claim 34, like Heller, is also directed to parts of the invention other than the bus. Thus, Microns alleged distinction actually proves Rambuss point, that the invention claimed in claim 34 is supported by the original specification and does not require a multiplexed bus. (See A39.) In sum, Microns alleged alternative ground for affirmance based on JEDEC and Park fails because Micron has raised an issue not within the scope of its reexamination and because claim 34 is entitled to its original April 1990 priority date, predating both references. This Court has twice held a generic bus to be

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supported by the specification, and the examiners and Boards decisions and the specification itself all support such a holding. III. CONCLUSION For the foregoing reasons and those explained in Rambuss opening brief, this Court should reverse the Boards decision finding the 037 patent invalid as obvious and reinstate the examiners finding of nonobviousness.

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Dated: July 22, 2013

Respectfully submitted,

/s/ James R. Barney J. Michael Jakes James R. Barney Molly R. Silfen FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER, LLP 901 New York Avenue, NW Washington, DC 20001 (202) 408-4000 Attorneys for Appellant Rambus Inc.

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CERTIFICATE OF COMPLIANCE I certify that the foregoing REPLY BRIEF FOR RAMBUS INC. contains 6,963 words as measured by the word-processing software used to prepare this brief.

Dated: July 22, 2013

Respectfully submitted,

/s/ James R. Barney J. Michael Jakes James R. Barney Molly R. Silfen FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER, LLP 901 New York Avenue, NW Washington, DC 20001 (202) 408-4000

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CERTIFICATE OF SERVICE I hereby certify that copies of the foregoing REPLY BRIEF FOR RAMBUS INC. were served upon registered counsel by operation of the Courts CM/ECF system on this 22nd day of July, 2013. Henry A. Petri, Jr. Novak Druce Connolly Bove + Quigg, LLP 1875 Eye Street, NW, 11th Floor Washington, DC 20001 henry.petri@novakdruce.com

/s/ Kay Wylie