6.

111 Lecture 6
Today: 1.Blocking vs. non-blocking assignments 2.Single clock synchronous circuits 3.Finite State Machines

6.111 Fall 2005

Lecture 6, Slide 1

I. Blocking vs. Nonblocking Assignments

Conceptual need for two kinds of assignment
(in always blocks):

a b

a b c

x y

Blocking: Evaluation and assignment are immediate Non-Blocking: Assignment is postponed until all r.h.s. evaluations are done When to use:
( only in always blocks! )

a = b b = a a <= b b <= a
Sequential Circuits

x = a & b y = x | c x <= a & b y <= x | c

Combinatorial Circuits
Lecture 6, Slide 2

6.111 Fall 2005

Assignment Styles for Sequential Logic

Flip-Flop Based Digital Delay Line
in clk q1 q2 out

D Q

D Q

D Q

Will nonblocking and blocking assignments both produce the desired result?
module nonblocking(in, clk, out); input in, clk; output out; reg q1, q2, out; always @ (posedge clk) begin q1 <= in; q2 <= q1; out <= q2; end endmodule
6.111 Fall 2005

module blocking(in, clk, out); input in, clk; output out; reg q1, q2, out; always @ (posedge clk) begin q1 = in; q2 = q1; out = q2; end endmodule
Lecture 6, Slide 3

Use Nonblocking for Sequential Logic

always @ (posedge clk) begin q1 <= in; q2 <= q1; out <= q2; end
At each rising clock edge, q1, q2, and out simultaneously receive the old values of in, q1, and q2.

always @ (posedge clk) begin q1 = in; q2 = q1; out = q2; end

At each rising clock edge, q1 = in. After that, q2 = q1 = in; After that, out = q2 = q1 = in; Finally out = in.

q1 in clk D Q D Q

q2 D Q out clk in D Q

q1 q2

out

Blocking assignments do not reflect the intrinsic behavior of multi-stage sequential logic

Guideline: use nonblocking assignments for sequential always blocks

6.111 Fall 2005 Lecture 6, Slide 4

Use Blocking for Combinational Logic

Blocking Behavior
(Given) Initial Condition a changes; always block triggered

abc xy 110 010 010 010 11 11 01 00

x = a & b; y = x | c;

always @ (a or b or c) begin x = a & b; a y = x | c; b end

c

x y

Nonblocking Behavior
(Given) Initial Condition a changes; always block triggered

abc xy 110 010 010 010 010 11 11 11 11 01

Deferred

x <= a & b; y <= x | c;

Assignment completion

x<=0 x<=0, y<=1

always @ (a or b or c) begin x <= a & b; y <= x | c; end

Nonblocking assignments do not reflect the intrinsic behavior of multi-stage combinational logic While nonblocking assignments can be hacked to simulate correctly (expand the sensitivity list), its not elegant

Guideline: use blocking assignments for combinational always blocks

6.111 Fall 2005 Lecture 6, Slide 5

Implementation for on/off button

button light

module onoff(button,light); input button; output light; reg light; always @ (posedge button) begin light <= ~light; end BUTTON endmodule
6.111 Fall 2005

D Q Q

LIGHT

Lecture 6, Slide 6

II. Single-clock Synchronous Circuits

Well use Flip Flops and Registers groups of FFs sharing a clock input in a highly constrained way to build digital systems.

Single-clock Synchronous Discipline:

No combinational cycles Single clock signal shared among all clocked devices Only care about value of combinational circuits just before rising edge of clock Period greater than every combinational delay Change saved state after noise-inducing logic transitions have stopped!
6.111 Fall 2005 Lecture 6, Slide 7

Clocked circuit for on/off button

module onoff(clk,button,light); input clk,button; output light; reg light; always @ (posedge clk) begin if (button) light <= ~light; end endmodule
0 D 1

Does this work with a 1Mhz CLK?

BUTTON CLK
SINGLE GLOBAL CLOCK
6.111 Fall 2005

LE CLK

D Q

LIGHT

LOAD-ENABLED REGISTER
Lecture 6, Slide 8

Asynchronous Inputs in Sequential Systems

What about external signals?
Sequential System

Cant guarantee setup and hold times will be met!

Clock

When an asynchronous signal causes a setup/hold violation...

I Q D Clock
Transition is missed on first clock cycle, but caught on next clock cycle.
6.111 Fall 2005

II

III
?

Transition is caught on first clock cycle.

Output is metastable for an indeterminate amount of time.

Q: Which cases are problematic?

Lecture 6, Slide 9

Asynchronous Inputs in Sequential Systems

All of them can be, if more than one happens simultaneously within the same circuit.

Idea: ensure that external signals directly feed exactly one flip-flop
Clocked Synchronous System Async Input D Q Q0

Sequential System D Q

Clock D Q Q1

Clock

Clock

This prevents the possibility of I and II occurring in different places in the circuit, but what about metastability?

6.111 Fall 2005

Lecture 6, Slide 10

Handling Metastability
Preventing metastability turns out to be an impossible problem High gain of digital devices makes it likely that metastable conditions will resolve themselves quickly Solution to metastability: allow time for signals to stabilize
Likely to be metastable right after sampling Very unlikely to be metastable for >1 clock cycle Extremely unlikely to be metastable for >2 clock cycle

D Q

D Q D Q

Complicated Sequential Logic System

Clock

How many registers are necessary?

Depends on many design parameters(clock speed, device speeds, ) In 6.111, a pair of synchronization registers is sufficient
Lecture 6, Slide 11

6.111 Fall 2005

III. Finite State Machines

Finite State Machines (FSMs) are a useful abstraction for sequential circuits with centralized states of operation At each clock edge, combinational logic computes outputs and next state as a function of inputs and present state

inputs + present state n

Combinational Logic

outputs + next state n

Q
CLK
6.111 Fall 2005

FlipFlops

Lecture 6, Slide 12

Example 1: Light Switch

State transition diagram
BUTTON=1 BUTTON=0 LIGHT = 0 BUTTON=1 LIGHT = 1 BUTTON=0

Logic diagram

Combinatorial logic
0 1

BUTTON CLK
6.111 Fall 2005

D Q

LIGHT

Register

Lecture 6, Slide 13

Two Types of FSMs

Moore and Mealy FSMs : different output generation
Moore FSM:
next state S+ Comb. Logic
n CLK D

inputs
x0...xn

Flip- Q Flops
n

Comb. Logic

outputs yk = fk(S)

present state S

Mealy FSM:
direct combinational path!

inputs
x0...xn
Comb. Logic

outputs yk = fk(S, x0...xn)

Comb. Logic
n

S+
n CLK

FlipFlops

S
6.111 Fall 2005 Lecture 6, Slide 17

Design Example: Level-to-Pulse

A level-to-pulse converter produces a single-cycle pulse each time its input goes high. Its a synchronous rising-edge detector. Sample uses:
Buttons and switches pressed by humans for arbitrary periods of time Single-cycle enable signals for counters Level to L P Pulse Converter
Whenever input L goes from low to high... CLK

...output P produces a single pulse, one clock period wide.

6.111 Fall 2005

Lecture 6, Slide 18

Step 1: State Transition Diagram

Block diagram of desired system:
Synchronizer
unsynchronized user input CLK

Edge Detector Level to Pulse FSM

D Q

D Q

State transition diagram is a useful FSM representation and design aid:

if L=1 at the clock edge, then jump to state 01.

L=1 00 01
Edge Detected!

L=1 11
High input, Waiting for fall

Binary values of states

L=0

Low input, Waiting for rise

L=1

P=0
if L=0 at the clock edge, then stay in state 00.

P=1 L=0 L=0

P=0
This is the output that results from this state. (Moore or Mealy?)

6.111 Fall 2005

Lecture 6, Slide 19

Step 2: Logic Derivation

Transition diagram is readily converted to a state transition table (just a truth table)
L=1 L=0 L=1 L=1

Curren In t State S1 0 0 0 0 1 1 S0 0 0 1 1 1 1 L 0 1 0 1 0 1

Next State S1+ S0+ 0 0 0 1 0 1 0 1 0 1 0 1

Out
P 0 0 1 1 0 0

00
Low input, Waiting for rise

01
Edge Detected!

11
High input, Waiting for fall

P=0

P=1
L=0

P=0 L=0

Combinational logic may be derived using Karnaugh maps

S1S0 for S1 : 00 01 11 10 L
+

0 0 0 0 X 1 0 1 1 X
+:

S+ Comb. Logic
n CLK D Flip- Q

S1S0 for S0 00 01 11 10 L

Flops
n

Comb. Logic

P S0 S1

for P:

0 0 0 0 X 1 1 1 1 X

+ + = LS S S1 0 1 = LS 0 + += S L S0 = L 0

P S0 P= =S S1 1S 0

0 1 0 0 X 1 1 0

6.111 Fall 2005

Lecture 6, Slide 21

Moore Level-to-Pulse Converter

inputs
x0...xn
next state S+ Comb. Logic
n CLK n D

Flip- Q Flops

Comb. Logic

outputs yk = fk(S)

present state S
+ + = LS S S1 0 1 = LS 0 + + S = L S0 = L 0

P S0 P= =S S1 1S 0

Moore FSM circuit implementation of level-to-pulse converter:

L
S0+
CLK

Q Q

S0

S1+

Q Q

S1

6.111 Fall 2005

Lecture 6, Slide 23

Design of a Mealy Level-to-Pulse

direct combinational path!

S+ Comb. Logic
n CLK D Flip- Q

Comb. Logic
n

Flops S

Since outputs are determined by state and inputs, Mealy FSMs may need fewer states than Moore FSM implementations
1. When L=1 and S=0, this output is asserted immediately and until the state transition occurs (or L changes).

L P

1 2

L=1 | P=1 L=0 | P=0

Clock

0
Input is low L=0 | P=0

1
Input is high

State
Output transitions immediately. State transitions at the clock edge.

L=1 | P=0
2. After the transition to S=1 and as long as L remains at 1, this output is asserted.
6.111 Fall 2005

Lecture 6, Slide 24

Mealy Level-to-Pulse Converter

L=1 | P=1

Pres. State

In L 0 1 0 1

Next Out State S+ 0 1 0 1 P 0 1 0 0

0
Input is low L=0 | P=0 L=0 | P=0

1
Input is high

L=1 | P=0

S 0 0 1 1

Mealy FSM circuit implementation of level-to-pulse converter:

P L
S+
CLK

Q Q

FSMs state simply remembers the previous value of L Circuit benefits from the Mealy FSMs implicit singlecycle assertion of outputs during state transitions
6.111 Fall 2005 Lecture 6, Slide 26

Moore/Mealy Trade-Offs
How are they different?
Moore: outputs = f( state ) only Mealy outputs = f( state and input ) Mealy outputs generally occur one cycle earlier than a Moore: Moore: delayed assertion of P
L P Clock State[0]

Mealy: immediate assertion of P

L P Clock State

Compared to a Moore FSM, a Mealy FSM might...

Be more difficult to conceptualize and design Have fewer states
6.111 Fall 2005 Lecture 6, Slide 27

FSM Timing Requirements

Timing requirements for FSM are identical to any generic sequential system with feedback
Minimum Clock Period
inputs + present state

Minimum Delay
inputs + present state

Combinational Logic

outputs + next state

Combinational Logic

outputs + next state

Tlogic Tcq
Q FlipFlops D

Tcd,logic Tcd,reg
Q FlipFlops D

CLK

Tsu

Thold

CLK

T > Tcq + Tlogic + Tsu

6.111 Fall 2005

Tcd,reg + Tcd,logic > Thold

Lecture 6, Slide 28

Summary
Assignments in always blocks:
blocking (=) for combinational logic non-blocking (<=) for sequential logic

Single-clock Synchronous discipline:

Reliable digital circuits / systems Global clock to edge-triggered registers

Finite state machines:

Programmable systems Moore & Mealy

Combinational Logic

Q
6.111 Fall 2005

FlipFlops

D
Lecture 6, Slide 29