DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

LABORATORY MANUAL FOR

ECAD & VLSI LAB

(IV B.Tech., I Sem)

BALAJI INSTITUTE OF TECHNOLOGY & SCIENCE

Laknepally, Narsampet, Warangal

Department of Electronics &Communication Engineering

ECAD & VLSI Lab

CMOS Layers

n-well process p-well process Twin-tub process

n-well process

MOSFET Layers in an n-well process

Layer Types

p-substrate n-well n+ p+ Gate oxide Gate (polycilicon) Field Oxide

Insulated glass Provide electrical isolation

Department of Electronics &Communication Engineering

ECAD & VLSI Lab

Top view of the FET pattern

Metal Interconnect Layers

Metal layers are electrically isolated from each other Electrical contact between adjacent conducting layers requires contact cuts and vias

Metal Interconnect Layers

Department of Electronics &Communication Engineering

ECAD & VLSI Lab

Interconnect Layout Example

Designing MOS Arrays

Department of Electronics &Communication Engineering

ECAD & VLSI Lab

Parallel Connected MOS Patterning

Basic Gate Design

Both the power supply and ground are routed using the Metal layer n+ and p+ regions are denoted using the same fill pattern. The only difference is the n-well Contacts are needed from Metal to n+ or p+

The CMOS NOT Gate

Department of Electronics &Communication Engineering

ECAD & VLSI Lab

Alternate Layout of NOT Gate

NAND2 Layout

NOR2 Layout

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NAND2-NOR2 Comparison

General Layout Geometry

Graph Theory: Euler Path

Department of Electronics &Communication Engineering

ECAD & VLSI Lab

Stick Diagrams

Cartoon of a layout. Shows all components. Does not show exact placement, transistor sizes, wire lengths, wire widths, boundaries, or any other form of compliance with layout or design rules. Useful for interconnect visualization, preliminary layout

compaction, power/ground routing, etc. Stick Diagrams

Department of Electronics &Communication Engineering

ECAD & VLSI Lab

Stick Diagram - Example I

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ECAD & VLSI Lab

Stick Diagram - Example II

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ECAD & VLSI Lab

Design Rules

Description of digital IC

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Process design rules

Lambda rules

Feature Size: minimum distance between source and transistor Feature size = 2 (@ 90nm feature size =45)

drain of

According to Moores Law, how much does the feature scale by every ~2 years?

size

Department of Electronics &Communication Engineering

ECAD & VLSI Lab

Design rules and gate layout

CMOS Process Layers

Department of Electronics &Communication Engineering

ECAD & VLSI Lab

Intra-Layer Design Rules

Transistor Layout

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Vias and Contacts

2 Via 1 1 5 Metal to 1 Active Contact Metal to Poly Contact 3 2 4

2 2

Select Layer
2 3 2 1 3 3 Select

Substrate

Well

Department of Electronics &Communication Engineering

ECAD & VLSI Lab

CMOS Inverter Layout

GND In VDD

Out (a) Layout

A p-substrate n
+

A n p
+

Field Oxide

(b) Cross-Section along A-A

A CMOS Inverter

Department of Electronics &Communication Engineering

ECAD & VLSI Lab

A CMOS NAND Gate

A CMOS NOR Gate

Department of Electronics &Communication Engineering

ECAD & VLSI Lab