IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO.

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A Novel Semiconductor Capacitive Sensor for a Single-Chip Fingerprint Sensor/Identifier LSI

Katsuyuki Machida, Member, IEEE, Satoshi Shigematsu, Member, IEEE, Hiroki Morimura, Member, IEEE, Yasuyuki Tanabe, Norio Sato, Nobuhiro Shimoyama, Toshihiko Kumazaki, Kazuhisa Kudou, Masaki Yano, and Hakaru Kyuragi

AbstractWe describe a new semiconductor capacitive sensor structure and the fabrication process for a single-chip fingerprint sensor/identifier LSI in which the sensor is stacked on a 0.5- m CMOS LSI. To ascertain the influence of the fabrication process and normal usage on the underlying LSI, sensor chips were subjected to an electrostatic discharge (ESD) test, mechanical stress test, and unsaturated pressure cooker test (USPCT). ESD tolerance is obtained at the value of 3.0 kV. To investigate mechanical stress, we carried out a tapping test. The sensor is immune to mechanical stress under the condition of 104 taps with the strength of 1 MPa. A multilayer passivation film consisting SiN under polyimide film provides protection against contamination such as water. Thus, under USPCT conditions of 130 C, 80% humidity, and 48 h, the chips were not degraded. The tests confirm that the proposed sensor has sufficient reliability for normal identification usage. Index TermsESD, fingerprint sensor, LSI, process, reliability, sensor.

I. INTRODUCTION SER authentication by fingerprints is an attractive way to prevent illegal usage of mobile equipment and secure devices. Recently, semiconductor capacitive sensor chips for fingerprint identification have been developed for small fingerprint identification systems [1][4]. These sensors were fabricated using LSI multilevel interconnection process technology with a conventional plate structure [1]. These are not enough to ensure sensor reliability. Also, a reliability estimation of fingerprint sensor LSI has not been established. In electrostatic discharge (ESD) tests, it is not clear whether the ESD should be applied by touching the sensor directly or indirectly with the probe. Then there is the issue of mechanical strength; even though the mechanical strength of sensor surface is a very serious concern, there is no data on finger pressure exerted on the sensor by touching. Still another issue is protection against contamination. For long-term reliability, a passivation film should be considered for this purpose because the sensor surface becomes dirty and degrades with regular use.
Manuscript received May 7, 2001; revised June 27, 2001. The review of this paper was arranged by Editor K. Najafi. K. Machida, Y. Tanabe, N. Sato, and H. Kyuragi are with NTT Telecommunications Energy Laboratories, Kanagawa 243-0198, Japan (e-mail: machi@aecl.ntt.co.jp). S. Shigematsu, H. Morimura, and N. Shimoyama are with NTT Lifestyle and Environmental Technology Laboratories, Kanagawa 243-0198, Japan. T. Kumazaki is with NTT Electronics, Kanagawa 243-0198, Japan. K. Kudo and M. Yano are with NTT Advanced Technology, Kanagawa 2430198, Japan. Publisher Item Identifier S 0018-9383(01)08360-5.

On the other hand, because identification systems using the above sensors require many chips such as a microprocessor and memories, it is possible to tamper with the data in the chip from the interconnections among chips. Stacking the sensor on the identifier in a single-chip would make systems much more secure. We have developed a single-chip fingerprint sensor/identifier LSI (FIL-chip) [5] in which the sensor is stacked on a 0.5m CMOS LSI. The FIL-chip consists of many sensor pixels, and each pixel has a capacitive sensor, a sensor circuit, and a logic circuit. This stacked configuration is tamper-proof, but, because the sensor and logic circuits contain many MOSFETs and are located under the capacitive sensor, the sensor fabrication and the identification usage may damage the MOSFETs. Thus, sensor reliability, from the standpoint of the influence of the fabrication process and regular usage on the underlying LSI, must be investigated in terms of the chip degradation caused by ESD, mechanical stress due to finger pressure, and contaminants. This paper first describes the new sensor structure, the sensor fabrication process, and the characteristics of the FIL-chip. Next, the reliability estimation tests for our chips are explained. Then, the results of ESD tests and tapping tests for evaluating mechanical strength are presented. Finally, we discuss protection against contamination at the sensor surface and present the results of an unsaturated pressure cooker test (USPCT). II. SENSOR STRUCTURE AND FABRICATION PROCESS Fig. 1 shows the sensor structure. The single-chip sensor/identifier LSI has many sensor pixels. Each pixel consists of a capacitive sensor, a sensor circuit, and a logic circuit. To ensure reliability, the sensor has 1) a grounded wall (GND wall) for ESD tolerance; 2) a gold electrode to prevent oxidation; 3) a thick, hard passivation film consisting of a layer of polyimide over a layer of SiN to keep moisture out. Fig. 2 shows the sensor fabrication process flow. The novelty of our approach is the integration of the sensor on each pixel. The sensor is fabricated after the 0.5- m CMOS LSI and three-metal interconnection processes. The sensor process temperature is below 350 C to prevent contamination diffusion. The sensor plate and GND wall are 1.0- and 3.0- m thick, respectively. They are made of gold and are fabricated by electroplating, which is an easy and simple way to form a thick film. The seed layers for electroplating are deposited by evaporating

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Fig. 1.

Cross section of sensor and identifying array.

Fig. 3. FIL-chip surface of SEM (scanning electron microscope) and the cross section of FIB (focused ion beam) photographs. TABLE I FIL-CHIP CHARACTERISTICS

Fig. 2.

Sensor fabrication process.

Au/Cr on the SiN film [Fig. 2(a)]. The SiN film is deposited at a substrate temperature of 300 C, using SiH /NH /N gas by plasma CVD (chemical vapor deposition). The Au, Cr, and SiN films are 0.1- m thick. After resist patterning and electroplating, the sensor plate and GND wall are patterned by wet etching [Fig. 2(b)]. Photosensitive polyimide film is applied to the thick, hard passivation layer. A polybenzoxazole material is used as polyimide. It is also spin-coated onto the sensor plate and the GND wall, and the polyimide on GND wall is exposed to UV irradiation in order to planarize the surface [Fig. 2(c)]. After that, the polyimide film is annealed at 310 C in nitrogen atmosphere. Finally, the planarization structure of the sensor surface

is obtained [Fig. 2(d)]. This sensor fabrication process is simple and cost effective. Fig. 3 shows a scanning electron micrograph (SEM) and a focused ion beam (FIB) photograph of the sensor structure. The SEM shows the sensor/identifier array at the FIL-chip surface. One can see that the planarization structure of the sensor surface is clearly achieved. Each pixel is 81.6 m 81.6 m. The FIB photograph shows that the sensor plate is fabricated on the MOSFETs and the GND wall is exposed at the sensor surface. The FIL-chip has an embedded controller and program memory. The controller operates at 1 MHz and consumes 187 W at a supply voltage of 3.3 V. The FIL-chip has 20 584 pixels, and each pixel contains 158 MOSFETs. It operates at the practical sensing and identifying time of 102 ms. The characteristics of the FIL-chip are summarized in Table I. III. RELIABILITY ESTIMATION TESTS In this section, we explain the reliability estimation tests for our chips. The ESD test, tapping test for mechanical stress, and USPCT are demonstrated. The ESD test was performed by directly touching the sensor surface with the probe because, in practical use, the fingerprint sensor LSI is touched directly by the finger. The diagram of the

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Fig. 4.

ESD measurement circuit.

measurement circuit is shown in Fig. 4. The circuit is based on the human body model (HBM). The fingerprint sensor to be tested is set on the estimation board and is connected to the voltage sources. The probe electrode is made of gold and is controlled by a spring. The ESD voltage was applied to the sensor surface three times. The same voltage, which had both positive and negative polarity, was applied each time. Mechanical stress due to finger pressure was examined by a tapping test. From the viewpoint of sensor reliability, it is important to know the finger pressure exerted on the sensor by touching. After conducting measurements to determine the normal finger pressure, tapping tests were carried out using a finger pressure larger than the normal one. The finger pressure was measured using pressure sensitive film (Fuji Prescale Film) in the range of 0.22.5 MPa. The measurement was carried out using 100 persons. How finger pressure affects the MOSFET characteristics and the sensing image of the FIL-chip was investigated using the tapping tests. The MOSFET for the tapping test was fabricated by the same process used for the MOSFETs in the FIL-chip. The gate oxide thickness and the gate length of the MOSFET are 11 nm and 0.5 m, respectively. To investigate the long-term reliability, we performed USPCT to chips. The USPCT was carried out under the conditions of 130 C, 80% humidity, and 48 h. Fingerprint images before and after USPCT are investigated. This condition will give us an estimate comparable to 20 years of practical usage at 30 C and 70% humidity. IV. EXPERIMENTAL RESULTS A. Electrostatic Discharge Tolerance to ESD is necessary because the fingerprint sensor could be destroyed by the charge from the finger. To ensure ESD tolerance, we use the GND wall structure and a new configuration in the sensor circuit. The GND wall is connected to ground and surrounds the sensor plate to discharge the finger charge. Fig. 5 shows our configuration and the conventional sensor circuit. The sensor plate of a conventional sensor circuit is connected to the gate electrode, so ESD tolerance depends on the gate breakdown voltage. In our configuration, to avoid the gate breakdown of conventional circuits like gate electrode of MOSFET Q2, the sensor plate is connected to the source electrode of MOSFET Q1 because its junction breakdown voltage is higher than the gate breakdown voltage. This circuit configuration is applied to the sensor circuit [6].

Fig. 5. Circuit configuration. Cr is the reference capacitance. Sout is the sensing signal output.

Fig. 6. Sensed image before and after ESD test.

The ESD tests were carried out three times using the same voltage, which had both positive and negative polarity, by directly touching the sensor surface with the probe. We applied the maximum voltage of 3.0 kV to the probe electrode. Tests were started 0.5 kV, and the voltage was increased in 0.5 kV increments. Final tests were carried out at 3.0 kV. Testing of 12 samples resulted in no failures. The results indicate that the sensor did not degrade and that the ESD tolerance of the test samples could exceed 3.0 kV without failures. Fingerprint images obtained before and after the ESD tests are shown in Fig. 6. A voltage of 2.0 kV, which is the standard in conventional LSI ESD tests, was used to test the ESD tolerance. However, even for the 3.0 kV test, the fingerprint image did not degrade, which indicates that the proposed sensor has high ESD tolerance. B. Mechanical Stress Due to Finger Pressure The histogram of the maximum finger pressure exerted on the chip surface is shown in Fig. 7. It indicates that the normal pressure during touching is below 0.6 MPa. Thus, a pressure of 1 MPa is sufficient for a tapping test. Fig. 8 shows the MOSFET characteristics after the tapping test. The threshold voltage and transconductance were not degraded by the tapping.

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Fig. 7. Finger pressure measurements for various persons. The measurement was carried out by using pressure sensitive film in the range of 0.22.5 MPa.

Fig. 10. TDS spectra of H O in three samples. The rate of heating was a constant 20 C/min. O TEOS film was used as the water source.

Fig. 8. MOSFET characteristics after pressure. The MOSFET was fabricated by the same process as the FIL-chip.

Fig. 11. Chip surface photograph and sensed image after USPCT.

C. Protect Against Contamination and Unsaturated Pressure Cooker Test In practical use, the sensor is touched by the finger and exposed to the atmosphere, so protection against moisture and Na is needed. Perspiration from the finger is considered to be the main contaminant. For long-term usage, the passivation film characteristics for protection against contamination are important. To examine the reliability of the sensor, we investigated the film layer under the polyimide film and carried out the USPCT for the long-term reliability estimation. To prevent water penetration, a thin SiN film is used under the polyimide film. The SiN and polyimide are 0.1- m and 3.0- m thick, respectively. It is well known that a thick SiN film has contamination-blocking ability. Thus, to examine the contamination blocking ability of SiN film, we used thermal desorption

Fig. 9. Sensed images before and after 10 000 tappings. Each tap had 1 MPa of pressure and lasted 2 s.

Fig. 9 shows sensed images before and after the tapping test; the taps. This test proves image was not degraded after tapping the FIL-chip has high tolerance against tapping. This is because the strength of the polyimide film used as the passivation film is 100 MPa. Thus, it is confirmed that the proposed sensor has the tolerance against mechanical stress.

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spectroscopy (TDS). The TDS spectra were measured in a lamp-heated high-vacuum quartz tube, in which the ion intensity was monitored with a quadrupole mass spectrometer. The rate of heating was a constant 20 C/min. TDS measurements were carried out for three kinds of film structure, O TEOS on Si, SiN/O TEOS on Si, and polyimide on Si. As a water source, we used O TEOS film, which is known to have high water absorption. TDS measurements were carried out for three kinds of film structure. The ion intensities in Fig. 10 show the H O. The ion intensity of the O TEOS film indicates that it contains the water. It is clear that the thin SiN film completely prevents water penetration and that the polyimide does not absorb water below 310 C. The results suggest that the proposed sensor is protected against contamination. Moreover, we examined USPCT to confirm the effect of the protection. Fig. 11 shows a photograph of a sensed image after USPCT; the chip surface and the image were not degraded after USPCT. This result shows that the chip should last for 20 years at 30 C and 70% humidity. Therefore, it is confirmed that our sensor has the potential for long-term identification usage.

[3] D. Inglis, L. Manchanda, R. Comizzoll, A. Dickinson, E. Martin, S. Mandis, P. Silveman, G. Weber, B. Ackland, and L. O. Gorman, A robust, 1.8V 250W direct-contact 500dpi fingerprint sensor, in ISSCC Tech. Dig., Feb. 1998, pp. 284285. [4] P. Rey, P. Charvet, M. T. Delaye, and S. Abou Hassan, A high density capacitive pressure sensor array for fingerprint sensor application, in Proc. Transducers97, Chicago, IL, June 1997, pp. 14531456. [5] S. Shigematsu, H. Morimura, Y. Tanabe, T. Adachi, and K. Machida, A single-chip fingerprint sensor and identifier, IEEE J. Solid-State Circuits, vol. 34, pp. 18521859, Dec. 1999. [6] H. Morimura, S. Shigematsu, and K. Machida, A novel sensor cell architecture and sensing circuit scheme for capacitive fingerprint sensors, IEEE J. Solid-State Circuits, vol. 35, pp. 724731, Dec. 2000.

V. SUMMARY We have proposed a new structure in which a semiconductor capacitive sensor is stacked on the fingerprint identifier LSI in order to realize a single chip. The sensor fabrication process is simple and cost-effective due to the use of Au electroplating and photosensitive polyimide film. The FIL-chip characteristics demonstrate the effectiveness of the sensor structure and fabrication process. MOSFETs do not degrade under the sensor fabrication process. An ESD test method for the fingerprint sensor LSI was proposed. The reliability experiments reveal that the proposed sensor has 1) ESD tolerance above 3.0 kV; 2) high strength for mechanical stress; 3) the long-term protection against contamination. Therefore, it is confirmed that the proposed sensor is reliable enough for conventional fingerprint identification usage.

Katsuyuki Machida (M99) was born in Nagasaki, Japan, on April 16, 1954. He received the B.E., M.E., and Dr.Eng. degrees in electronics engineering from the Kyushu Institute of Technology, Kitakyusyu, Japan, in 1979, 1981, and 1995, respectively. In 1981, he joined the Musashino Electrical Communication Laboratory, Nippon Telegraph and Telephone Public Corporation (NTT), Musashino, Tokyo, Japan. Since then, he has engaged in the research on ECR plasma CVD, the development of LSI process and manufacturing technologies. He is now a Senior Research Engineer, Supervisor, at the NTT Telecommunications Energy Laboratories, Atsugi, Kanagawa, Japan. He is currently engaged in research and development on the material and manufacturing technologies for MEMS. Dr. Machida is a member of the Japan Society of Applied Physics.

Satoshi Shigematsu (M93) was born in Tokyo, Japan, on August 2, 1967. He received the B.S. and M.E. degrees in system engineering from Tokyo Denki University, Tokyo, Japan, in 1990 and 1992, respectively. In 1992, he joined Nippon Telegraph and Telephone Corporation (NTT), Tokyo. Since 1992, he has been engaged in the research and development of low-voltage, low-power CMOS circuit. He is now in the NTT Lifestyle and environmental technology Laboratories, Kanagawa, Japan. His research interests include biometrics sensor and identification circuit technologies, and low-power and high-speed circuit design technique. Mr. Shigematsu is a member of the Institute of Electronics, Information, and Communication Engineers of Japan.

ACKNOWLEDGMENT The authors would like to thank K. Takeya and J. Yamada for their helpful support and encouragement. They also would like to thank H. Ishii, K. Sakuma and Y. Okazaki for their helpful discussions.

REFERENCES
[1] M. Tartagni and R. Guerrieri, A fingerprint sensor based on the feedback capacitive sensing scheme, IEEE Trans. Solid-State Circuits, vol. 33, pp. 133142, Jan. 1998. [2] N. D. Young, G. Harkin, R. M. Bunn, D. J. McCuulloch, R. W. Wilks, and A. G. Knapp, Novel fingerprint scanning arrays using polysilicon TFTs on glass and polymer substrates, IEEE Electron Device Lett., vol. 18, pp. 1920, Jan. 1997.

Hiroki Morimura (M96) was born in Saitama, Japan, on January 9, 1968. He received the B.E. degree in physical electronics and the M.E. degree in applied electronics from the Tokyo Institute of Technology, Tokyo, Japan, in 1991 and 1993, respectively. In 1993, he joined Nippon Telegraph and Telephone Corporation (NTT), Tokyo. He is now at NTT Lifestyle and Environmental Technology Laboratories, Kanagawa, Japan. He has been engaged in the research and development of low-voltage, low-power SRAM circuits. He is currently doing research on sensing circuits for CMOS fingerprint sensors and developing single-chip fingerprint sensor/identifier LSIs for portable equipment. Mr. Morimura is a member of the Institute of Electronics, Information, and Communication Engineers of Japan.

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Yasuyuki Tanabe was born in Okayama, Japan, on June 17, 1953. He received the B.E. and M.E. degrees in electrical engineering from Waseda University, Tokyo, Japan, in 1976 and 1978, respectively. Since joining the Musashino Electrical Communications Laboratories, Nippon Telegraph and Telephone Public Corporation (NTT), Tokyo, in 1978, he has been engaged in the research on high-speed silicon bipolar devices using polysilicon self-aligned process technology and the development of BiCMOS process for telecommunications ASIC LSIs. His current research interests include reliability of fingerprint sensor LSIs. He is now a Senior Research Engineer at the NTT Telecommunications Energy Laboratories, Kanagawa, Japan. Mr. Tanabe is a member of The Institute of Electronics, Information, and Communication Engineers (IEICE) of Japan and The Japan Society of Applied Physics.

Kazuhisa Kudou was born in Miyazaki, Japan, on May 28, 1968. He received the B.E degree in the electronics engineering from the North Shore College, Kanagawa, Japan, in 1989. In 1989, he joined Nippon Telegraph and Telephone Technology Transfer Corporation, (NTEC), Atsugi, Kanagawa, Japan. Since then, he has been engaged in the development of plasma etching and LSI fabrication process. His current work is the development the thick film patterning technology for MEMS. He is now an Engineer with the NTT Advanced Technology Corporation, Atsugi, Kanagawa. Mr. Kudou is a member of the Japan Society of Applied Physics.

Norio Sato was born in Tokyo, Japan, in 1974. He received the B.S. and M.S. degrees in physics from Tokyo University, Japan, in 1997 and 1999, respectively. In 1999, he joined Nippon Telegraph and Telephone Corp. (NTT), Tokyo. He is now in the NTT Telecommunications Energy Laboratories, Kanagawa, Japan. Since 1999, he has been engaged in the research and development of the semiconductor fabrication process and MEMS. Mr. Sato is a member of the Japan Society of Applied Physics and the Physical Society of Japan. Atsugi, Kanagawa. Nobuhiro Shimoyama was born in Saitama, Japan, on January 2, 1961. He received the B.S. and M.S. degrees in electrical engineering from Nihon University, Chiba, Japan, in 1983 and 1985, respectively. In 1985, he joined the Atsugi Electrical Communication Laboratories, Nippon Telegraph and Telephone Corporation (NTT), Kanagawa, Japan. Since then, he has been engaged in research and development of Bi-CMOS LSI process and hot carrier reliability in MOS devices. He is now a Senior Research Engineer, at the NTT Lifestyle and Environmental Laboratories, Atsugi, Kanagawa. His current research interests include the reliability in MOS devices and reliability and endurance of IC cards. Mr. Shimoyama is a member of the Japan Society of Applied Physics.

Masaki Yano was born in Kanagawa, Japan, on March 11, 1967. He received the B.E degree in the electronics engineering from the North Shore College, Kanagawa, in 1987. In 1987, he joined Nippon Telegraph and Telephone Technology Transfer Corporation, (NTEC), Atsugi, Kanagawa. Since then, he has been engaged in the development of the CVD and LSI fabrication process. His current work is the electroplating and thick film technologies. He is now a Staff Engineer with the NTT Advanced Technology Corporation,

Toshihiko Kumazaki was born in Gifu, Japan, on October 3, 1963. He received the B.E degree in the electronics engineering from the North Shore College, Kanagawa, Japan, in 1984. In 1984, he joined Nippon Denshi Gijyutsu (NDG), Atsugi, Kanagawa, Japan. Since then, he has been engaged in the development of bipolar transistor fabrication process. His current work is the capacitive fingerprint sensor technology. He is now a Chief Engineer with the NTT Electronics, Atsugi, Kanagawa, Japan.

Hakaru Kyuragi was born in Fukuoka, Japan, on October 4, 1954. He received the B.E., M.E., and Dr.Eng. degrees in electronic engineering from Kyoto University, Kyoto, Japan, in 1978, 1980, and 2000, respectively. He joined the Nippon Telegraph and Telephone Public Corporation in 1980, where he has been involved in the research and development of interfacial reaction processes between refractory metal and poly silicon, SR-excited photo processes such as SiN film deposition and etching, and BiCMOS process technology using SR lithography. He is now Senior Research Engineer, Group Leader in Advanced System Devices Research Group, NTT Telecommunications Energy Laboratories. His current research interest is in the application of Si-based technology to fingerprint sensor, MEMS, and millimeter-wave component module. Dr. Kyuragi is a member of the Japan Society of Applied Physics and The Institute of Electronics, Information and Communication Engineers.