(BAR-ILAN

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UNIVERSITY (RA
School of Engineering
Ramat-Gan 52900, Israel

- 52900

1 2011

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120

 ' 35) 1(
:
C .D .Q C D .
Q D :
0 ,1 Q=0 D=1 Q .1 1 ,0 Q=1 D=0 Q .0 . :
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. SR-LATCH .
RESET RESET=1 Q.
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RGB .
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' 30) 3(
' ! N N=1 N=8
. !.N
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n.
. LOAD1 ,CLK1 LOAD2 .CLK2
. CLK2 CLK1 " ,
CLK2 .

In
CLK1
LOAD1

n-bit decimal presetable counter

n

n
PRESET

CLR
n
CLK2

n
n-bit parallel register
X

n-bit multiplier: Z=X*Y

LOAD2

PRESET

CLR
n
CLK2

n
n-bit parallel register
Out