IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO.

10, OCTOBER 2012

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Step-Up DC/DC Converters With Cascaded Quasi-Z-Source Network

Dmitri Vinnikov, Senior Member, IEEE, Indrek Roasto, Member, IEEE, Ryszard Strzelecki, Senior Member, IEEE, and Marek Adamowicz, Member, IEEE

AbstractThis paper is devoted to the step-up dc/dc converter family with a cascaded quasi-Z-source network (qZS-network). The cascaded (two-stage) qZS-network could be derived by the adding of one diode, one inductor, and two capacitors to the traditional quasi-Z-source inverter (qZSI). The proposed cascaded qZSI inherits all the advantages of the traditional solution (voltage boost and buck functions in a single stage, continuous input current, and improved reliability). Moreover, as compared to the conventional qZSI, the proposed solution reduces the shoot-through duty cycle by over 30% at the same voltage boost factor. Theoretical analysis of the two-stage qZSI in the shoot-through and non-shoot-through operating modes is described. The proposed and traditional qZS-networks are compared. A prototype of a step-up dc/dc converter with the cascaded qZS-network was built to verify the theoretical assumptions. The experimental results are presented and analyzed. Finally, a further optimization method of the cascaded qZS-network is proposed, and some practical design issues are discussed. Index TermsDCDC power conversion, fuel cells (FCs), power conditioning units (PCUs), pulsewidth-modulated power converters, rectiers.

I. I NTRODUCTION HE voltage-fed quasi-Z-source inverter [(qZSI); Fig. 1(a)] has been reported to be suitable for different renewable power applications (fuel cells (FCs), solar panels, wind power generators, etc.) because of its unique capability of voltage boost and buck functions in a single stage [1][4]. If necessary, the qZSI can boost the input voltage by introducing a special shoot-through switching state, which is the simultaneous conduction (cross conduction) of both switches of the same inverters phase leg. This switching state is forbidden for the traditional voltage-source inverters (VSIs) because it causes the short circuit of the dc-link capacitors. In the qZSI, the shootManuscript received December 2, 2010; revised May 6, 2011 and October 18, 2011; accepted November 15, 2011. Date of publication December 7, 2011; date of current version April 27, 2012. This work was supported in part by the Estonian Ministry of Education and Research under Project SF0140016s11 and in part by the Estonian Science Foundation under Grants ETF8538 and ETF8687. D. Vinnikov and I. Roasto are with the Department of Electrical Drives and Power Electronics, Tallinn University of Technology, 19086 Tallinn, Estonia (e-mail: dmitri.vinnikov@ieee.org; indrek.roasto@ieee.org). R. Strzelecki is with the Department of Ship Automation, Gdynia Maritime University, 81-225 Gdynia, Poland, and also with the Power Electronics Laboratories, Electrotechnical Institute, Po zaryskiego 28, 04-703 Warsaw, Poland (e-mail: rstrzele@am.gdynia.pl). M. Adamowicz is with the Department of Mechatronics and High Voltage Engineering, Gdansk University of Technology, 80-233 Gdansk, Poland (e-mail: madamowi@ely.pg.gda.pl). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TIE.2011.2178211

Fig. 1. (a) Voltage-fed qZSI and (b) voltage-fed qZSI with the cascaded qZSnetwork.

through states are used to boost the magnetic energy stored in the dc-side inductors L1 and L2 without short circuiting the dc capacitors C1 and C2 . This increase in magnetic energy, in turn, provides the boost of the voltage seen on the inverter output during traditional operating states. If the input voltage is high enough, the shoot-through states are eliminated, and the qZSI begins to operate as a traditional VSI. This paper discusses a method of performance improvement for the voltage-fed qZSI with continuous input current gained by the introduction of the cascaded quasi-Z-source network (qZS-network). The cascaded (two-stage) qZS-network is derived by the adding of one diode (D2 ), one inductor (L3 ), and two capacitors (C3 and C4 ) to the traditional qZSI, as shown in Fig. 1(b). The proposed cascaded qZS-network enables the duty cycle of the shoot-through state to be sufciently decreased at the same voltage boost factor and component stresses as those of the traditional qZSI [5][9]. Due to the decreased shootthrough duty cycle, the values of the inductors and capacitors of the qZS-network could also be decreased. On the other hand, for the same component ratings and voltage and current stresses, the qZSI with the proposed cascaded qZS-network will ensure a higher voltage boost factor than with traditional solutions.

0278-0046/$26.00 2011 IEEE

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Fig. 3. Equivalent schemes of the inverter during the non-shoot-through (active) states: (a) positive and (b) negative half-cycles.

Fig. 2. Proposed isolated step-up dc/dc converter based on a voltage-fed qZSI with a cascaded qZS-network and a voltage-doubler rectier.

II. N EW S TEP -U P DC/DC C ONVERTER W ITH C ASCADED qZS-N ETWORK The main focus of this paper is on the power conditioning units (PCUs) for residential power systems. PCUs are used to interconnect distributed energy sources producing low dc voltage, like FCs or solar panels (typically 4080 V dc), to the residential loads (typically 230 V ac single-phase or 3 400 V ac). Due to safety and dynamic performance requirements, the PCU should be realized within the dc/dc/ac concept [4]. This means that low voltage from the energy source rst passes through the front-end step-up dc/dc converter with galvanic isolation; afterward, the output dc voltage is inverted in the three-phase inverter and ltered to comply with the imposed standards and requirements (second dc/ac stage). Our novel approach to the front-end step-up dc/dc converters provides a very high voltage gain. The topology proposed (Fig. 2) utilizes the voltage-fed qZSI with a cascaded qZS-network and continuous input current, a high-frequency step-up isolation transformer, and a voltage-doubler rectier. This paper analyzes the design of the two-stage qZSI, whereas the design and operation of the transformerrectier stage of the converter remain the same as those with traditional isolated full-bridge converters [4], [10][13]. To regulate the varying input voltage, the front-end qZSI has two different operating modes: shoot-through and non-shootthrough. In the non-shoot-through mode, the qZSI performs only the voltage buck function. This operation mode is typically used during light-load conditions, when the output voltage of an FC or a solar panel reaches its maximum. The inverter is controlled in the same manner as with the traditional VSI, utilizing only the active states when one and only one switch in each phase leg conducts. The transistors in the full-bridge conguration are controlled alternately in pairs (T1 and T4 or T2 and T3 , Fig. 3) with 180 -phase-shifted control signals. In this operating mode, the duty cycle of inverter switches could never exceed 0.5. The equivalent circuit of the two-stage qZSI during non-shoot-through (active) states is shown in Fig. 5(a). When the input voltage drops below some predened value, the qZSI starts to operate in the shoot-through mode. In order to boost the input voltage during this mode, a special
Fig. 4. Equivalent scheme of the inverter during the shoot-through states.

Fig. 5. Equivalent circuits of the cascaded qZS-network: (a) During the nonshoot-through (active) state and (b) during the shoot-through state.

switching statethe shoot-through stateis implemented in the pulsewidth modulation (PWM) inverter control. During the shoot-through states, the primary winding of the isolation transformer is shorted through all switches of both phase legs (Fig. 4). This shoot-through state (or vector) is forbidden in the traditional VSIs because it would cause a short circuit of dc capacitors and destruction of power switches. The cascaded qZSnetwork makes the shoot-through states possible, effectively protecting the circuit from damage [14]. Moreover, the shootthrough states are used to boost the magnetic energy stored in the dc-side inductors L1 , L2 , and L3 without short circuiting the dc capacitors C1 , . . . , C4 . This increase in the magnetic energy, in turn, provides the boost of the voltage seen on the inverter output during the active states. The equivalent circuit of the two-stage qZSI during the shoot-through states is shown in Fig. 5(b).

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III. C IRCUIT A NALYSIS OF THE VOLTAGE -F ED qZSI W ITH C ASCADED qZS-N ETWORK In the non-shoot-through mode, the inverter bridge viewed from the dc side is equivalent to a current source [Fig. 5(a)]. From Fig. 5(a), for the active states, the voltages of the inductors can be represented as vL1 = VIN VC 1 vL2 = VC 4 VC 2 = VC 1 VC 3 vL3 = VC 4 . (1) (2) (3)
Fig. 6. Shoot-through duty cycle as a function of the voltage boost factor for different types of qZS-networks.

From the equivalent circuit of the two-stage qZSI during the shoot-through state [Fig. 5(b)], the voltages of the inductors can be represented as vL1 = VIN + VC 2 vL2 = VC 4 + VC 1 vL3 = VC 3 . (4) (5) (6)

The resulting boost factor B of the input voltage is B= 1 v dc = . VIN 1 3DS (14)

Let us consider that the duty cycles of the shoot-through and non-shoot-through states are DS and (1 DS ), correspondingly. At steady state, the average voltages of the inductors over one switching period are zero
t+T

For the desired input voltage boost factor B , the duty cycle of the shoot-through state is calculated as DS = 1 B 1 . 3 (15)

VL1 =
t t+T

vL1 dt = 0

Higher stage qZS-networks can be designed by just multiple repeating of the parts D2 C3 L3 C4 [Fig. 1(b)]. For the nthstage qZS-network, the boost factor B of the input voltage is Bn = 1 1 DS (1 + n) (16)

VL2 =
t t+T

vL2 dt = 0

where n is the number of stages (n = 1 for traditional qZSIs, n = 2 for two-stage qZSIs, etc.). (7) IV. C OMPARISON OF THE P ROPOSED T WO -S TAGE qZSI W ITH THE T RADITIONAL S OLUTION A. Boost Performance Comparison In contrast to the proposed two-stage qZS-network, the boost factor of the traditional topology based on two capacitors, two inductors, and one diode [single-stage qZS-network, Fig. 1(a)] is B= 1 . 1 2DS (17)

VL3 =
t

vL3 dt = 0.

From (1)(7), we obtain VL1 = v L1 = DS (VIN + VC 2 ) + (1 DS )(VIN VC 1 ) = 0 VL2 = v L2 = DS (VC 4 + VC 1 ) + (1 DS )(VC 4 VC 2 ) = 0 V L2 = v L2 = DS (VC 4 + VC 1 ) + (1 DS )(VC 1 VC 3 ) = 0 VL3 = v L3 = DS (VC 3 ) (1 DS )(VC 4 ) = 0. (8) Solving (8), the voltages of capacitors C1 , . . . , C4 could be found as VC 1 VC 2 VC 3 VC 4 1 2DS = VIN 1 3DS 2DS = VIN 1 3DS 1 DS = VIN 1 3DS DS = VIN . 1 3DS (9) (10) (11) (12)

The peak dc-link voltage across the inverter bridge is v dc = VC 1 + VC 2 = VC 3 + VC 4 = VIN 1 . 1 3DS (13)

As seen from Fig. 6, the proposed two-stage qZS-network features a 33.3% smaller shoot-through duty cycle at the same boost factor of the input voltage than the traditional qZSnetwork. It means that the time of the shoot-through states of the two-stage qZSI could be decreased by 33.3% for one switching period. The shoot-through duty cycle of the qZSI with the two-stage qZS-network and positive input voltage should never exceed one-third of the switching period, while in the traditional (single-stage) topology, it is, in theory, possible to use the shootthrough duty cycle values up to one-half. Practically, it is not advisable to operate at high shoot-through duty cycle values because it will cause high power losses in the components, which could seriously reduce the converters efciency.

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TABLE I O PERATING VOLTAGES OF THE I NDUCTORS AND C APACITORS OF THE T RADITIONAL AND T WO -S TAGE qZS-N ETWORKS

Capacitors also play a very signicant role in the qZSnetwork, absorbing the current ripple and limiting the voltage ripple across the inverter bridge. In order to limit the voltage ripple on the inverter during active states, for example, by 3% at the peak power, the capacitance of capacitors C1 , C2 , C3 , and C4 in the two-stage qZS-network should be C1 = C2 = C3 = C4 = = 2 P DS 0.03 VIN Vdc f (21)

P 2 f DS (1 3DS ). 0.015 VIN

Under the same operating conditions, the capacitance of capacitors C1 and C2 in a traditional (single-stage) qZSnetwork is C1 = C2 = = B. Comparison of Component Ratings In Table I, the operating voltages of the inductors and capacitors during the shoot-through states are compared for the traditional and the two-stage qZS-networks. The average currents through the inductors in both congurations have the same value IL,av = P VIN (18) 2 P DS 0.03 VIN Vdc f (22)

P 2 f DS (1 2DS ). 0.015 VIN

For the same operating conditions and target value of the dc-link voltage, the capacitors in the two-stage conguration should have capacitance values that are 33.3% lower than those of a traditional topology. Neglecting transients and voltage drops, the maximum voltage across the switches (T1 , . . . , T4 ) and the diodes (D1 and D2 ) will be equal to the peak dc-link voltage of the converter for both of the compared topologies. The average current through the diodes of the qZS-network equals the average current through the inductors (18) in both of the compared topologies. V. I MPACT OF C OMPONENT L OSSES ON THE VOLTAGE B OOST P ROPERTIES AND E FFICIENCY OF THE C ASCADED qZSI From (14), it follows that the proposed cascaded qZSI is theoretically capable of innite input voltage gain. In real practice, the voltage boost properties of the qZSI are seriously affected by the losses in components: inductors, diodes, and transistors. For more careful estimation of the operating characteristics of the cascaded qZSI, the loss elements should be added to the analysis. In our analysis, the losses in inductors L1 , . . . , L3 , as well as primary winding losses of the isolation transformer, are represented by the resistances rL , and losses in diodes during the conduction state are controlled by the voltage drop VD . Moreover, the insulated-gate bipolar transistor (IGBT) with a summarized saturation voltage of VS was assumed. To simplify the analysis, it was stated that the capacitors and inductors of the cascaded qZSI are identical. The secondary side (isolation transformer and rectierlter stack) of the converter was represented by the equivalent load resistance RO (represents the secondary part of the converter referred to the primary). Considering losses in components, (8) written for the lossless system could be extended to (23), shown at the bottom of the next page. Furthermore, the peak dc-link voltage of the cascaded qZSI could be expressed by (24), shown at the bottom of the next page.

where P is the system power rating and VIN is the input voltage. The maximum current through the inductors in both congurations occurs when the maximum shoot-through happens, which causes maximum ripple current. A 20% peak-to-peak current ripple through the inductors during maximum power operation was assumed for the comparison. During the shoot-through states, the voltages of inductors L1 , L2 , and L3 will have the same values and could be easily derived from (8). With the assumed peak-to-peak current ripple, the inductance for L1 , L2 , and L3 for the two-stage qZS-network can be calculated by L1 = L2 = L3 =
2 1 DS VC 3 DS VIN DS = 0.2 f IL,av 0.2 P f 1 3DS

(19)

where f is the operating frequency of the qZS-network. In the case of the traditional (single-stage) qZS-network, the inductance under the same operating conditions is L1 = L2 =
2 1 DS VC 1 DS VIN DS = . 0.2 f IL,av 0.2 P f 1 2DS

(20)

As stated earlier, at the same boost factor, the two-stage qZS-network features a shoot-through duty cycle that is 33.3% lower. Finally, it means that, at the same operating conditions and target value of the dc-link voltage, the inductors in the twostage conguration will have inductance values around 25% smaller than those of a traditional topology.

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Fig. 9. Impact of the inductors winding resistance on the efciency of the cascaded qZSI. Fig. 7. Comparison of idealized and practical boost properties of the proposed cascaded qZSI.

Fig. 10. Impact of forward voltage drop of a diode on the efciency of the cascaded qZSI. Fig. 8. Efciency of the experimental cascaded qZSI as a function of the shoot-through duty cycle.

In order to demonstrate the impact of losses in components on the input voltage boost properties of the cascaded qZSI, the lossless and lossy models with the following parameters were compared mathematically: VIN = 40 V RO = 4.5 VS = 1.7 V rL = 4 m VD = 1.6 V DS = 00.25.

Fig. 7 shows the impact of losses on the input voltage boost factor of the proposed cascaded qZSI. It could be found from the diagrams that, at the shoot-through duty cycle of DS = 0.25, the cascaded qZSI has demonstrated a reduction of 14% in the targeted amplitude dc-link voltage. Fig. 8 shows that, with selected components, the efciency of the cascaded qZSI lies in the range from 91.7% at DS = 0 to 87.1% at DS = 0.25.

In order to demonstrate the impact of component losses on the overall efciency of the cascaded qZSI, a comprehensive mathematical analysis was performed. First, the impact of the inductors winding resistance was studied. The results (Fig. 9) show that, with a 50% decrease of winding resistances (from 4 to 2 m), an efciency rise of only 1%1.5% could be obtained. In the second experiment, the impact of forward voltage drop of diodes D1 and D2 on the efciency of the cascaded qZSI was studied. Fig. 10 shows that, at the maximal shoot-through duty cycle (DS = 0.25) and selected fast-recovery epitaxial diodes (VD = 1.6 V), the maximal efciency, which could be obtained with the experimental cascaded qZSI, is 87.1%. However, if diodes are replaced with high-power Schottky rectiers with low forward voltage drop (VD = 0.6 V), an efciency rise by at least 5% could be expected. Thus, it was concluded that, during the design of the cascaded qZSI, serious attention should be paid to the minimization of the forward voltage drop of diodes.

V = v = D (V + V I r V ) + (1 D )(V V I r V ) = 0 L1 L1 S IN C2 L L S S IN C1 L L D VL2 = vL2 = DS (VC 1 + VC 4 IL rL VS ) + (1 DS )(VC 1 + VC 3 IL rL VD ) = 0 V = v = D (V I r V ) (1 D )(I r + V + V ) = 0

L3 L3 S C3 L L S S L L C4 D

VL3 = v L3 = DS (VC 3 IL rL VS ) + (1 DS )(VC 3 IL rL VC 1 VC 2 VD ) = 0 0 ) + (1 DS )(VC 4 I0 rL + VC 3 VC 0 + VD ) = 0 VL0 = vL0 = DS (VS I0 rL VC I0 IL IC 3 = iC 3 = DS IL + (1 DS )

2

(23)

=0

Vdc =

2 +(3R V (9R0 VD 9R0 VS +12VD rL 12VS rL )DS 0 IN 12R0 V D +3R0 V S 18V Dr L +3VIN r L +6V Sr L )D S +3R0 V D R0 VIN 6V Dr L VIN r L 2 +(6R +12r )D R 4r (9R0 12rL )DS 0 0 L S L

(24)

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TABLE II S PECIFICATIONS OF THE I NVESTIGATED S TEP -U P DC/DC C ONVERTERS

Fig. 11. Efciencies of a boost converter, a qZSI, and a cascaded qZSI as functions of the dc-link voltage.

In Fig. 11, the efciencies of three boost topologies (boost converter, single-stage qZSI, and cascaded qZSI) are compared. The topologies were modeled with the following parameters: VIN = 40 V Pload = 1000 W VS = 1.7 V rL = 4 m. VD = 1.6 V

It was assumed that all three topologies have the same output circuitry, i.e., a full-bridge inverter, an isolation transformer, a rectier, and an output lter. Thus, the output side could be simplied and replaced by an equivalent resistor. The value of the resistor was calculated separately for each topology according to the rated load power. The shoot-through duty cycle was calculated so that the required dc-link voltage could be achieved. The boost converter has the lowest component count, which results in the highest efciency, as shown in Fig. 11. The traditional qZSI has slightly smaller efciency, which more strongly depends on the dc-link voltage. The smallest efciency was achieved with the cascaded qZSI, as shown in Fig. 11. This effect is caused by the highest number of input lter components. VI. E XPERIMENTAL V ERIFICATION As it follows from the aforementioned analysis, in contrast to the traditional solution, the proposed two-stage qZSnetwork provides a reduction of 33.3% in the shoot-through duty cycle at the same input voltage boost factor. As a consequence, the values of the inductors and capacitors of the twostage qZS-network could also be reduced in comparison with the traditional solution [15]. However, the number of passive components and their summarized values will be increased. For example, despite the 33.3% capacitance reduction, the summarized capacitance value (C1 + C2 + C3 + C4 ) required for the two-stage qZS-network is 33.3% higher than that of the traditional solution. The summarized value of the required inductance (L1 + L2 + L3 ) will also be 12.5% higher. From here, the feasibility of the two-stage qZSI emerges. In this section, the proposed two-stage qZS-network will be experimentally compared with the traditional solution in terms of equal summarized values of passive components of the qZS-network. For that purpose, two qZSI-based isolated step-up dc/dc converters were assembled and tested. Both of the investigated converters are fairly identical in terms of the IGBT bridge, the isolation transformer, and lter assemblies; the only

Fig. 12. Measured waveforms of the input voltage VIN , dc-link voltage Vdc , and input current IIN of (a) the traditional (single-stage) qZS-network with DS = 0.25 and (b) the proposed two-stage qZS-network with DS = 0.167.

Fig. 13. Operating waveforms of the two-stage qZS-network operating with DS = 0.25: (a) Input voltage VIN , dc-link voltage Vdc , and input current IIN and (b) voltages of capacitors C1 , . . . , C4 .

modications done were within the qZS-networks. Specications of the investigated converters are listed in Table II. The experimental results are shown in Figs. 12 and 13. Both experiments were made in identical operating conditions with an input voltage of 44 V and a dc load of 700 . During shoot-through, small input voltage uctuations can be seen (Figs. 12 and 13). The uctuation is caused by the voltage drop in the input wires. During shoot-through, the load is suddenly increased, which results in voltage drops. Considering losses in the components of the qZS-network (voltage drops in diodes, transistors, and inductors), 80 V was set as the desired dc-link voltage, which means that the twofold boost of the input voltage was required. In the rst experiment, to achieve the targeted boost, the shoot-through duty cycle DS = 0.25 was set for the converter with a traditional (single-stage) qZS-network. In accordance with theoretical assumptions, the

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shoot-through duty cycle of the converter with the two-stage qZS-network was reduced by 33.3% (DS = 0.167). During the experiments, main attention was paid to the comparison of the boost performances of different qZS-networks in the same operating conditions. Thus, the input voltage, dc-link voltage, and input current were acquired and compared (Fig. 12). It was experimentally veried that, despite the reduced shootthrough duty cycle, the two-stage qZS-network provides the demanded twofold boost of the input voltage, thus ensuring 80 V on the dc link [Fig. 12(b)]. Moreover, it was stated during the experiments that the step-up isolated dc/dc converter with the two-stage qZS-network ensures continuous input current in the shoot-through operating mode. During the second experiment, the shoot-through duty cycle of the dc/dc converter with the two-stage qZS-network was increased by 33.3% (DS = 0.25). Fig. 13(a) shows that, at the input voltage of 40 V and a shoot-through duty cycle of 0.25, the two-stage qZS-network provides a stable threefold boost, thus ensuring around 120 V on the dc link. Fig. 13(b) shows the voltage waveforms of the capacitors of the two-stage qZS-network. It can be seen that, with the same summarized values of the capacitance and shoot-through duty cycle as in the traditional solution, the proposed two-stage qZS-network operates normally without any intolerable voltage ripple. Finally, it is concluded that, for the equal summarized values of passive components, the proposed two-stage qZS-network could provide up to 1.5 times higher boost factor than the traditional qZS-network. VII. R EDUCTION OF C APACITOR VOLTAGES IN THE T WO -S TAGE qZS-N ETWORK The proposed two-stage qZS-network is a nonsymmetrical LC network where the voltage of capacitor C3 is substantially higher than the voltage of capacitor C4 [Fig. 13(b)] VC 3 = VC 4 + VC 1 . (25)

Fig. 14. Isolated step-up dc/dc converter with a modied two-stage qZSnetwork.

The presented modied network has the same advantages as the basic two-stage qZS-network, such as continuous input current and increased boost factor of the input voltage at the same value of the shoot-though duty cycle as the traditional (single-stage) qZS-network. VIII. S OME P RACTICAL D ESIGN I SSUES OF THE N EW S TEP -U P DC/DC C ONVERTER W ITH THE C ASCADED qZS-N ETWORK This section describes the new topology of the FC PCU (Fig. 15). The PCU consists of the proposed isolated stepup dc/dc converter with a modied two-stage qZS-network, a three-phase inverter, and an output LC lter. If demanded, the standard three-phase inverter could be extended to a threephase four-wire inverter by adding an extra arm to the threephase inverter. The presented PCU topology is intended for applications with power ratings up to 50 kW. In this design, the desired dc-link voltage level Vdc of the step-up dc/dc converter (Fig. 15) should correspond to the idle (open cell) voltage of the FC stack, which is 80 V. The FC voltage variation range is 4080 V dc, and the desired output voltage of the step-up dc/dc converter VOUT is 600 V dc, which is typical of a 3 400 Vacrms output. Despite the uctuation of the FC voltage with the load, the output voltage of the step-up dc/dc converter could be kept constant simply by the variation of a shoot-through duty cycle DS VOUT = 2 VIN n 1 1 3DS (29)

By changing the interconnection points of capacitors C2 and C3 , as shown in Fig. 14, the proposed two-stage qZSnetwork could be easily transformed to a symmetrical LC network, which will feature reduced operating voltage of capacitor C3 [7][9]. Moreover, the voltages of capacitors C2 , . . . , C4 will be equalized VC 2 = VC 3 = VC 4 DS = VIN . 1 3DS (26)

The voltage of capacitor C1 remains the same as that for the basic two-stage qZS-network VC 1 = VIN 1 2DS . 1 3DS (27)

In the modied topology (Fig. 14), the peak dc-link voltage is equal to the sum of the voltages of capacitors C1 , C2 , and C4 given by v dc = VC 1 + VC 2 + VC 4 = VIN 1 . 1 3DS (28)

where VIN is the FC voltage and n is the turns ratio of the isolation transformer. For the control of the input voltage gain, a special shootthrough generation method by phase-shift modulation (PSM) was implemented [16]. As seen from Fig. 16, the shoot-through states are generated during zero states. The zero and shootthrough states are spread over the switching period so that the number of higher harmonics in the transformer primary could be reduced. In order to reduce switching losses of the transistors, the number of shoot-through states per period was limited by two. The block diagram of the gating signal generator for the proposed control method is shown in Fig. 15.

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Fig. 15. Power circuit and control system schematics of the proposed PCU for FCs.

Fig. 17. Experimental waveforms of the isolated step-up dc/dc converter: Operations in the (a) non-shoot-through and (b) shoot-through modes.

Fig. 16. states.

Generation of PSM signals with shoot-through states during zero

The active states are controlled by two 180 -phase-shifted PWM signal generators (PWM1 and PWM2) operating with constant frequency. The duty cycle is kept constant nearly 0.5, and only the phase shift is changed. The transistors are driven alternately in pairs (T1 and T4 and then T2 and T3 ). In Fig. 15, the control schematic of the proposed converter is shown. It is important to notice that, due to the voltage doubler, the output voltage does not depend on the active-state duty cycle of the isolation transformer. Therefore, the activestate duty cycle is kept constant at its maximum possible value, ensuring constant voltsecond and ux swing of the isolation transformer. The output voltage directly depends on the dc-link voltage and can be regulated merely by the shoot-through duty cycle. Typically, the converter has to fulll combined regulation requirements, i.e., to provide a stable output voltage under the conditions of changing input voltage and output load. A type-II compensator was used to stabilize the output voltage. The output of the regulator is scaled so that it can be directly

Fig. 18. Experimental waveforms of the PCU in the conditions of (a) constant minimal and (b) varying FC voltages.

used for the shoot-through duty cycle. In order to improve the control system response to input voltage changes, an additional feedforward voltage control loop was added. The idea is to calculate the shoot-through duty cycle in accordance with the input voltage. The transfer function of the converter is known (13). In general, feedforward voltage mode control is inherently stable. The experimental results demonstrate that the proposed converter operates correctly, thus ensuring a ripple-free intermediate dc voltage VOUT in both boundary operating points (Fig. 17). Moreover, it was experimentally conrmed that the proposed PCU ensures stable 3 400 Vacrms 50-Hz output voltage within the predened input voltage and load variation range (Fig. 18).

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IX. C ONCLUSION This paper has presented a further optimization possibility of the voltage-fed qZSI developed by the introduction of the cascaded qZS-network. To compose the cascaded qZS-network, one diode, one inductor, and two capacitors were added to the traditional voltage-fed qZSI. The novel conguration inherits all the advantages of traditional solutions (voltage boost and buck functions in a single stage, continuous input current, and improved reliability). Moreover, the voltage-fed qZSI with the cascaded qZS-network reduced the shoot-through duty cycle by over 30% at the same voltage boost factor and component stresses as the conventional qZSI. The proposed cascaded qZSI can be applied to almost all dc/ac, ac/dc, ac/ac, and dc/dc power conversion schemes. To further decrease the shoot-through duty cycle at the same voltage boost factor, the number of stages of the qZS-network could be increased. The main focus in the practical part was on the PCUs for residential power systems. PCUs are used to interconnect distributed energy sources producing low dc voltage, like FCs or solar panels, to the residential loads. The new dc/dc converter with the cascaded qZS-network was proposed as a front-end step-up dc/dc converter for a PCU. Our research efforts were mostly concentrated on the comparison of boost properties of a traditional (single-stage) and a two-stage qZS-network. It was experimentally proved that, at the equal summarized values of passive components and identical shoot-through duty cycles, the two-stage qZS-network could ensure up to 1.5 times higher input voltage gain. Furthermore, the two-stage qZS-network ensures continuous input current of the converter during the shoot-through operating mode, thus featuring the reduced stress of the input voltage source, which is particularly topical in such demanding applications as power conditioners for FCs and solar panels. R EFERENCES
[1] J. Anderson and F. Z. Peng, Four quasi-Z-source inverters, in Proc. IEEE Power Electron. Spec. Conf., Jun. 1519, 2008, pp. 27432749. [2] Y. Li, J. Anderson, F. Z. Peng, and D. Liu, Quasi-Z-source inverter for photovoltaic power generation systems, in Proc. IEEE APEC, Feb. 1519, 2009, pp. 918924. [3] J.-H. Park, H.-G. Kim, E.-C. Nho, T.-W. Chun, and J. Choi, Gridconnected PV system using a quasi-Z-source inverter, in Proc. IEEE APEC, Feb. 1519, 2009, pp. 925929. [4] D. Vinnikov and I. Roasto, Quasi-Z-source-based isolated dc/dc converters for distributed power generation, IEEE Trans. Ind. Electron., vol. 58, no. 1, pp. 192201, Jan. 2011. [5] R. Strzelecki and M. Adamowicz, Boostbuck inverters with cascaded qZ-type impedance networks, Elect. Rev., vol. 86, no. 2, pp. 370375, 2010. [6] M. Adamowicz, R. Strzelecki, and D. Vinnikov, Cascaded quasiZ-source inverters for renewable energy generation systems, in Proc. Ecologic Vehicles Renew. Energies Conf. (EVER), Monaco, France, Mar. 2528, 2010. [7] D. Vinnikov, I. Roasto, R. Strzelecki, and M. Adamowicz, Performance improvement method for the voltage-fed qZSI with continuous input current, in Proc. 15th IEEE MELECON , Apr. 2628, 2010, pp. 14591464. [8] C. J. Gajanayake, H. B. Gooi, F. L. Luo, P. L. So, L. K. Siow, and Q. N. Vo, Simple modulation and control method for new extended boost quasi Z-source inverters, in Proc. IEEE Region 10 Conf. (TENCON), Jan. 2326, 2009, pp. 16. [9] C. J. Gajanayake, F. L. Luo, H. B. Gooi, P. L. So, and L. K. Siow, Extended-boost Z-source inverters, IEEE Trans. Power Electron., vol. 25, no. 10, pp. 26422652, Oct. 2010.

[10] W.-J. Lee, C.-E. Kim, G.-W. Moon, and S.-K. Han, A new phaseshifted full-bridge converter with voltage-doubler-type rectier for highefciency PDP sustaining power module, IEEE Trans. Ind. Electron., vol. 55, no. 6, pp. 24502458, Jun. 2008. [11] J.-M. Kwon, E.-H. Kim, B.-H. Kwon, and K.-H. Nam, High-efciency fuel cell power conditioning system with input current ripple reduction, IEEE Trans. Ind. Electron., vol. 56, no. 3, pp. 826834, Mar. 2009. [12] J.-J. Lee, J.-M. Kwon, E.-H. Kim, and B.-H. Kwon, Dual series-resonant active-clamp converter, IEEE Trans. Ind. Electron., vol. 55, no. 2, pp. 699710, Feb. 2008. [13] V. Vaisanen, T. Riipinen, and P. Silventoinen, Effects of switching asymmetry on an isolated full-bridge boost converter, IEEE Trans. Power Electron., vol. 25, no. 8, pp. 20332044, Aug. 2010. [14] D. Vinnikov, I. Roasto, R. Strzelecki, and M. Adamowicz, CCM and DCM operation analysis of cascaded quasi-Z-source inverter, in Proc. IEEE ISIE, Jun. 2730, 2011, pp. 159164. [15] D. Vinnikov, I. Roasto, R. Strzelecki, and M. Adamowicz, Two-stage quasi-Z-source network based step-up DC/DC converter, in Proc. IEEE ISIE, Jul. 47, 2010, pp. 11431148. [16] I. Roasto and D. Vinnikov, Analysis and evaluation of PWM and PSM shoot-through control methods for voltage-fed qZSI based DC/DC converters, in Proc. 14th Int. EPE-PEMC, Sep. 68, 2010, pp. T3-100T3-105.

Dmitri Vinnikov (M07SM11) received the Dipl.Eng., M.Sc., and Dr.Sc.Techn. degrees in electrical engineering from Tallinn University of Technology, Tallinn, Estonia, in 1999, 2001, and 2005, respectively. He is currently the Head of the Power Electronics Research Group, Department of Electrical Drives and Power Electronics, Tallinn University of Technology. He has authored more than 100 published papers on power converter design and development and is the holder of several patents and utility models in this application eld. His research interests include switch-mode power converters, modeling and simulation of power systems, applied design of power converters and control systems, and application and development of energystorage systems.

Indrek Roasto (M10) received the B.Sc. and M.Sc. degrees in electrical engineering from Tallinn University of Technology, Tallinn, Estonia, in 2003 and 2005, respectively, and the Ph.D. degree from Tallinn University of Technology, Tallinn, Estonia, in 2009, with a thesis devoted to the research and development of smart control and protection systems for high-voltage high-power galvanically isolated dc/dc converters. He is currently a Senior Researcher with the Department of Electrical Drives and Power Electronics, Tallinn University of Technology. He has over 40 publications and is the holder of ve utility models and one patent in the eld of power electronics. His research interests are in digital control of switching power converters, including modeling, design, and simulation.

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 10, OCTOBER 2012

Ryszard Strzelecki (M97SM07) was born in Bydgoszcz, Poland. He received the M.Sc. (with honors) and Ph.D. degrees in electronic engineering from the Department of Industrial Electronics, National Technical University of Ukraine Kyiv Polytechnic Institute, Kyiv, Ukraine, in 1981 and 1984, respectively, and the Dr.Sc. degree in electrical engineering from the Institute of Electrodynamics, The National Academy of Sciences of Ukraine, Kyiv, in 1991. From 1996 to 2003, he was the Director of the Institute of Electrical Engineering, University of Zielona Gra, Zielona Gra, Poland. He is currently a Full Professor with the Power Electronics Laboratories, Electrotechnical Institute, Warsaw-Mi edzylesie, Poland, and Gdynia Maritime University, Gdynia, Poland. His research activity is centered on the topology, control, and industry application of power electronic conditioners, particularly for power quality enhancement and power ow control on distributed electrical networks. He is the author of numerous technical papers and six books and monographs and the holder of six patents. He is a Member of the Editorial Boards of the journals Electrical Power Quality and Utilization and Przegla d Elektrotechniczny (Electrical Review). Dr. Strzelecki is the Chair of the Power Electronics Committee of the Association of Polish Electrical Engineers. He is the Founder and currently a Cochairman of the IEEE Conference-Workshop Compatibility and Power Electronics.

Marek Adamowicz (M11) received the M.Sc.E.E. and Ph.D. degrees (with honors) in electrical engineering from the Faculty of Electrical and Control Engineering, Gdansk University of Technology, Gdansk, Poland, in 2001 and 2008, respectively. From 2005 to 2011, he was an Assistant Professor with Gdynia Maritime University, Gdynia, Poland. He is currently with the Department of Mechatronics and High Voltage Engineering, Gdansk University of Technology. He is the Head of the young scientists team LIDER supported by the Polish National Centre for Research and Development. He is the author of over 40 technical papers. He is the holder of one patent. His current research interests include new topologies of power converters for smart grids, SiC devices, and gate driver circuits, control of small wind energy generation systems, and sensorless control of induction motor drives. Dr. Adamowicz is a member of the Technical Program Committee of the IEEE Conference-Workshop Compatibility and Power Electronics.