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Contents:
Introduction Block Diagram and Pin Description of the 8051 Registers Some Simple Instructions Structure of Assembly language and Running an 8051 program Memory mapping in 8051 8051 Flag bits and the PSW register Addressing Modes 16-bit, BCD and Signed Arithmetic in 8051 Stack in the 8051 LOOP and JUMP Instructions CALL Instructions I/O Port Programming
Introduction
General-purpose microprocessor
CPU for Computers No RAM, ROM, I/O on CPU chip itself ExampleIntels x86, Motorolas 680x0
Data Bus
RAM
ROM
I/O Port
Timer
Microcontroller :
A smaller computer On-chip RAM, ROM, I/O ports... ExampleMotorolas 6811, Intels 8051, Zilogs Z8 and PIC 16X
RAM ROM
A single chip
Serial Timer COM Port Microcontroller
Embedded System
Embedded system means the processor is embedded into that application. An embedded product uses a microprocessor or microcontroller to do one task only. In an embedded system, there is only one application software that is typically burned into ROM. Exampleprinter, keyboard, video game player
Block Diagram
External interrupts Interrupt Control On-chip ROM for program code
Timer/Counter
On-chip RAM
Timer 1 Timer 0
Counter Inputs
OSC
Bus Control
4 I/O Ports
P0 P1 P2 P3
TxD RxD
Address/Data
Feature 8051 ROM (program space in bytes) 4K RAM (bytes) 128 Timers 2 I/O pins 32 Serial port 1 Interrupt sources 6
8052 8K 256 3 32 1 8
8031 0K 128 2 32 1 6
8051 (8031)
Pins of 80511/4
Vccpin 40 Vcc provides supply voltage to the chip. The voltage source is +5V. GNDpin 20ground XTAL1 and XTAL2pins 19,18 These 2 pins provide external clock. Way 1using a quartz crystal oscillator Way 2using a TTL oscillator Example 4-1 shows the relationship between XTAL and the machine cycle.
Pins of 80512/4
RSTpin 9reset It is an input pin and is active highnormally low. The high pulse must be high at least 2 machine cycles. It is a power-on reset. Upon applying a high pulse to RST, the microcontroller will reset and all values in registers will be lost. Reset values of some 8051 registers Way 1Power-on reset circuit Way 2Power-on reset with debounce
Pins of 80513/4
/EApin 31external access There is no on-chip ROM in 8031 and 8032 . The /EA pin is connected to GND to indicate the code is stored externally. /PSEN ALE are used for external ROM. For 8051, /EA pin is connected to Vcc. / means active low. /PSENpin 29program store enable This is an output pin and is connected to the OE pin of the ROM. See Chapter 14.
Pins of 80514/4
ALEpin 30address latch enable It is an output pin and is active high. 8051 port 0 provides both address and data. The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch. I/O port pins The four ports P0, P1, P2, and P3. Each port uses 8 pins. All I/O pins are bi-directional.
Using a quartz crystal oscillator We can observe the frequency on the XTAL2 pin. C2 XTAL2 30pF C1 XTAL1 30pF GND
XTAL2
XTAL1
GND
Example :
Find the machine cycle for (a) XTAL = 11.0592 MHz (b) XTAL = 16 MHz. Solution: (a) 11.0592 MHz / 12 = 921.6 kHz; machine cycle = 1 / 921.6 kHz = 1.085 s (b) 16 MHz / 12 = 1.333 MHz; machine cycle = 1 / 1.333 MHz = 0.75 s
9 RST
31 10 uF 30 pF
EA/VPP X1
X2 RST 9 8.2 K
The 8051 has four I/O ports Port 0 pins 32-39P0P0.0P0.7 Port 1pins 1-8 P1P1.0P1.7 Port 2pins 21-28P2P2.0P2.7 Port 3pins 10-17P3P3.0P3.7 Each port has 8 pins. Named P0.X X=0,1,...,7, P1.X, P2.X, P3.X ExP0.0 is the bit 0LSBof P0 ExP0.7 is the bit 7MSBof P0 These 8 bits form a byte. Each port can be used as input or output (bi-direction).
Registers
A B R0 R1 R2 R3 R4 R5 R6 R7 Some 8-bitt Registers of the 8051 Some 8051 16-bit Register PC PC DPTR DPH DPL
; dest = source
;A=72H ;A=r OR 72H ;R4=62H ;B=the content of F9th byte of RAM
ADD A, Source
;A=A+SOURCE
SETB CLR
SETB SETB SETB SETB SETB
Note:
bit bit
C P0.0 P3.7 ACC.2 05
; bit=1 ; bit=0
; CY=1 ;bit 0 from port 0 =1 ;bit 7 from port 3 =1 ;bit 2 from ACCUMULATOR =1 ;set high D5 of RAM loc. 20h
Bit Addressable Page 359,360
CLR instruction is as same as SETB i.e: CLR C ;CY=0 But following instruction is only for CLR: CLR A ;A=0
SUBB
SETB C SUBB A,R5
A,source ;A=A-source-CY
;CY=1 ;A=A-R5-1
ADC
SETB C ADC
A,source ;A=A+source+CY
;CY=1 A,R5 ;A=A+R5+1
DEC INC
INC DEC DEC
byte byte
R7 A 40H
;byte=byte-1 ;byte=byte+1
; [40]=[40]-1
CPL
Example: L01: MOV CPL MOV ACALL SJMP
;1s complement
A,#55H ;A=01010101 B A P1,A DELAY L01
CALL
ANL - ORL - XRL EXAMPLE: MOV R5,#89H ANL R5,#08H RR RL RRC RLC A EXAMPLE:
RR A
Myfile.asm ASSEMBLER PROGRAM Myfile.lst Myfile.obj LINKER PROGRAM Other obj file
8k
0000H
32k
30H 2FH Bit-Addressable RAM 20H 1FH 18H 17H 10H 0FH 08H 07H 00H Register Bank 3 Register Bank 2 (Stack) Register Bank 1
Register Bank 0
Carry flag Auxiliary carry flag Available to the user for general purpose Register Bank selector bit 1 Register Bank selector bit 0 Overflow flag User define bit Parity flag Set/Reset odd/even parity
CY AC -RS1 RS0 OV -P
RS1 0 0 1 1
RS0 0 1 0 1
Register Bank 0 1 2 3
Note: X can be 0 or 1
Example: MOV A,#88H ADD A,#93H 88 +93 ---11B CY=1 AC=0 10001000 +10010011 -------------00011011 P=0
Example: MOV A,#9CH ADD A,#64H 9C +64 ---100 CY=1 AC=1 10011100 +01100100 -------------00000000 P=0
Example: MOV A,#38H ADD A,#2FH 38 +2F ---67 CY=0 AC=1 00111000 +00101111 -------------01100111 P=1
Addressing Modes
Immediate Register Direct Register Indirect Indexed
In other word, the content of register R0 or R1 is sources or target in MOV, ADD and SUBB insructions. Example: Write a program to copy a block of 10 bytes from RAM location sterting at 37h to RAM location starting at 59h. Solution: MOV R0,37h MOV R1,59h MOV R2,10 L1: MOV A,@R0 MOV @R1,A INC R0 INC R1 DJNZ R2,L1 ; source pointer ; dest pointer ; counter
jump
Example: Assuming that ROM space starting at 250h contains Hello., write a program to transfer the bytes into RAM locations starting at 40h. Solution: ORG 0 MOV DPTR,#MYDATA MOV R0,#40H L1: CLR A MOVC A,@A+DPTR JZ L2 MOV @R0,A INC DPTR INC R0 SJMP L1 L2: SJMP L2 ;------------------------------------ORG 250H MYDATA: DB Hello,0 END Notice the NULL character ,0, as end of string and how we use the JZ instruction to detect that.
Example: Write a program to get the x value from P1 and send x2 to P2, continuously . Solution: ORG 0 MOV DPTR, #TAB1 MOV A,#0FFH MOV P1,A L01: MOV A,P1 MOVC A,@A+DPTR MOV P2,A SJMP L01 ;---------------------------------------------------ORG 300H TAB1: DB 0,1,4,9,16,25,36,49,64,81 END
;A=2, B=5
Example: MOV MOV MOV PUSH PUSH PUSH R6,#25H R1,#12H R4,#0F3H 6 1 4
SP=08H
SP=09H
SP=08H
SJMP and LJMP: LJMP(long jump) LJMP is an unconditional jump. It is a 3-byte instruction in which the first byte is the opcode, and the second and third bytes represent the 16-bit address of the target location. The 20byte target address allows a jump to any memory location from 0000 to FFFFH. SJMP(short jump) In this 2-byte instruction. The first byte is the opcode and the second byte is the relative address of the target location. The relative address range of 00-FFH is divided into forward and backward jumps, that is , within -128 to +127 bytes of memory relative to the address of the current PC.
CJNE , JNC
Exercise: Write a program that compare R0,R1. If R0>R1 then send 1 to port 2, else if R0<R1 then send 0FFh to port 2, else send 0 to port 2.
CALL Instructions
Another control transfer instruction is the CALL instruction, which is used to call a subroutine. LCALL(long call) In this 3-byte instruction, the first byte is the opcode an the second and third bytes are used for the address of target subroutine. Therefore, LCALL can be used to call subroutines located anywhere within the 64K byte address space of the 8051.
Port 1 is denoted by P1. P1.0 ~ P1.7 We use P1 as examples to show the operations on ports. P1 as an output port (i.e., write CPU data to the external pin) P1 as an input port (i.e., read pin data into CPU bus)
A Pin of Port 1
Read latch TB2 Vcc Load(L1) Internal CPU bus Write to latch
D Clk Q Q
P1.X M1
P1.X pin
P0.x
8051 IC
Tri-state Buffer
Output Input
Low
Highimpedance (open-circuit)
BACK:
BACK:
Description Bring into A the data at P2 pins Jump if pin P2.1 is low Jump if pin P1.3 is high Copy status of pin P2.4 to CY
Read-Modify-Write Instructions
Mnemonics ANL ORL XRL JBC PX.Y, TARGET CPL INC DEC DJNZ PX, TARGET MOV PX.Y,C CLR PX.Y SETB PX.Y Example ANL P1,A ORL P1,A XRL P1,A JBC P1.1, TARGET CPL P1.2 INC P1 DEC P1 DJNZ P1,TARGET MOV P1.2,C CLR P1.3 SETB P1.4
10 K
P0.0 DS5000 P0.1 P0.2 8751 P0.3 P0.4 8951 P0.5 P0.6 P0.7
Port 0
74LS373
PSEN ALE P0.0 P0.7 OE OC A0 A7
G D
74LS373
D0 EA P2.0 P2.7 D7
A8 A15
8051
ROM
A7
A8 A12
8051
ROM
74LS373
OE OC A0 A7
Address
8051
ROM
ALE Pin
The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.
When ALE=0, P0 provides data D0-D7. When ALE=1, P0 provides address A0-A7. The reason is to allow P0 to multiplex address and data.