Colour Television

Chassis

L11M1.1L
LA

19130_000_110421.eps 110421

Contents
1. 2. 3. 4. 5. 6. 7. 8. 9. 2 2 4 8 12 18 20 26 35 36 37 38 39 40 41 42 43 45 46 50 52 56 57 59 65 66 67 Revision List Technical Specifications and Connections Precautions, Notes, and Abbreviation List Mechanical Instructions Service Modes, Error Codes, and Fault Finding Alignments Circuit Descriptions IC Data Sheets Block Diagrams Wiring Diagram 32" (Thriller) Wiring Diagram 40" (Thriller) Block Diagram Video Block Diagram Audio Block Diagram Control & Clock Signals Block Diagram I2C Supply Lines Overview 10. Circuit Diagrams and PWB Layouts B01 393912365052 B02 393912365052 B03 393912365052 B04 393912365052 B05 393912365052 B06 393912365052 B07 393912365052 313912365052 SSB Layout T01 393912365071 313912365071 TCON Layout 11. Styling Sheets Styling Sheet Thriller 32" Styling Sheet Thriller 40"

Page

Copyright 2011 Koninklijke Philips Electronics N.V. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical, photocopying, or otherwise without the prior permission of Philips.

Published by ER/JY 1164 BU TV Consumer Care

Printed in the Netherlands

Subject to modification

EN 3122 785 19130 2011-Apr-29

EN 2

1.

L11M1.1L LA

Revision List

1. Revision List
Manual xxxx xxx xxxx.0 First release.

2. Technical Specifications and Connections

Table 2-1 Described Model numbers CTN 32PFL3606D/78 Thriller 40PFL3606D/78 Styling Published in: 3122 785 19130 Index of this chapter: 2.1 Technical Specifications 2.2 Directions for Use 2.3 Connections Notes: Figures can deviate due to the different set executions. Specifications are indicative (subject to change).

2.2

Directions for Use

You can download this information from the following websites: http://www.philips.com/support http://www.p4c.philips.com

2.1
For on-line product support please use the links in Table 2-1. Here is product information available, as well as getting started, user manuals, frequently asked questions and software & drivers.

Technical Specifications

2.3

Connections

REAR CONNECTORS
CVI 1 DIGITAL AUDIO OUT SERV.U AUDIO IN DVI/VGA

SIDE CONNECTORS

Pr

Pb

1 4 5 6 7

BOTTOM REAR CONNECTORS

8 9 10 11

3
R L Pr CVI 2 Pb Y HDMI 1 (ARC) VGA ANTENNA
19130_001_110421.eps 110421

Figure 2-1 Connection overview Note: The following connector colour abbreviations are used (according to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy= Grey, Rd= Red, Wh= White, Ye= Yellow. 2.3.1 Side Connections 1 - USB2.0
1 2 3 4 10000_022_090121.eps 090121

Figure 2-2 USB (type A)

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Technical Specifications and Connections L11M1.1L LA 2.

9 - HDMI1: Digital Video, Digital Audio - In
19 18 1 2

EN 3

1 2 3 4 Gnd
10000_017_090121.eps 090428

- +5V - Data (-) - Data (+) - Ground

k jk jk H

2 - AV IN: Cinch: Video CVBS - In, Audio - In Ye - Video CVBS 1 VPP / 75 ohm Wh - Audio L 0.5 VRMS / 10 kohm Rd - Audio R 0.5 VRMS / 10 kohm jq jq jq 3 - HDMI: Digital Video, Digital Audio - In
19 18 1 2

Figure 2-4 HDMI (type A) connector

10000_017_090121.eps 090428

Figure 2-3 HDMI (type A) connector

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 10 - Aerial - In - - F-type

- D2+ - Shield - D2- D1+ - Shield - D1- D0+ - Shield - D0- CLK+ - Shield - CLK- Easylink - ARC - DDC_SCL - DDC_SDA - Ground - +5V - HPD - Ground

Data channel Gnd Data channel Data channel Gnd Data channel Data channel Gnd Data channel Data channel Gnd Data channel Control channel/CEC Audio Return Channel DDC clock DDC data Gnd Hot Plug Detect Gnd

j H j j H j j H j j H j jk j j jk H j j H

Data channel Gnd Data channel Data channel Gnd Data channel Data channel Gnd Data channel Data channel Gnd Data channel Control channel/CEC

j H j j H j j H j j H j jk

Coax, 75 11 - VGA: Video RGB - In

1 6 11 5 10 15

DDC clock DDC data Gnd Hot Plug Detect Gnd

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 j jk H j j H 2.3.2 Rear Connections

- D2+ - Shield - D2- D1+ - Shield - D1- D0+ - Shield - D0- CLK+ - Shield - CLK- Easylink - n.c. - DDC_SCL - DDC_SDA - Ground - +5V - HPD - Ground

10000_002_090121.eps 090127

Figure 2-5 VGA Connector 0.7 VPP / 75 0.7 VPP / 75 0.7 VPP / 75 jq jq jq jq jq Gnd Gnd Gnd Gnd +5 V Gnd 5 - Cinch: Digital Audio - Out Bk - Coaxial 0.4 - 0.6VPP / 75 ohm 6 - Service Connector (UART) 1 - Ground Gnd 2 - UART_TX Transmit 3 - UART_RX Receive kq DDC data 0-5V 0-5V DDC clock H k j 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 4 - CVI-1: Cinch: Video YPbPr - In, Audio - In Wh - Audio - L 0.5 VRMS / 10 k Rd - Audio - R 0.5 VRMS / 10 k Rd - Video Pr 0.7 VPP / 75 Bu - Video Pb 0.7 VPP / 75 Gn - Video Y 1 VPP / 75 - Video Red - Video Green - Video Blue - n.c. - Ground - Ground Red - Ground Green - Ground Blue - +5VDC - Ground Sync - n.c. - DDC_SDA - H-sync - V-sync - DDC_SCL j j j H H H H j H j j j j

7 - Mini Jack: Audio - In DVI/VGA Bk - Audio 0.5 VRMS / 10 k 2.3.3 Bottom Connections

jo

8 - CVI-2: Cinch: Video YPbPr - In, Audio - In Wh - Audio - L 0.5 VRMS / 10 k Rd - Audio - R 0.5 VRMS / 10 k Rd - Video Pr 0.7 VPP / 75 Bu - Video Pb 0.7 VPP / 75 Gn - Video Y 1 VPP / 75

jq jq jq jq jq

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EN 4

3.

L11M1.1L LA

Precautions, Notes, and Abbreviation List

3. Precautions, Notes, and Abbreviation List

Index of this chapter: 3.1 Safety Instructions 3.2 Warnings 3.3 Notes 3.4 Abbreviation List Where necessary, measure the waveforms and voltages with (D) and without (E) aerial signal. Measure the voltages in the power supply section both in normal operation (G) and in stand-by (F). These values are indicated by means of the appropriate symbols.

3.1

Safety Instructions

3.3.2

Schematic Notes

Safety regulations require the following during a repair: Connect the set to the Mains/AC Power via an isolation transformer (> 800 VA). Replace safety components, indicated by the symbol h, only by components identical to the original ones. Any other component substitution (other than original type) may increase risk of fire or electrical shock hazard.

All resistor values are in ohms, and the value multiplier is often used to indicate the decimal point location (e.g. 2K2 indicates 2.2 k). Resistor values with no multiplier may be indicated with either an E or an R (e.g. 220E or 220R indicates 220 ). All capacitor values are given in micro-farads ( = 10-6), nano-farads (n = 10-9), or pico-farads (p = 10-12). Capacitor values may also use the value multiplier as the decimal point indication (e.g. 2p2 indicates 2.2 pF). An asterisk (*) indicates component usage varies. Refer to the diversity tables for the correct values. The correct component values are listed on the Philips Spare Parts Web Portal. Spare Parts For the latest spare part overview, consult your Philips Spare Part web portal.

3.3.3

3.3.4

BGA (Ball Grid Array) ICs Introduction For more information on how to handle BGA devices, visit this URL: http://www.atyourservice-magazine.com. Select Magazine, then go to Repair downloads. Here you will find Information on how to deal with BGA-ICs. BGA Temperature Profiles For BGA-ICs, you must use the correct temperature-profile. Where applicable and available, this profile is added to the IC Data Sheet information section in this manual. 3.3.5 Lead-free Soldering

Safety regulations require that after a repair, the set must be returned in its original condition. Pay in particular attention to the following points: Route the wire trees correctly and fix them with the mounted cable clamps. Check the insulation of the Mains/AC Power lead for external damage. Check the strain relief of the Mains/AC Power cord for proper function. Check the electrical DC resistance between the Mains/AC Power plug and the secondary side (only for sets that have a Mains/AC Power isolated power supply): 1. Unplug the Mains/AC Power cord and connect a wire between the two pins of the Mains/AC Power plug. 2. Set the Mains/AC Power switch to the on position (keep the Mains/AC Power cord unplugged!). 3. Measure the resistance value between the pins of the Mains/AC Power plug and the metal shielding of the tuner or the aerial connection on the set. The reading should be between 4.5 M and 12 M. 4. Switch off the set, and remove the wire between the two pins of the Mains/AC Power plug. Check the cabinet for defects, to prevent touching of any inner parts by the customer.

3.2

Warnings

All ICs and many other semiconductors are susceptible to electrostatic discharges (ESD w). Careless handling during repair can reduce life drastically. Make sure that, during repair, you are connected with the same potential as the mass of the set by a wristband with resistance. Keep components and tools also at this same potential. Be careful during measurements in the high voltage section. Never replace modules or other components while the unit is switched on. When you align the set, use plastic rather than metal tools. This will prevent any short circuits and the danger of a circuit becoming unstable.

3.3
3.3.1

Notes
General

Due to lead-free technology some rules have to be respected by the workshop during a repair: Use only lead-free soldering tin. If lead-free solder paste is required, please contact the manufacturer of your soldering equipment. In general, use of solder paste within workshops should be avoided because paste is not easy to store and to handle. Use only adequate solder tools applicable for lead-free soldering tin. The solder tool must be able: To reach a solder-tip temperature of at least 400C. To stabilize the adjusted temperature at the solder-tip. To exchange solder-tips for different applications. Adjust your solder tool so that a temperature of around 360C - 380C is reached and stabilized at the solder joint. Heating time of the solder-joint should not exceed ~ 4 sec. Avoid temperatures above 400C, otherwise wear-out of tips will increase drastically and flux-fluid will be destroyed. To avoid wear-out of tips, switch off unused equipment or reduce heat. Mix of lead-free soldering tin/parts with leaded soldering tin/parts is possible but PHILIPS recommends strongly to avoid mixed regimes. If this cannot be avoided, carefully clear the solder-joint from old tin and re-solder with new tin. Measure the voltages and waveforms with regard to the chassis (= tuner) ground (H), or hot ground (I), depending on the tested area of circuitry. The voltages and waveforms shown in the diagrams are indicative. Measure them in the Service Default Mode with a colour bar signal and stereo sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and picture carrier at 475.25 MHz for PAL, or 61.25 MHz for NTSC (channel 3).
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3.3.6

Alternative BOM identification It should be noted that on the European Service website, Alternative BOM is referred to as Design variant.

Precautions, Notes, and Abbreviation List L11M1.1L LA 3.

EN 5

powered TV set, it is best to test the high voltage insulation. It is easy to do, and is a good service precaution.

3.4
0/6/12

Abbreviation List

AARA

ACI

The third digit in the serial number (example: AG2B0335000001) indicates the number of the alternative B.O.M. (Bill Of Materials) that has been used for producing the specific TV set. In general, it is possible that the same TV model on the market is produced with e.g. two different types of displays, coming from two different suppliers. This will then result in sets which have the same CTN (Commercial Type Number; e.g. 28PW9515/12) but which have a different B.O.M. number. By looking at the third digit of the serial number, one can identify which B.O.M. is used for the TV set he is working with. If the third digit of the serial number contains the number 1 (example: AG1B033500001), then the TV set has been manufactured according to B.O.M. number 1. If the third digit is a 2 (example: AG2B0335000001), then the set has been produced according to B.O.M. no. 2. This is important for ordering the correct spare parts! For the third digit, the numbers 1...9 and the characters A...Z can be used, so in total: 9 plus 26= 35 different B.O.M.s can be indicated by the third digit of the serial number. ADC AFC

Identification: The bottom line of a type plate gives a 14-digit serial number. Digits 1 and 2 refer to the production centre (e.g. SN is Lysomice, RJ is Kobierzyce), digit 3 refers to the B.O.M. code, digit 4 refers to the Service version change code, digits 5 and 6 refer to the production year, and digits 7 and 8 refer to production week (in example below it is 2010 week 10 / 2010 week 17). The 6 last digits contain the serial number.

AGC

AM AP AR ASF

ATSC

ATV Auto TV

AV AVC AVIP B/G BDS BLR BTSC

10000_053_110228.eps 110228

Figure 3-1 Serial number (example) 3.3.7 Board Level Repair (BLR) or Component Level Repair (CLR) If a board is defective, consult your repair procedure to decide if the board has to be exchanged or if it should be repaired on component level. If your repair procedure says the board should be exchanged completely, do not solder on the defective board. Otherwise, it cannot be returned to the O.E.M. supplier for back charging! 3.3.8 Practical Service Precautions

B-TXT C CEC

CL CLR ComPair CP CSM CTI

CVBS DAC DBE DCM It makes sense to avoid exposure to electrical shock. While some sources are expected to have a possible dangerous impact, others of quite high potential are of limited current and are sometimes held in less regard. Always respect voltages. While some may not be dangerous in themselves, they can cause unexpected reactions that are best avoided. Before reaching into a

DDC

SCART switch control signal on A/V board. 0 = loop through (AUX to TV), 6 = play 16 : 9 format, 12 = play 4 : 3 format Automatic Aspect Ratio Adaptation: algorithm that adapts aspect ratio to remove horizontal black bars; keeps the original aspect ratio Automatic Channel Installation: algorithm that installs TV channels directly from a cable network by means of a predefined TXT page Analogue to Digital Converter Automatic Frequency Control: control signal used to tune to the correct frequency Automatic Gain Control: algorithm that controls the video input of the feature box Amplitude Modulation Asia Pacific Aspect Ratio: 4 by 3 or 16 by 9 Auto Screen Fit: algorithm that adapts aspect ratio to remove horizontal black bars without discarding video information Advanced Television Systems Committee, the digital TV standard in the USA See Auto TV A hardware and software control system that measures picture content, and adapts image parameters in a dynamic way External Audio Video Audio Video Controller Audio Video Input Processor Monochrome TV system. Sound carrier distance is 5.5 MHz Business Display Solutions (iTV) Board-Level Repair Broadcast Television Standard Committee. Multiplex FM stereo sound system, originating from the USA and used e.g. in LATAM and AP-NTSC countries Blue TeleteXT Centre channel (audio) Consumer Electronics Control bus: remote control bus on HDMI connections Constant Level: audio output to connect with an external amplifier Component Level Repair Computer aided rePair Connected Planet / Copy Protection Customer Service Mode Color Transient Improvement: manipulates steepness of chroma transients Composite Video Blanking and Synchronization Digital to Analogue Converter Dynamic Bass Enhancement: extra low frequency amplification Data Communication Module. Also referred to as System Card or Smartcard (for iTV). See E-DDC
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EN 6
D/K DFI DFU DMR DMSD DNM DNR DRAM DRM DSP DST iTV LS

3.

L11M1.1L LA

Precautions, Notes, and Abbreviation List

DTCP

DVB-C DVB-T DVD DVI(-d) E-DDC

LATAM LCD LED L/L'

EDID EEPROM EMI EPG EPLD EU EXT FDS FDW FLASH FM

LPL LS LVDS Mbps M/N MHEG

MIPS

MOP MOSFET MPEG MPIF MUTE MTV NC NICAM

FPGA FTV Gb/s G-TXT H HD HDD HDCP

NTC NTSC

NVM HDMI HP I O/C OSD OAD

OTC P50

I2 C I2 D I2 S IF IR IRQ ITU-656

Monochrome TV system. Sound carrier distance is 6.5 MHz Dynamic Frame Insertion Directions For Use: owner's manual Digital Media Reader: card reader Digital Multi Standard Decoding Digital Natural Motion Digital Noise Reduction: noise reduction feature of the set Dynamic RAM Digital Rights Management Digital Signal Processing Dealer Service Tool: special remote control designed for service technicians Digital Transmission Content Protection; A protocol for protecting digital audio/video content that is traversing a high speed serial bus, such as IEEE-1394 Digital Video Broadcast - Cable Digital Video Broadcast - Terrestrial Digital Versatile Disc Digital Visual Interface (d= digital only) Enhanced Display Data Channel (VESA standard for communication channel and display). Using E-DDC, the video source can read the EDID information form the display. Extended Display Identification Data (VESA standard) Electrically Erasable and Programmable Read Only Memory Electro Magnetic Interference Electronic Program Guide Erasable Programmable Logic Device Europe EXTernal (source), entering the set by SCART or by cinches (jacks) Full Dual Screen (same as FDW) Full Dual Window (same as FDS) FLASH memory Field Memory or Frequency Modulation Field-Programmable Gate Array Flat TeleVision Giga bits per second Green TeleteXT H_sync to the module High Definition Hard Disk Drive High-bandwidth Digital Content Protection: A key encoded into the HDMI/DVI signal that prevents video data piracy. If a source is HDCP coded and connected via HDMI/DVI without the proper HDCP decoding, the picture is put into a snow vision mode or changed to a low resolution. For normal content distribution the source and the display device must be enabled for HDCP software key decoding. High Definition Multimedia Interface HeadPhone Monochrome TV system. Sound carrier distance is 6.0 MHz Inter IC bus Inter IC Data bus Inter IC Sound bus Intermediate Frequency Infra Red Interrupt Request The ITU Radio communication Sector (ITU-R) is a standards body subcommittee of the International Telecommunication Union relating to radio communication. ITU-656 (a.k.a. SDI), is a digitized video format used for broadcast grade video. Uncompressed digital component or digital composite signals can be used. The SDI signal is self-synchronizing, uses 8 bit or 10 bit data words, and has a maximum data rate of 270 Mbit/s, with a minimum bandwidth of 135 MHz. Institutional TeleVision; TV sets for hotels, hospitals etc. Last Status; The settings last chosen by the customer and read and stored in RAM or in the NVM. They are called at start-up of the set to configure it according to the customer's preferences Latin America Liquid Crystal Display Light Emitting Diode Monochrome TV system. Sound carrier distance is 6.5 MHz. L' is Band I, L is all bands except for Band I LG.Philips LCD (supplier) Loudspeaker Low Voltage Differential Signalling Mega bits per second Monochrome TV system. Sound carrier distance is 4.5 MHz Part of a set of international standards related to the presentation of multimedia information, standardised by the Multimedia and Hypermedia Experts Group. It is commonly used as a language to describe interactive television services Microprocessor without Interlocked Pipeline-Stages; A RISC-based microprocessor Matrix Output Processor Metal Oxide Silicon Field Effect Transistor, switching device Motion Pictures Experts Group Multi Platform InterFace MUTE Line Mainstream TV: TV-mode with Consumer TV features enabled (iTV) Not Connected Near Instantaneous Compounded Audio Multiplexing. This is a digital sound system, mainly used in Europe. Negative Temperature Coefficient, non-linear resistor National Television Standard Committee. Color system mainly used in North America and Japan. Color carrier NTSC M/N= 3.579545 MHz, NTSC 4.43= 4.433619 MHz (this is a VCR norm, it is not transmitted off-air) Non-Volatile Memory: IC containing TV related data such as alignments Open Circuit On Screen Display Over the Air Download. Method of software upgrade via RF transmission. Upgrade software is broadcasted in TS with TV channels. On screen display Teletext and Control; also called Artistic (SAA5800) Project 50: communication protocol between TV and peripherals
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Precautions, Notes, and Abbreviation List L11M1.1L LA 3.

PAL SSC STB STBY SVGA SVHS SW SWAN

EN 7

PCB PCM PDP PFC PIP PLL SXGA TFT THD TMDS

POD

POR PSDL PSL PSLS

TS TXT TXT-DW UI uP UXGA V VESA VGA VL VSB WYSIWYR

PTC PWB PWM QRC QTNR QVCP RAM RGB

WXGA XTAL XGA Y Y/C YPbPr

RC RC5 / RC6 RESET ROM RSDS R-TXT SAM S/C SCART

YUV

Spread Spectrum Clocking, used to reduce the effects of EMI Set Top Box STand-BY 800 600 (4:3) Super Video Home System Software Spatial temporal Weighted Averaging Noise reduction 1280 1024 Thin Film Transistor Total Harmonic Distortion Transmission Minimized Differential Signalling Transport Stream TeleteXT Dual Window with TeleteXT User Interface Microprocessor 1600 1200 (4:3) V-sync to the module Video Electronics Standards Association 640 480 (4:3) Variable Level out: processed audio output toward external amplifier Vestigial Side Band; modulation method What You See Is What You Record: record selection that follows main picture and sound 1280 768 (15:9) Quartz crystal 1024 768 (4:3) Luminance signal Luminance (Y) and Chrominance (C) signal Component video. Luminance and scaled color difference signals (B-Y and R-Y) Component video

SCL SCL-F SD SDA SDA-F SDI SDRAM SECAM

SIF SMPS SoC SOG SOPS SPI

S/PDIF SRAM SRP SSB

Phase Alternating Line. Color system mainly used in West Europe (colour carrier = 4.433619 MHz) and South America (colour carrier PAL M = 3.575612 MHz and PAL N = 3.582056 MHz) Printed Circuit Board (same as PWB) Pulse Code Modulation Plasma Display Panel Power Factor Corrector (or Preconditioner) Picture In Picture Phase Locked Loop. Used for e.g. FST tuning systems. The customer can give directly the desired frequency Point Of Deployment: a removable CAM module, implementing the CA system for a host (e.g. a TV-set) Power On Reset, signal to reset the uP Power Supply for Direct view LED backlight with 2D-dimming Power Supply with integrated LED drivers Power Supply with integrated LED drivers with added Scanning functionality Positive Temperature Coefficient, non-linear resistor Printed Wiring Board (same as PCB) Pulse Width Modulation Quasi Resonant Converter Quality Temporal Noise Reduction Quality Video Composition Processor Random Access Memory Red, Green, and Blue. The primary color signals for TV. By mixing levels of R, G, and B, all colors (Y/C) are reproduced. Remote Control Signal protocol from the remote control receiver RESET signal Read Only Memory Reduced Swing Differential Signalling data interface Red TeleteXT Service Alignment Mode Short Circuit Syndicat des Constructeurs d'Appareils Radiorcepteurs et Tlviseurs Serial Clock I2C CLock Signal on Fast I2C bus Standard Definition Serial Data I2C DAta Signal on Fast I2C bus Serial Digital Interface, see ITU-656 Synchronous DRAM SEequence Couleur Avec Mmoire. Colour system mainly used in France and East Europe. Colour carriers = 4.406250 MHz and 4.250000 MHz Sound Intermediate Frequency Switched Mode Power Supply System on Chip Sync On Green Self Oscillating Power Supply Serial Peripheral Interface bus; a 4wire synchronous serial data link standard Sony Philips Digital InterFace Static RAM Service Reference Protocol Small Signal Board

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EN 8

4.

L11M1.1L LA

Mechanical Instructions

4. Mechanical Instructions
Index of this chapter: 4.1 Cable Dressing 4.2 Service Positions 4.3 Assy/Panel Removal 4.4 Set Re-assembly Notes: Figures below can deviate slightly from the actual situation, due to the different set executions.

4.1

Cable Dressing

19130_002_110421.eps 110421

Figure 4-1 Cable dressing 32"

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Mechanical Instructions L11M1.1L LA 4.

EN 9

11 mm saddle 1 150 mm tape 3 70 mm tape 4 Foam 2

19130_003_110426.eps 110426

Figure 4-2 Cable dressing 40"

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EN 10 4.2
For easy servicing of a TV set, the set should be put face down on a soft flat surface, foam buffers or other specific workshop tools. Ensure that a stable situation is created to perform measurements and alignments. When using foam bars take care that these always support the cabinet and never only the display. Caution: Failure to follow these guidelines can seriously damage the display! Ensure that ESD safe measures are taken.

4.

L11M1.1L LA

Mechanical Instructions

Service Positions

4.3
Instructions below apply to the 40PFL3606D/78, but will be similar for other models. 4.3.1 Rear Cover

Assy/Panel Removal

2 3 2 2

2 3 3

1
2 3 3 1 1 1 1 3 2

19130_004_110426.eps 110426

Figure 4-3 Rear cover removal (40") Warning: Disconnect the mains power cord before removing the rear cover. See Figure 4-3. 1. Remove fixation screws [2] and [3] that secure the rear cover. It is not necessary to remove the stand first [1]. 2. Lift the rear cover from the TV. Make sure that wires and flat foils are not damaged while lifting the rear cover from the set.

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Mechanical Instructions L11M1.1L LA 4.

4.3.2 Refer to Figure 4-4 for details. 1. Remove the Stand [A]. 2. Remove the Speakers/Subwoofer [B]. 3. Remove the PSU [C], SSB [D] and TCON (E). 4. 5. 6. 7. LCD Panel

EN 11

Remove the IR/LED board [F]. Remove the Local Control board [G]. Remove the clamps [1]. Remove all metal subframes [2] that do not belong to the LCD display.

2 1 C 1

2 1

2 1

B 1 2 1 D

G F 1 1

A 1

19130_006_110426.eps 110426

Figure 4-4 LCD Panel removal (based on 40" model)

4.4

Set Re-assembly

Panel
To re-assemble the whole set, execute all processes in reverse order.
Thinner blue FFC supporting tape belong to Panel side Proper FFC insertion: Silver line is not visible when connector lock is closed

Notes: While re-assembling, make sure that all cables are placed and connected in their original position. See Figure 4-5 Pay special attention not to damage the EMC foams in the set. Ensure that EMC foams are mounted correctly.

TCON

Thicker blue FFC supporting tape belong to SSB side

Improper FFC insertion: Silver line is visible when connector lock is closed
19130_007_110426.eps 110426

Figure 4-5 Flat Foil Cable (FFC) precautions

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EN 12

5.

L11M1.1L LA

Service Modes, Error Codes, and Fault Finding

5. Service Modes, Error Codes, and Fault Finding

5.2.1 General Next items are applicable to all Service Modes or are general. Life Timer During the life time cycle of the TV set, a timer is kept (called Op. Hour). It counts the normal operation hours (not the Stand-by hours). The actual value of the timer is displayed in SDM and SAM in a decimal value. Every two soft-resets increase the hour by +1. Stand-by hours are not counted. Index of this chapter: 5.1 Test Points 5.2 Service Modes 5.3 Service Tools 5.4 Error Codes 5.5 The Blinking LED Procedure 5.6 Fault Finding and Repair Tips 5.7 Software Upgrading

5.1
In the chassis schematics and layout overviews, the test points are mentioned. In the schematics and layouts, test points are indicated with Fxxx or Ixxx. As most signals are digital, it will be difficult to measure waveforms with a standard oscilloscope. Several key ICs are capable of generating test patterns, which can be controlled via ComPair. In this way it is possible to determine which part is defective. Perform measurements under the following conditions: Service Default Mode. Video: Colour bar signal. Audio: 3 kHz left, 1 kHz right.

Test Points

5.2
The Service Mode feature is split into four parts: Service Default Mode (SDM). Service Alignment Mode (SAM). Customer Service Mode (CSM). Computer Aided Repair Mode (ComPair).

Service Modes

Software Identification, Version, and Cluster The software ID, version, and cluster will be shown in the main menu display of SDM, SAM, and CSM. The screen will show: AAAAAAB-XX.YY, where: AAAAAA is the chassis name: L11M11. B is the region indication: E= Europe, A= AP/China, U= NAFTA, L= LATAM. XX is the main version number: this is updated with a major change of specification (incompatible with the previous software version). Numbering will go from 01 - 99 and AA ZZ. If the main version number changes, the new version number is written in the NVM. If the main version number changes, the default settings are loaded. YY is the sub version number: this is updated with a minor change (backwards compatible with the previous versions) Numbering will go from 00 - 99. If the sub version number changes, the new version number is written in the NVM. If the NVM is fresh, the software identification, version, and cluster will be written to NVM. Display Option Code Selection When after an SSB or display exchange, the display option code is not set properly, it will result in a TV with no display. Therefore, it is required to set this display option code after such a repair. To do so, press the following key sequence on a standard RC transmitter: 062598 directly followed by MENU/HOME and xxx, where xxx is a 3 digit decimal value of the panel type, see sticker on the side/bottom of the cabinet. When the value is accepted and stored in NVM, the set will switch to Stand-by, to indicate that the process has been completed.

SDM and SAM offer features, which can be used by the Service engineer to repair/align a TV set. Some features are: A pre-defined situation to ensure measurements can be made under uniform conditions (SDM). Activates the blinking LED procedure for error identification when no picture is available (SDM). The possibility to overrule software protections when SDM is entered via the Service pins. Make alignments (e.g. White Tone), (de)select options, enter options codes, reset the error buffer (SAM). Display information (SDM or SAM indication in upper right corner of screen, error buffer, software version, operating hours, options and option codes, sub menus).

Display Option Code

39mm

PHILIPS
27mm

040

The CSM is a Service Mode that can be enabled by the consumer. The CSM displays diagnosis information, which the customer can forward to the dealer or call centre. In CSM mode, CSM, is displayed in the top right corner of the screen. The information provided in CSM and the purpose of CSM is to: Increase the home repair hit rate. Decrease the number of nuisance calls. Solved customers' problem without home visit.

MODEL: 32PF9968/10
PROD.SERIAL NO: AG 1A0620 000001

(CTN Sticker)

10000_038_090121.eps 090819

ComPair Mode is used for communication between a computer and a TV on I2C /UART level and can be used by a Service engineer to quickly diagnose the TV set by reading out error codes, read and write in NVMs, communicate with ICs and the uP (PWM, registers, etc.), and by making use of a fault finding database. It will also be possible to up and download the software of the TV set via I2C with help of ComPair. To do this, ComPair has to be connected to the TV set via the ComPair connector, which will be accessible through the rear of the set (without removing the rear cover).

Figure 5-1 Location of Display Option Code sticker During this algorithm, the NVM-content must be filtered, because several items in the NVM are TV-related and not SSBrelated (e.g. Model and Prod. S/N). Therefore, Model and Prod. S/N data is changed into See Type Plate. In case a call centre or consumer reads See Type Plate in CSM mode, he needs to look to the side/bottom sticker to identify the set, for further actions.

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5.2.2 Service Default Mode (SDM)

EN 13

Purpose Set the TV in SDM mode in order to be able to create a predefined setting for measurements to be made. In this platform, a simplified SDM is introduced (without protection override and without tuning to a predefined frequency).

ERR: Shows all errors detected since the last time the buffer was erased in format <xxx> <xxx> <xxx> <xxx> <xxx> (five errors possible). OP: Used to read-out the option bytes. Ten codes (in two rows) are possible.

How to Navigate As this mode is read only, there is not much to navigate. To switch to other modes, use one of the following methods: Command MENU from the user remote will enter the normal user menu (brightness, contrast, color, etc...) with SDM OSD remaining, and pressing MENU key again will return to the last status of SDM again. To prevent the OSD from interfering with measurements in SDM, command OSD or i+ (STATUS or INFO for NAFTA and LATAM) from the user remote will toggle the OSD on/off with SDM OSD remaining always on. Press the following key sequence on the remote control transmitter: 062596 directly followed by the INFO[i+]/OK button to switch to SAM (do not allow the display to time out between entries while keying the sequence). How to Exit Switch the set to Stand-by by pressing the standby button on the remote control transmitter or on the television set, or via a standard RC-transmitter by keying the 00 sequence. If you switch the television set off by removing the mains (i.e., unplugging the television), the television set will remain in SDM when mains is re-applied, and the error buffer is not cleared. The error buffer will only be cleared when the clear command is used in the SAM menu. Note: If the TV is switched off by a power interrupt while in SDM, the TV will show up in the last status of SDM menu as soon as the power is supplied again. The error buffer will not be cleared. In case the set is accidentally in Factory mode (with an F displayed on the screen), pressing and holding VOL- button for 5 seconds and then followed by pressing and holding the CH- button for another 5 seconds should exit the Factory mode. 5.2.3 Service Alignment Mode (SAM) Purpose To change option settings. To display / clear the error code buffer. To perform alignments.

Specifications Set linear video and audio settings to 50%, but volume to 25%. Stored user settings are not affected. Set Smart Picture to Game. Set Smart Sound to Standard. Tune channel to: - for analogue SDM: channel 3 (61.25 MHz) - for digital SDM: channel 26 (545.143 MHz). For digital SDM: set PID default from the stream. All service-unfriendly modes (if present) are disabled, since they interfere with diagnosing/repairing a set. These service unfriendly modes are: (Sleep) timer. Blue mute/Wall paper. Auto switch off (when there is no ident signal). Hotel or hospital mode. Child lock or parental lock (manual or via V-chip). Skipping, blanking of Not favourite, Skipped or Locked presets/channels. Automatic storing of Personal Preset or Last Status settings. Automatic user menu time-out (menu switches back/ OFF automatically. Auto Volume levelling (AVL). How to Activate To activate analogue SDM, use one of the following methods: Press the following key sequence on the RC transmitter: 062596 directly followed by the MENU button. Short one of the Service pads on the TV board during cold start (see Figure 5-2). Then press the mains button (remove the short after start-up). Caution: When doing this, the service-technician must know exactly what he is doing, as it could damage the television set. To activate digital SDM: Press the following sequence on the RC transmitter: 062593 directly followed by the MENU button.

SDM

Specifications Operation hours counter (maximum five digits displayed). Software version, error codes, and option settings display. Error buffer clearing. Option settings. Software alignments (White Tone). NVM Editor. Set screen mode to full screen (all content is visible). Set Smart Picture to Game.
19130_008_110426.eps 110426

Figure 5-2 Service pads (SSB component side)

How to Activate To activate SAM, use one of the following methods: Press the following key sequence on the remote control transmitter: 062596 directly followed by the INFO[i+] /OK button. Do not allow the display to time out between entries while keying the sequence. Or via ComPair. On Screen Menu After activating SDM, the following items are displayed, with SDM in the upper right corner of the screen to indicate that the television is in Service Default Mode. Menu items and explanation: xxxxx: Operating hours (in decimal). AAAAAAB-XX.YY: See paragraph Software Identification, Version, and Cluster for the SW name definition. After entering SAM, the following items are displayed, with SAM in the upper right corner of the screen to indicate that the television is in Service Alignment Mode.

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5.

L11M1.1L LA

Service Modes, Error Codes, and Fault Finding

soon as the power is supplied again. The error buffer will not be cleared. In case the set is in Factory mode by accident (with F displayed on screen), pressing and holding VOL- button for 5 seconds and then followed by pressing and holding the CH- button for another 5 seconds should exit the Factory mode.

5.2.4

Customer Service Mode (CSM) Purpose The Customer Service Mode shows error codes and information on the TVs operation settings. A call centre can instruct the customer (by telephone) to enter CSM in order to identify the status of the set. This helps them to diagnose problems and failures in the TV before making a service call. The CSM is a read-only mode; therefore, modifications are not possible in this mode. Specifications Ignore Service unfriendly modes. Set volume to 25%. Set Smart Picture to Game. Set Smart Sound to Standard. Line number for every line (to make CSM language independent). Set the screen mode to full screen (all contents on screen is visible). After leaving the Customer Service Mode, the original settings are restored. Possibility to use CH+ or CH- for channel surfing, or enter the specific channel number on the RC. How to Activate To activate CSM, press the following key sequence on a standard remote control transmitter: 123654 (do not allow the display to time out between entries while keying the sequence). After entering the Customer Service Mode, the following items are displayed: Menu Explanation CSM1 1. Set Type. Type number, e.g. 32PFL3605/78. (*) 2. Production code. Product serial no., e.g. BZ1A1008123456 (*). BZ= Production centre, 1= BOM code, A= Service version change code, 10= Production year, 08= Production week, 123456= Serial number. 3. Installation date. Indicates the date of the first initialization of the TV. This date is acquired via time extraction. 4. a - Option Code 1. Option code information (group 1). b - Option Code 2. Option code information (group 2). 5. SSB. Indication of the SSB factory ID (= 12nc). (*) 6. Display. Indication of the display ID (=12 nc). (*) 7. PSU. Indication of the PSU factory ID (= 12nc). (*) If an NVM IC is replaced or initialized, these items must be re-written to it. ComPair will foresee in a possibility to do this. Also the NVM editor in the SAM menu can be used.

Menu items and explanation: 1. System Information. Op Hour: This represents the life timer. The timer counts normal operation hours, but does not count Stand-by hours. MAIN SW ID: See paragraph Software Identification, Version, and Cluster for the SW name definition. ERR: Shows all errors detected since the last time the buffer was erased. Five errors possible. OP1/OP2: Used to read-out the option bytes. See paragraph 6.6 Option Settings in the Alignments section for a detailed description. Ten codes are possible. 2. Tuner. AGC Adjustment: See paragraph 6.3.1 for instructions. Store: To store the data. 3. Clear. Erases the contents of the error buffer. Select this menu item and press the MENU RIGHT key on the remote control. The content of the error buffer is cleared. 4. Options. To set the option bits. See paragraph 6.6 Option Settings in the Alignments chapter for a detailed description. 5. RGB Align. To align the White Tone. See White Tone Alignment: for a detailed description. 6. NVM Editor. To change the NVM data in the television set. See also paragraph 5.6 Fault Finding and Repair Tips. 7. Upload to USB. 8. Download from USB. 9. Initialise NVM. To initialize a (corrupted) NVM. Be careful, this will erase all settings! 10. Auto ADC. Refer to chapter 6. Alignments for detailed information. 11. EDID Write Enable. Enables EDID writing (not applicable to Berlinale sets). 12. Service Data. Virtual Key board for character input entry. How to Navigate In the SAM menu, select menu items with the UP/DOWN keys on the remote control transmitter. The selected item will be indicated. When not all menu items fit on the screen, use the UP/DOWN keys to display the next / previous menu items. With the LEFT/RIGHT keys, it is possible to: Activate the selected menu item. Change the value of the selected menu item. Activate the selected sub menu. When you press the MENU button twice while in top level SAM, the set will switch to the normal user menu (with the SAM mode still active in the background). To return to the SAM menu press the MENU button. The INFO[i+]/OK key from the user remote will toggle the OSD on/off with SAM OSD remaining always on. Press the following key sequence on the remote control transmitter: 062596 directly followed by the MENU button to switch to SDM (do not allow the display to time out between entries while keying the sequence). How to Store SAM Settings To store the settings changed in SAM mode (except the OPTIONS and RGB ALIGN settings), leave the top level SAM menu by using the POWER button on the remote control transmitter or the television set. The mentioned exceptions must be stored separately via the STORE button. How to Exit Switch the set to STANDBY by pressing the mains button on the remote control transmitter or the television set, or by keying-in the 00 sequence on a standard RC-transmitter. Note: When the TV is switched off by a power interrupt while in SAM, the TV will show up in normal operation mode as

Menu Explanation CSM2 1. Current Main SW. Shows the main software version. 2. Standby SW. Shows the Stand-by software version. 3. Panel Code. Shows the current display code. 4. Bootloader ID. Shows the Bootloader software ID. 5. NVM Version. The NVM software version no. 6. Flash ID. Shows the flash ID. Menu Explanation CSM3 1. Signal Quality. Shows the signal quality (No Tuned/Poor/ Average/Good). 2. Child lock. This is a combined item for locks. If any lock (Preset lock, child lock, lock after, or Parental lock) is active, this item indicates active.
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EN 15

TO TV
TO UART SERVICE CONNECTOR TO I2C SERVICE CONNECTOR TO UART SERVICE CONNECTOR

3. HDCP Keys. Indicates if the HDMI keys (or HDCP keys) are valid or not. Not applicable to Berlinale series. 4. not used 5. not used 6. not used 7. not used.
ComPair II RC in RC out Multi function

Optional Power Link/ Mode Switch Activity

I2C

RS232 /UART

Create a CSM dump on an USB stick There will be CSM dump to a plugged in USB-stick upon entering CSM-mode. An extended CSM dumpwill be created when the OK button on RC is pressed in CSM while a USB stick is plugged in. A direct CSM flash dump will be created when the buttons red + 2679 on the remote control are pressed in CSM while a USB stick is plugged in.

PC

ComPair II Developed by Philips Brugge Optional power 5V DC HDMI I2C only

How to Exit To exit CSM, use one of the following methods: Press the MENU/HOME button on the remote control transmitter. Press the POWER button on the remote control transmitter. Press the POWER button on the television set.

10000_036_090121.eps 091118

5.3
5.3.1 ComPair

Service Tools

Figure 5-3 ComPair II interface connection Caution: It is compulsory to connect the TV to the PC as shown in the picture above (with the ComPair interface in between), as the ComPair interface acts as a level shifter. If one connects the TV directly to the PC (via UART), ICs will be blown! How to Order ComPair II order codes: ComPair II interface: 3122 785 91020. ComPair UART interface cable: 3138 188 75051. Program software can be downloaded from the Philips Service web portal. Note: For this chassis, Pgammar and T-con NVM programming (VCOM alignment) are added to ComPair. Additional cables for VCOM Alignment ComPair/I2C interface cable: 3122 785 90004. ComPair/VGA adapter cable: 9965 100 09269.

Introduction ComPair (Computer Aided Repair) is a Service tool for Philips Consumer Electronics products. and offers the following: 1. ComPair helps you to quickly get an understanding on how to repair the chassis in a short and effective way. 2. ComPair allows very detailed diagnostics and is therefore capable of accurately indicating problem areas. You do not have to know anything about I2C or UART commands yourself, because ComPair takes care of this. 3. ComPair speeds up the repair time since it can automatically communicate with the chassis (when the uP is working) and all repair information is directly available. 4. ComPair features TV software up possibilities.

Specifications ComPair consists of a Windows based fault finding program and an interface box between PC and the (defective) product. The (new) ComPair II interface box is connected to the PC via an USB cable. For the TV chassis, the ComPair interface box and the TV communicate via a bi-directional cable via the service connector(s). How to Connect This is described in the ComPair chassis fault finding database.

5.4
5.4.1

Error Codes
Introduction Error codes are required to indicate failures in the TV set. In principle a unique error code is available for every: Activated (SW) protection. Failing I2C device. General I2C error. The last five errors, stored in the NVM, are shown in the Service menus. This is called the error buffer. The error code buffer contains all errors detected since the last time the buffer was erased. The buffer is written from left to right. When an error occurs that is not yet in the error code buffer, it is displayed at the left side and all other errors shift one position to the right. An error will be added to the buffer if this error differs from any error in the buffer. The last found error is displayed on the left. An error with a designated error code never leads to a deadlock situation. It must always be diagnosable (e.g. error buffer via OSD or blinking LED or via ComPair). In case a failure identified by an error code automatically results in other error codes (cause and effect), only the error code of the MAIN failure is displayed.

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EN 16
5.4.2 Example (2): the content of the error buffer is 12 9 6 0 0 After entering SDM, the following occurs: 1 long blink of 5 seconds to start the sequence, 12 short blinks followed by a pause of 1.5 seconds, 9 short blinks followed by a pause of 1.5 seconds, 6 short blinks followed by a pause of 1.5 seconds, 1 long blink of 1.5 seconds to finish the sequence, The sequence starts again with 12 short blinks. 5.5.2 Displaying the Entire Error Buffer Additionally, the entire error buffer is displayed when Service Mode SDM is entered. You can read the error buffer in three ways: On screen via the SAM/SDM/CSM (if you have a picture). Example: ERROR: 0 0 0 0 0 : No errors detected ERROR: 6 0 0 0 0 : Error code 6 is the last and only detected error ERROR: 9 6 0 0 0 : Error code 6 was detected first and error code 9 is the last detected (newest) error Via the blinking LED procedure (when you have no picture). See paragraph 5.5 The Blinking LED Procedure. Via ComPair. 5.4.3 Error codes How to Read the Error Buffer

5.

L11M1.1L LA

Service Modes, Error Codes, and Fault Finding

5.6

Fault Finding and Repair Tips

Notes: It is assumed that the components are mounted correctly with correct values and no bad solder joints. Before any fault finding actions, check if the correct options are set.

The layer 1 error codes are pointing to the defective board. They are triggered by LED blinking when CSM is activated. In the LC10 platform, only two boards are present: the SSB and the PSU/IPB, meaning only the following layer 1 errors are defined: 2: SSB 3: IPB/PSU 4: Display 5.6.1 Table 5-1 Error code table
Layer-1 Defective error code board 2 3 3 2 2 2 2 4 Display (Inverter) 18 SSB 27 SSB 23 SSB 34 Tuner I2C error on SSB HDMI Mux IC I2C error on SSB - Berninale models with Mux only Channel decoder on SSB LCD Panel inverter error. INV_STATUS (for 32 sets only) SSB 35 IPB/PSU 17 POK line defective EEPROM I2C error on SSB, M24C16 IPB/PSU 16 +12 missing/low, PSU defective SSB 11 Speaker DC protection active on SSB Layer-2 error code Defective device

NVM Editor In some cases, it can be convenient if one directly can change the NVM contents. This can be done with the NVM Editor in SAM mode. With this option, single bytes can be changed. Caution: Do not change these, without understanding the function of each setting, because incorrect NVM settings may seriously hamper the correct functioning of the TV set! Always write down the existing NVM settings, before changing the settings. This will enable you to return to the original settings, if the new settings turn out to be incorrect. 5.6.2 Load Default NVM Values

5.4.4

How to Clear the Error Buffer The error code buffer is cleared in the following cases: By using the CLEAR command in the SAM menu: By using the following key sequence on the remote control transmitter: 062599 directly followed by the OK button. If the contents of the error buffer have not changed for 50 hours, the error buffer resets automatically. Note: If you exit SAM by disconnecting the mains from the television set, the error buffer is not reset.

5.5
5.5.1

The Blinking LED Procedure

Introduction The software is capable of identifying different kinds of errors. Because it is possible that more than one error can occur over time, an error buffer is available, which is capable of storing the last five errors that occurred. This is useful if the OSD is not working properly. Errors can also be displayed by the blinking LED procedure. The method is to repeatedly let the front LED pulse with as many pulses as the error code number, followed by a period of 1.5 seconds in which the LED is off. Then this sequence is repeated. Example (1): error code 4 will result in four times the sequence LED on for 0.25 seconds / LED off for 0.25 seconds. After this sequence, the LED will be off for 1.5 seconds. Any RC command terminates the sequence. Error code LED blinking is in red color.
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It is possible to download default values automatically into the NVM in case a blank NVM is placed or when the NVM first 20 address contents are FF. After the default values are downloaded, it is possible to start-up and to start aligning the TV set. To initiate a forced default download the following action has to be performed: 1. Switch off the TV set with the mains cord disconnected from the wall outlet (it does not matter if this is from Standby or Off situation). 2. Short-circuit the SDM pads on the SSB (keep short circuited, see Figure 5-2). 3. Press P+ or CH+ on the local keyboard (and keep it pressed). 4. Reconnect the mains supply to the wall outlet. 5. Release the P+ or CH+ when the set is started up and has entered SDM. When the downloading has completed successfully, the set will perform a restart. After this, put the set to Stand-by and remove the short-circuit on the SDM pads.

Alternative method: It is also possible to upload the default values to the NVM with ComPair in case the SW is changed, the NVM is replaced with a new (empty) one, or when the NVM content is corrupted. After replacing an EEPROM (or with a defective/no EEPROM), default settings should be used to enable the set to start-up and allow the Service Default Mode and Service Alignment Mode to be accessed.

Service Modes, Error Codes, and Fault Finding L11M1.1L LA 5.

5.6.3 When you have no picture, first make sure you have entered the correct display code. See Display Option Code Selection for the instructions. 5.6.4 Unstable Picture via HDMI input No Picture

EN 17

3. Execute the command "NVM Copy" > "NVM Copy from USB" to copy the USB data to NVM (this takes about a minute to complete). To write an NVM mask to the TV, ensure that the mask has the correct format: "L11M11L_NVM_U2T.MAK" (0x00 to write protect, 0xFF to overwrite). Important: The file must be located in the "/Repair" directory of the USB stick. 5.7.4 How to Copy EDID Data to/from USB

Check (via ComPair) if HDMI EDID data is properly programmed. 5.6.5 Check if HDCP key is valid. This can be done in CSM. 5.6.6 Go to Home/Menu ->Setup -> Installation -> Preference and set the Easylink option to on. Also check if the connected device is CEC enabled. 5.6.7 Possible Stand-by Controller failure. Reflash the SW. TV Will Not Start-up from Stand-by. HDMI CEC Not Functioning No Picture via HDMI input

Write EDID Data to USB 1. Insert the USB stick into the USB slot while in SAM mode. 2. Execute the command "NVM Copy" > "EDID Copy to USB", to copy the EDID data to the USB stick. The filename on the USB stick will be named "L11M11L_EDID_T2U.BIN" (this takes a couple of seconds). Write EDID Data to TV 1. First, ensure (via a PC) that the filename on the USB stick has the correct format: "L11M11L_EDID_U2T.BIN". 2. Insert the USB stick into the USB slot while in SAM mode. 3. Execute the command "NVM Copy" > "EDID Copy from USB" to copy the USB data to EDID (this takes about a minute to complete). Important: The file must be located in the "/Repair" directory of the USB stick. 5.7.5 How to Copy the Channel List to/from USB

5.7
5.7.1 Introduction

Software Upgrading

It is possible for the user to upgrade the main software via the USB port. This allows replacement of a software image in a stand alone set. A description on how to upgrade the main software can be found in the DFU or on the Philips website. 5.7.2 Main Software Upgrade

Write Channel List Data to USB 1. Insert the USB stick into the USB slot while in SAM mode. 2. Execute the command "Channel list Copy to USB", to copy the channel list data to the USB stick. The filename on the USB stick will be named "L11M11L_CHTB_T2U.BIN" (this takes a couple of seconds). Write Channel List Data to TV 1. First, ensure (via a PC) that the filename on the USB stick has the correct format: "L11M11L_CHTB_U2T.BIN". 2. Insert the USB stick into the USB slot while in SAM mode. 3. Execute the command "Chanel list Copy from USB" to copy the USB data to the TV (this takes about a minute to complete). Important: The file must be located in the "/Repair" directory of the USB stick.

Automatic Software Upgrade In normal conditions, so when there is no major problem with the TV, the main software and the default software upgrade application can be upgraded with the autorun.upg (FUS part in the one-zip file). This can also be done by the consumers themselves, but they will have to get their software from the commercial Philips website or via the Software Update Assistant in the user menu (see DFU). The autorun.upg file must be placed in the root of your USB stick. How to upgrade: 1. Copy the autorun.upg file to the root of an USB stick. 2. Insert the USB stick in the side I/O while the set is on. The TV will prompt an upgrade message. Press Update to continue, after which the upgrading process will start. As soon as the programming is finished, the set must be restarted. In the Setup menu you can check if the latest software is running. 5.7.3 How to Copy NVM Data to/from USB Write NVM Data to USB 1. Insert the USB stick into the USB slot while in SAM mode. 2. Execute the command "NVM Copy" > "NVM Copy to USB", to copy the NVM data to the USB stick. The NVM filename on the USB stick will be named "L11M11L_NVM_T2U.BIN" (this takes a couple of seconds). Write NVM Data to TV 1. First, ensure (via a PC) that the filename on the USB stick has the correct format: "L11M11L_NVM_U2T.BIN". 2. Insert the USB stick into the USB slot while in SAM mode.

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6.

L11M1.1L LA

Alignments

6. Alignments
6.3 Software Alignments
With the software alignments of the Service Alignment Mode (SAM) the Tuner and RGB settings can be aligned. Index of this chapter: 6.1 General Alignment Conditions 6.2 Hardware Alignments 6.3 Software Alignments 6.4 ADC gain adjustment 6.6 Option Settings Note: Figures below can deviate slightly from the actual situation, due to the different set executions. 6.3.1 Tuner Adjustment (RF AGC Take Over Point) Purpose: To keep the tuner output signal constant as the input signal amplitude varies. No alignment is necessary, as the AGC alignment is done automatically. 6.3.2 RGB Alignment Before alignment, set the picture as follows:
Picture Setting Dynamic backlight Dynamic Contrast Colour Enhancement Picture Format Light Sensor Brightness Colour Contrast Off Off Off Unscaled Off 50 0 100

General: The Service Default Mode (SDM) and Service Alignment Mode (SAM) are described in chapter 5. Menu navigation is done with the CURSOR UP, DOWN, LEFT or RIGHT keys of the remote control transmitter.

6.1
Perform all electrical adjustments under the following conditions: Power supply voltage (depends on region): AP-NTSC: 120 VAC or 230 VAC / 50 Hz ( 10%). AP-PAL-multi: 120 - 230 VAC / 50 Hz ( 10%). EU: 230 VAC / 50 Hz ( 10%). LATAM-NTSC: 120 - 230 VAC / 50 Hz ( 10%). US: 120 VAC / 60 Hz ( 10%). Connect the set to the mains via an isolation transformer with low internal resistance. Allow the set to warm up for approximately 15 minutes. Measure voltages and waveforms in relation to correct ground (e.g. measure audio signals in relation to AUDIO_GND). Caution: It is not allowed to use heatsinks as ground. Test probe: Ri > 10 Mohm, Ci < 20 pF. Use an isolated trimmer/screwdriver to perform alignments.

General Alignment Conditions

White Tone Alignment: Activate SAM. Select RGB Align. and choose a color temperature. Use a 100% white screen as input signal and set the following values: Red BL Offset and Green BL Offset to 7 (if present). All White point values initial to 127.

6.2

Hardware Alignments
There are no hardware alignments foreseen for this chassis, but below find an overview of the most important DC voltages on the SSB. These can be used for checking proper functioning of the DC/DC converters.
Test Description Point +12VS +3V3_SW +1V25_SW +5V_SW +1V8_SW +1V1_SW +5VS +2V5_SW F118 +3V3_STBY F113 F133 F131 F132 F125 F101 F235 F136 +5VTUN_DI F236 GITAL VLS_15V6 VGH_35V VGL_-6V VCC_3V3 VCC1V8 FJ01 FM02 FJ14 FJ13 FJ05 Specifications (V) Min. 11.7 3.2 3.17 1.18 4.98 1.74 0.94 4.94 2.38 4.75 14.82 34.0 -7.0 3.14 1.71 Typ. 12.3 3.3 3.34 1.25 5.25 1.83 1.1 5.2 2.5 5 15.6 35.0 -6.0 3.3 1.8 Max. 12.91 3.4 3.5 1.31 5.51 1.92 1.15 5.46 2.62 5.25 16.38 36.0 -5.0 3.47 1.89 Diagram B01_DC-DC B01_DC-DC B01_DC-DC B01_DC-DC B01_DC-DC B01_DC-DC B01_DC-DC B02A_Tuner_IF B01_DC-DC B02_Tuner_IF

In case you have a color analyzer: Measure with a calibrated (phosphor- independent) color analyzer (e.g. Minolta CA-210) in the centre of the screen. Consequently, the measurement needs to be done in a dark environment. Adjust the correct x,y coordinates (while holding one of the White point registers R, G or B on max. value) by means of decreasing the value of one or two other white points to the correct x,y coordinates (see Table 6-1 White D alignment values). Tolerance: dx: 0.002, dy: 0.002. Repeat this step for the other color Temperatures that need to be aligned. When finished return to the SAM root menu and press STANDBY on the RC to store the aligned values to the NVM. Table 6-1 White D alignment values Value Cool (11000 K) Normal (9000 K) Warm (6500 K)
B08C_TCON DC/DC B08F_MINI LVDS B08C_TCON DC/DC B08C_TCON DC/DC B08C_TCON DC/DC

x y

0.276 0.282

0.287 0.296

0.313 0.329 If you do not have a color analyzer, you can use the default values. This is the next best solution. The default values are average values coming from production (statistics). Set the RED, GREEN and BLUE default values per temperature according to the values in the Tint settings table. When finished return to the SAM root menu and press STANDBY on the RC to store the aligned values to the NVM.

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Alignments L11M1.1L LA 6.
Table 6-2 Tint settings 32"
Colour Temp. Cool Normal Warm t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. R G B

EN 19

6.5

TCON Alignment (= VCOM alignment)

Table 6-3 Tint settings 40"

Colour Temp. Cool Normal Warm t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. R G B

New requirement for TCON on SSB project: The purpose of VCOM alignment is to obtain an equal voltages for both Positive and Negative LC polarity. This is important to avoid Flicker and Image Sticking. The P-Gamma + VCOM calibrator IC, ISL24837 is used for VCOM adjustment. The adjusted VCOM data will be stored inside on-chip memory and will be automatically recalled during each power-up. ComPair (see 5.3.1 ComPair) will foresee in a possibility to do this alignment.

6.4 6.6
6.6.1 Use a Quantum Data Patters Generator 802BT and apply a PgcWrgb image (dot, cross and color bar mix pattern) according to Figure 6-1.

ADC gain adjustment

Option Settings
Introduction The microprocessor communicates with a large number of I2C ICs in the set. To ensure good communication and to make digital diagnosis possible, the microprocessor has to know which ICs to address. The presence/absence of these specific ICs (or functions) is made known by the option codes. Notes: After changing the option(s), save them with the STORE command. The new option setting becomes active after the TV is switched off and on again with the mains switch (the EAROM is then read again).

6.6.2
18920_200_100317.eps 100317

How To Set Option Codes

Figure 6-1 PgcWrgb pattern 6.4.1 YPbPr Following instructions result in correct alignment of ADC gain, offset and phase, related to YPbPr input signal. Apply a signal of format 1080i25. Apply following signals to the YPbPr input connectors: Pr signal of 0.7 Vp-p1 / 75 ohm to the red cinch connector. Y signal of 0.7 Vb-p2 / 75 ohm with a sync pulse of 0.3 Vp-p1 to the green cinch connector. Pb signal of 0.7 Vb-p1 / 75 ohm to the blue cinch connector. Select the input source to YPbPr input. In SAM, initiate the Auto ADC calibration command. Upon appearance of the Auto ADC Completed message, the alignment is completed. Notes: 1. Peak-to-Peak 2. Black-to-Peak. 6.4.2 PC VGA Following instructions result in correct alignment of ADC gain, offset and phase, related to PC VGA input signal. Apply a signal of format DMT1060. Apply following signals to the PC VGA input connector: Red signal of 0.7 Vp-p1 / 75 ohm. Green signal of 0.7 Vp-p1 / 75 ohm. Blue signal of 0.7 Vp-p1 / 75 ohm. Select the input source to PC VGA input. In SAM, initiate the Auto ADC calibration command. Upon appearance of the Auto ADC Completed message, the alignment is completed.

When the NVM is replaced, all options will require resetting. To be certain that the factory settings are reproduced exactly, you must set all option numbers. You can find the correct option numbers see sticker on the inside the cabinet. How to Change Options Codes An option code (or option byte) represents eight different options (bits). All options are controlled via ten option bytes (OP#1... OP#10). Activate SAM and select Options. Now you can select the option byte (OP#1... OP#10) with the CURSOR UP/ DOWN keys, and enter the new 3 digit (decimal) value. For the correct factory default settings, see the sticker inside the set.

2011-Apr-29

EN 20

7.

L11M1.1L LA

Circuit Descriptions

7. Circuit Descriptions
7.1 Introduction
The LC11M1.1L LA chassis is a digital chassis using a Mediatek chipset. It covers screen sizes of 32" to 40". The xxPFL3x06D/xx sets come with the Thriller styling, and the xxPFL5x06D/xx come with the Berlinale styling. Main key components are the Mediatek MT5363 integrated System On Chip (SoC) that supports multimedia video/audio input, and the integrated TCON (Timing Controller) part for the LCD panel. System SoC is based on MT5363: NAND Flash 128 Mbyte, NumOnyx/Hynix. DDR 128 Mbyte (32 16M, 2 pcs), Hynix. Use internal MT5363 Stand-by micro-controller. Tuner/Frontend configuration: Half NIM tuner (VA1E1BF2403) from Sharp. Toshiba Channel Decoder (TC90517). Interfaces for debug and SW upgrade: UART (3.5 mm jack). USB port. JTAG. Refer to Figure 7-1 for details. Index of this chapter: 7.1 Introduction 7.2 Power Supply 7.3 Video 7.3.1 Video: Front-End 7.4 Audio 7.5 Inputs 7.5.1 Inputs: HDMI 7.5.2 Inputs: USB Notes: Only new circuits (circuits that are not published recently) are described. Figures can deviate slightly from the actual situation, due to different set executions. For a good understanding of the following circuit descriptions, please use chapter 9. Block Diagrams and 10. Circuit Diagrams and PWB Layouts. Where necessary, you will find a separate drawing for clarification.

19130_009_110426.eps 110429

Figure 7-1 L11M1.1L LA Architecture

2011-Apr-29

Circuit Descriptions L11M1.1L LA 7.

EN 21

19130_010_110426.eps 110426

Figure 7-2 SSB cell layout

19130_047_110429.eps 110429

Figure 7-3 SSB key component overview

2011-Apr-29

EN 22

7.

L11M1.1L LA

Circuit Descriptions

19130_048_110429.eps 110429

Figure 7-4 TCON key component overview

7.2

Power Supply
+12 VS DCDC DCDC DCDC 1.1 V 0.05 V 1.8 V 0.09 V 3.3 V 0.16 V
DDR2 2

Regulator 5.25 V 0.26 V DCDC Regulator USB Regulator 5.25 V 0.25 V Tuner 2.5 V 0.12 V

1.25 V 0.06 V

The Power Supply Unit (PSU) in this chassis is a buy-in and is a black-box for Service. When defective, a new panel must be ordered and the defective panel must be returned for repair, unless the main fuse of the unit is broken. Always replace the fuse with one with the correct specifications! This part is commonly available in the regular market. Refer to Figure 7-5 and Figure 7-6 for details

Dig Demod

MT5363

NVM EEPROM

Flash +3.3 VSTBY

19130_012_110426.eps 110426

The power supply system consists of stand-by, switched and regulated voltages. The stand-by voltage, +3V3STBY, will be available once AC supply is provided to the system. As for the other voltages, namely switched and regulated voltages, these are available once the STANDBY signal is pulled low to allow other supplies from the IPB to turn on. The switched supplies are generated from the main +12VS supply, while the regulated supplies are derived from the switched supplies. There are a number of detection circuits to detect the following supplies: +12VS, +12Vdisp and +3V3_SW. The +12VS is the main supply voltage from the IPB that enables the switched voltages to be generated. The +12Vdisp is the supply to the display timing controller, while the +3V3_SW is powering the microprocessor and its flash memory. The mains power supply unit distribute the following voltages to the TV system: +3V3STBY, 12VS, +24Vaudio, and +24Vpanel for panel with inverter (or) high voltage (HV) for inverterless panel. Requirement of the High Voltage depend on the specification of the LCD panel.

Figure 7-5 Power distribution overview

18980_203_100402.eps 100402

Figure 7-6 Power timing overview

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Circuit Descriptions L11M1.1L LA 7. 7.3

7.3.1 Key components for the tuner section are: Sharp Half NIM tuner VA1E1BF2403, Refer to Figure 7-7 for details. Video: Front-End

EN 23

Video

Toshiba channel decoder TC90517 (external ISDB-T channel decoder). Analog demodulator (using internal MT5363 analog demodulator - pin AH35 VIP, AH37 VIN).

19130_013_110426.eps 110426

Figure 7-7 Front-end functional block diagram

2011-Apr-29

EN 24 7.4
Table 7-2 Microprocessor control lines - 2 From uP SW_MUTE HIGH RESET_AUDIO LOW HIGH MUTE HIGH DC_PROT HIGH LOW MUTE DC detected -> set going to protection No DC -> normal operating LOW LOW HIGH Operating (unmute) Class D shutdown (mute) Operating (unmute) Operating (unmute) LOW MUTE

7.

L11M1.1L LA

Circuit Descriptions

Audio
In this chassis, audio processing is done by the following key components: MT5363 micro-processor for input selection and audio processing, TPA3123D2 class-D power amplifier for 2 x 10 W amplification. The audio profile (optimal setting per screen size and styling) is stored at Option 10 (bit 0 to bit 4). Profile 1 for 32-inch Dali and profile 2 for 40-inch Dali. Table 7-1 Microprocessor control lines - 1 From uP SW_MUTE RESET_AUDIO A_STBY MUTE DC_PROT DC_PROT Detecting present of DC at speakers output and feedback to uP. This will trigger TV into protection mode. This is important to protect speakers MUTE Corresponding to the MUTE button on Remote Control, to mute/unmute speakers Control SHUTDOWN pin of class D amplifier: ON/OFF the amplifier SW_MUTE Will pull audio signals to LOW upon DC drops, help to eliminate plop sound. At class D Usage A_STBY to class D Class D outputs

19130_014_110426.eps 110426

Figure 7-8 Audio signal flow

7.5
7.5.1

Inputs
Inputs: HDMI In this chassis, the main Mediatek MT5363 SoC has an on-chip HDMI multiplexer. Refer to Figure 7-9 for the implementation.

2011-Apr-29

Circuit Descriptions L11M1.1L LA 7.

EN 25

RX2 OPWR2_5V HDMI_HPD2 HDMI_SCL2 HDMI_SDA2 ARC eHDMI+ HDMI_CEC CEC

TMDS PWR5V SIDE_HDMI_HPD1 SIDE_HDMI_SCL1 SIDE_HDMI_SDA1

MT5363
GPIO_7 GPIO 7 EDID EDID_WC EDID WC

RX1 OPWR1_5V HDMI_HPD1 HDMI_SDA1 HDMI_SDA1 TMDS PWR5V HDMI_HPD2 HDMI_SDA2 HDMI_SCL2

ASPDIF_OUT ARC_SW EDID Buffer & Selection circuit

19130_015_110426.eps 110426

Figure 7-9 HDMI implementation Signal description: TMDS: Signals that contain audio and video information. PWR5V: Signal to detect the presence of any HDMI source connected to the TVs HDMI input port. SIDE_HDMI_HPD1 and HDMI_HPD2: Signal to initiate reading of the TV EDID data by the source device. I2C: The EDID data reading and the HDCP authentication process runs via I2C. CEC: Signal direct connected between inputs and uP. EDID_WC: Signal used to disable the write protect pin of the EEPROM. When updating, the program will temporarily pull this pin LOW before writing new data. 7.5.2 Inputs: USB In this chassis, the main Mediatek MT5363 SoC has an on-chip USB processor. Refer to Figure 7-10 for the implementation.

18980_207_100402.eps 100402

Figure 7-10 USB implementation

2011-Apr-29

EN 26

8.

L11M1.1L LA

IC Data Sheets

8. IC Data Sheets
This section shows the internal block diagrams and pin layouts of ICs that are drawn as "black boxes" in the electrical diagrams (with the exception of "memory" and "logic" ICs).

8.1

Diagram B01, Type TPS54386 (IC7116 and 7117)

BLOCK DIAGRAM
2 CLK1 Level Shift f(IDRAIN1) + DC(ofst) + GND + FB1 0.8 VREF RCOMP f(ISLOPE1) f(IMAX1) CLK1 Soft Start 1 SD1 CCOMP 7 f(IDRAIN1) Overcurrent Comp Q 4 R R S Q Current Comparator BP 1 PVDD1 BOOT1

+
BP Weak Pull-Down MOSFET Anti-Cross Conduction f(ISLOPE1) Ramp Gen 1 TSD 6 A 6 A SD1 Internal Control 150 k SD2 UVLO 1.2 MHz Oscilator Divide by 2/4 Ramp Gen 2 CLK2 CLK1 f(ISLOPE2)

SW1

VDD2

EN1 EN2 6

SEQ 10 BP 150 k CLK2

FB1 FB2

Output Undervoltage Detect BP Level Shift f(IDRAIN2) + DC(ofst) Current Comparator + S R R + f(IDRAIN2) Q Q FET Switch

13 BOOT2

14 PVDD2

GND

FB2

8 0.8 VREF

+
RCOMP SD2 f(ISLOPE2) Soft Start 2 CCOMP

Overcurrent Comp f(IMAX2) CLK2 BP Weak Pull-Down MOSFET Anti-Cross Conduction

12 SW2

BP 11 150 k BP ILIM2 9 150 k Level Select

5.25-V Regulator

PVDD2

0.8 VREF References IMAX2 (Set to one of three limits)

UDG-07124

PIN CONNECTIONS
HTSSOP (PWP) (Top View) PVDD1 BOOT1 SW1 GND EN1 EN2 FB1 1 2 3 4 5 6 7 Thermal Pad (bottom side) 14 PVDD2 13 BOOT2 12 SW2 11 BP 10 SEQ 9 ILIM2 8 FB2

18980_300_100402.eps 100402

Figure 8-1 Internal block diagram and pin configuration

2011-Apr-29

IC Data Sheets L11M1.1L LA 8. 8.2 Diagram B01A DC-DC, Type LD1117D (IC7119)

EN 27

Block diagram

LD1117DT

Pinning information

DPAK

F_15710_166.eps 100402

Figure 8-2 Internal block diagram and pin configuration

2011-Apr-29

EN 28 8.3 Diagram B03 Class-D & muting, Type TPA3123 (IC7400)

8.

L11M1.1L LA

IC Data Sheets

Block diagram
1 F 0.22 F LIN 22 H 0.68 F 0.68 F 470 F RIN 1 F PGNDR 1 F BYPASS AGND BSL 0.22 F 22 H 470 F LOUT PGNDL ROUT BSR

AVCC PVCCR

PVCCL

VCLAMP Shutdown Control SD 1 F

MUTE

GAIN0 GAIN1

}
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13

Control

Pinning information
PVCCL SD PVCCL MUTE LIN RIN BYPASS AGND AGND PVCCR VCLAMP PVCCR
TERMINAL NAME SD RIN LIN GAIN0 GAIN1 MUTE BSL PVCCL LOUT PGNDL VCLAMP BSR ROUT PGNDR PVCCR AGND AGND BYPASS AVCC Thermal pad 24-PIN (PWP) 2 6 5 18 17 4 21 1, 3 22 23, 24 11 16 15 13, 14 10, 12 9 8 7 19, 20 Die pad I/O/P DESCRIPTION

PGNDL PGNDL LOUT BSL AVCC AVCC GAIN0 GAIN1 BSR ROUT PGNDR PGNDR

I I I I I I I/O P O P P I/O O P P P P O P P

Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance to AVCC Audio input for right channel Audio input for left channel Gain select least-significant bit. TTL logic levels with compliance to AVCC Gain select most-significant bit. TTL logic levels with compliance to AVCC Mute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle, low = outputs enabled). TTL logic levels with compliance to AVCC Bootstrap I/O for left channel Power supply for left-channel H-bridge, not internally connected to PVCCR or AVCC Class-D 1/2-H-bridge positive output for left channel Power ground for left-channel H-bridge Internally generated voltage supply for bootstrap capacitors Bootstrap I/O for right channel Class-D 1/2-H-bridge negative output for right channel Power ground for right-channel H-bridge. Power supply for right-channel H-bridge, not connected to PVCCL or AVCC Analog ground for digital/analog cells in core Analog ground for analog cells in core Reference for preamplifier inputs. Nominally equal to AVCC/8. Also controls start-up time via external capacitor sizing. High-voltage analog power supply. Not internally connected to PVCCR or PVCCL Connect to ground. Thermal pad should be soldered down on all applications to properly secure device to printed wiring board.

18440_302_090303.eps 090318

Figure 8-3 Internal block diagram and pin configuration

2011-Apr-29

IC Data Sheets L11M1.1L LA 8. 8.4 Diagram B04 MT5363 Power, Type MT5363 (IC7700)

EN 29

Block diagram
CVBS/ YC Input

HDMI Rx Panel LVDS

Audio Input

CVBS VDAC TVE

DVB-T TV Decoder VDO-In PreProc BIM MDDi 2-D Graphic Audio In JPEG,MPEG H.264

ATD

VADCx4

HDMI In I/F

Audio Demod Audio ADC

DDR DRAM Controller Mix andPost Processing OSD scaler Vplane scaler/PIP

ARM

TS Demux

IO Bus Audio DSP Audio I/F Audio DAC BScan PVR

JTAG IrDA SIF USB2.0 Watchdog

Standby uP CKGEN
Serial Flash Servo ADC

RTC UART

MS,SD

PWM

NAND Flash

SPDIF, I2S
18850_300_100107.eps 100222

Figure 8-4 Internal block diagram

2011-Apr-29

EN 30

8.

L11M1.1L LA

IC Data Sheets

Pinning information
LT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A RCLK0_ RDQ12 RDQ10 RDQ15 RDQS0_ RDQ14 AO1N AOCKN

B RCLK0 RDQ8 RDQS0 RDQ11 VCC2IO RDQS1 AO0N

VCC2IO

AO2N

AO3N

C VCC2IO VCC2IO
AO1P

RDQ13 RDQS1_ DVSS RDQM1

AOCKP

D VCC2IO RDQ5
AO0P

RA9 RDQ0 DVSS RDQ9 VCC2IO

AO2P

AO3P

E RA12 VCC2IO RA5 RA7 VCC2IO DVSS RDQ6 VCC2IO RDQ7 VCC2IO RDQ2 DVSS RDQM0 VCC2IO

AE0N

AE2N

AVDD33_L VDS VCC2IO AVDD33_L VDS VCC2IO

AE0P

AE1N

AECKN

G RA10 RDQ3 RBA2 RBA0 RA1 RDQ1 VCC2IO RA3 VCC2IO DVSS DVSS

AE2P

RDQ4

AE1P

AECKP

J RBA1 RCKE RWE_ MEMTN

MEMTP

DVSS DVSS

AVSS33_L VDS

L RCAS_ RA13 RA2 RA4 RA6 DVSS DVSS

TP_VPLL

N RA11
RVREF

RA0 RODT

DVSS

AVDD12_L VDS AVDD12_M EMPLL DVSS AVSS12_M EMPLL VCCK DVSS DVSS DVSS DVSS AVSS12_L VDS VCCK

AVDD12_V PLL AVSS12_V PLL DVSS

P RCS_ RRAS_ RVREF

RA8

R VCC2IO RDQ19 RDQ20 RDQ30 RDQ25 VCC2IO VCC2IO

DVSS DVSS

U RDQ22 RDQM2 RDQS2 RDQ28 RDQ17 RDQM3

RDQ27

VCCK

DVSS

DVSS

DVSS

W RDQS2_ RDQS3 DVSS RDQ24 DVSS DVSS

DVSS

DVSS

DVSS

RDQ31

VCCK

VCCK

DVSS

DVSS

AA RDQS3_ RDQ16 RDQ23 RDQ29

RDQ26

VCCK

DVSS

DVSS

AB

REXTDN

DVSS

DVSS

DVSS

DVSS

AC RDQ21 RCLK1

RDQ18

VCC2IO VCC2IO
VCC2IO

DVSS

DVSS

DVSS

AD

RCLK1_

DVSS

VCCK

VCCK

VCCK

AE
VCC2IO

VCC2IO

GPIO39

DVSS

VCCK

VCCK

VCCK

AF

VCC2IO

VCC2IO

GPIO37

GPIO40

DVSS

VCCIO33-1

VCCIO33-1

AG

GPIO38 GPIO44

GPIO41

GPIO42

VCCK

AH

GPIO43

JTDO

VCCK VCCK JTDI JTMS VCCK

AJ

AK

JTRST_

JTCK AL

VCCK

VCCK HDMI_SCL VCCK VCCK VCCK VCCK AM VCCK AVDD12_U SB VCCK AN VCCK VCCK AVSS12_U SB VCCK AP OSDA0 VCCK POCE1_ AVSS33_U OSCL0 PDD1 PDD4 PDD6 AR PDD0 AT POCE0_
PAALE

2 AVDD33_U SB AVSS33_H USB_VRT AVDD12_H SB PDD2 USB_DM POWE_ AU PARB_ AVSS33_U PDD5 SB POOE_ AV 1 2 3
PACLE AVSS33_U

HDMI_SDA 2 AVDD33_H DMI HDMI_CEC DMI RX2_0 DMI RX2_C RX2_0B SB PDD3 4 5 6 7 PDD7 8 9 USB_DP 10 11 RX2_CB 12 13 RX2_2 PWR5V_2

PWR5V_1

HDMI_HPD 1 HDMI_SCL 1
HDMI_SDA

OPCTRL1

HDMI_HPD 2 RX1_0

1 RX1_2

RX2_1

RX1_C RX2_2B RX1_0B

RX1_1 RX1_2B

RX2_1B 14 15

RX1_CB 16 17

RX1_1B 18 19

18850_301_100107.eps 100222

Figure 8-5 Internal block diagram

2011-Apr-29

IC Data Sheets L11M1.1L LA 8.

EN 31

Pinning information
20 AO4N GPI O35 GPI O21 GPI O3 ETTXD0 ETRXD2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 ETRXD0 37 RT A

DVSS

GPIO32

GPIO26

GPIO17

GPIO9

ETTXD3

ETRXCLK

ETRXD1

ETRXDV

AO4P

GPIO36

GPIO28

GPIO22

GPIO11

GPIO4

ETTXD1

ETRXD3

ETCRS

DVSS

GPIO34

GPIO27

GPIO18

GPIO10

ETTXEN

ETTXCLK

ETRXER ETMDC ETTXER

ETMDIO

AE3N

DVSS

GPIO30

GPIO20

GPIO12

GPIO6

ETTXD2

E CI_MOSTR CI_MCLKO CI_MCLKI CI_MOVAL T

AE4N

GPIO33

GPIO24

GPIO16

GPIO8

ETPHYCLK

AE3P

DVSS

GPIO29

GPIO19

GPIO14

GPIO5

ETCOL
CI_MISTR

CI_MIVAL

G CI_MDO0 VCCIO33 T GPIO2 OPWM0 CI_MDI0 OPWM1 H

AE4P

VCCIO33

GPIO25

GPIO15

GPIO7

GPIO31

GPIO23

GPIO13

VCCIO33

AOSDATA3

ASPDIF FSRC_WR ALIN AOBCK

GPIO0 AOSDATA0

GPIO1

IF_AGC DVSS VCCK VCCK AOSDATA4

RF_AGC TUNER_DA TA

AOMCLK TUNER_CL K OSCL2 OSDA2 AOSDATA1

AOLRCK

DVSS

DVSS

DVSS

AOSDATA2

DVSS

DVSS

DVSS

OSDA1

OSCL1

U1RX
VCXO

DVSS

DVSS

VCCK

AVDD33_A DAC1 AVSS33_A DAC1 AL1

OPWM2

U1TX

DVSS

DVSS

DVSS

AR2

AR3
AL3 V

DVSS
DVSS

DVSS DVSS VCCK

VCCK AVDD33_R EF_AADC

VCCIO33 VCCIO33

AR1 VCCIO33

AL2 VCCIO33

W AIN6_R_A

DVSS

DVSS

VCCK

AVSS33_R EF_AADC VMID_AAD VCCK DVSS VCCK

AVDD33_A ADC AIN4_L_AA C AIN1_L_AA DC DC

AVSS33_A ADC AIN5_L_AA DC AIN4_R_A ADC

AIN5_R_A ADC AIN6_L_AA DC AIN2_R_A ADC

ADC

DVSS DVSS DVSS

DVSS

AA AIN3_R_A AB ADC DVSS DVSS AIN1_R_A ADC AIN0_R_A ADC AIN3_L_AA DC AC

DVSS

DVSS

DVSS

AIN0_L_AA DC AVSS33_A

AIN2_L_AA DC

AD

VCCK

VCCK

DVSS AVDD12_T VDPLL AVDD12_A PLL AVSS12_P LL AVSS33_D IG AVSS33_SI F AVSS33_V OPWRSB OPCTRL0 OPCTRL2 OIRI ORESET_ AVDD10_L DO AVDD33_V GA_STB U0TX SOG SOY1 GA_STB AVDD12_R GB AVSS12_R GB PR1P Y0P
OPCTRL3 AVDD33_

DAC0 AVICM ADAC0 AVDD12_S YSPLL AVSS12_P LL AVDD12_A DCPLL XTALO AVDD33_D IG AVDD33_S IF FS_VDAC AVDD33_V DAC PB0P AVSS33_V HSYNC COM COM1 DAC VDAC_OUT U0RX BP RP PB1P COM0 2
OPCTRL4

AR0 AL0 AVDD33_ DEMOD1 ADCINN_D EMOD XTALI ADIN1_SR V ADIN0_SR V BYPASS0 AVDD33_C VBS VDAC_OUT 1 AVSS33_C VBS SC0 SY0 CVBS2P AF MPXP ADIN3_SR V ADIN2_SR V MPXN TUNER_BY PASS SY1 CVBS0N AVDD33_X TAL_STB ADIN5_SR V ADIN4_SR V AVSS33_X TAL AVSS33_D EMOD1 ADCINP_D EMOD

AE

AF

AG AH AJ

AK

AL

AM AN

AP AR

CVBS3P CVBS1P VSYNC 20 21 22 23 GP 24 25 Y1P 26 27 SOY0 28 29 PR0P 30 31 32 33 SC1 34 35

CVBS0P

AT AU

36

37

RB

18850_302_100107.eps 100222

Figure 8-6 Internal block diagram

2011-Apr-29

EN 32 8.5 Diagram B06B Analog I/O - Audio, Type LM833 (IC7B01)

8.

L11M1.1L LA

IC Data Sheets

Pinning information

Output 1
2 1 7

VCC Output 2

Inputs 1
3 6 2

Inputs 2
5

VEE (Top View)

18520_306_090325.eps 100402

Figure 8-7 Pin configuration

2011-Apr-29

IC Data Sheets L11M1.1L LA 8. 8.6 Diagram T01C TCON DC/DC, Type ISL97653 (IC7J00)

EN 33

Block diagram
RSET HVS VREF PROT CM1 GM AMPLIFIER FBB + VREF UVLO COMPARATOR + RSENSE 0.75 VREF FREQ VL PVIN1,2 REGULATOR REFERENCE BIAS CDEL EN SEQUENCE CONTROLLER AND CURRENT LIMIT COMPARATOR CURRENT LIMIT THRESHOLD 680kHz OSCILLATOR CURRENT AMPLIFIER PGND1 PGND2 BUFFER SLOPE COMPENSATION LX1 LX2 HVS LOGIC SAWTOOTH GENERATOR

CONTROL LOGIC

VL PVIN1,2 SUPN LXL1 LXL2 CONTROL LOGIC CURRENT LIMIT COMPARATOR + CURRENT LIMIT THRESHOLD BUFFER CURRENT AMPLIFIER GM AMPLIFIER CM2 CB

NOUT

FBN + 0.2V UVLO COMPARATOR + 0.4V 0.75 VREF +

(
SLOPE COMPENSATION SAWTOOTH GENERATOR

+ VREF

FBL

LDO-CTL
LDO CONTROL LOGIC2

LDO-FB

FBP VREF

SUPP +

TEMP SENSOR

TEMP

POUT SUPP

C1-

C1+

POUT

C2+

C2-

DRN

CTL

COM

LDO-CTL

LDO-FB

Pinning information

PVIN1

AGND

PROT

LX2

PGND2

PGND1 40 PVIN2 CB LXL1 LXL2 PGND3 PGND4 CM2 FBL VL VREF 1 2 3 4 5 6 7 8 9 10 11 FBN 12 SUPN 13 NOUT 14 PGND5 15 C1P 16 C1N 17 C2P 18 C2N 19 SUPP 39 38 37 36 35 34 LX1 33 32

31 30 COMP 29 FBB 28 RSET 27 HVS 26 EN 25 CDEL 24 CTL 23 DRN 22 COM 21 POUT 20 FBP

ISL97653A 40 LD 6X6 QFN TOP VIEW

TEMP

18770_307_100217.eps 100217

Figure 8-8 Internal block diagram and pin configuration

2011-Apr-29

EN 34

8.

L11M1.1L LA

IC Data Sheets

Personal Notes:

10000_012_090121.eps 090121

2011-Apr-29

Block Diagrams L11M1.1L LA 9. EN 35

9. Block Diagrams

Wiring Diagram 32" (Thriller)

WIRING DIAGRAM 32" THRILLER

Board Level Repair

Component Level Repair Only For Authorized Workshop

LCD DISPLAY (1004)
TO DISPLAY

8G51

TO BACKLIGHT

1M99

14P

8319

MAIN POWER SUPPLY 32 PSLC-P002A

LOUDSPEAKER (5213)
9P 1M99

(1005)
1G51 51P
11P 1M95

1M99

9P

8M99

1M95

11P

8M95

B
1M20 1735 8P
4P

SSB
3139 123 6505.x (1150)

TUNER

KEYBOARD CONTROL (1114)

2P3 N 1308 L

3P

J1

8308

INLET

J2

J1

3P

8P

IR/LED BOARD (1112)

MAINS CORD

8M20

HDMI

VGA

8191

1M95 (B01)
1. +3V3STDBY 2. STANDBY 3. GND 4. GND 5. GND 6. +12VS 7. +12VS 8. +12VS 9. +24VAUDIO 10. GND-AUDIO 11. ...

1M99 (B01)
1. 2. 3. 4. 5. 6. 7. 8. 9. +12VDISP +12VDISP GND GND LAMP-ON BACKLIGHT-PWM BACKLIGHT-BOOST INV_STATUS POWER-OK

1M20 (B04c)
1. 2. 3. 4. 5. 6. 7. 8. LIGHT-SENSOR GND RC LED-2 +3V3STBY LED-1 KEYBOARD +5V_SW

HDMI

USB

1735 (B03)
1. 2. 3. 4. LEFT_SPEAKER GND-AUDIO GND-AUDIO RIGHT_SPEAKER

1G51 (B04D)
1. +VDISP-INT 2. +VDISP-INT 3. +VDISP-INT 4. +VDISP-INT | 51. GND

19130_044_110428.eps 110429

2011-Apr-29

Block Diagrams L11M1.1L LA 9. EN 36

Wiring Diagram 40" (Thriller)

WIRING DIAGRAM 40" THRILLER

Board Level Repair

TO DISPLAY

LCD DISPLAY (1004)

TO DISPLAY

Component Level Repair Only For Authorized Workshop

8KA1 8KA2

TO BACKLIGHT

8316

1KA2 80P 80P

1KA1

TCON
(1157)
1N01 51P

T
LOUDSPEAKER (5213)

1319

1316

1P3

1P3

HIGH VOLTAGE

9P

MAIN POWER SUPPLY IPB 40 PLHE-P986A

1M99

(1005)
1G51 51P
11P 1M95

B
1M95 11P

SSB
3139 123 6505.x (1150)

8M95

1M99

9P

8M99

8G51

1M20 1735

8P

4P

TUNER

2P3 N 1308 L

KEYBOARD CONTROL (1114)

8M20

SPDIF

PHONE

HDMI

HDMI

VGA

HDMI

USB

1M95 (B01)
8308

1M99 (B01)

1M20 (B04c)

1KA2 (T01F)

3P

J1

INLET

1. 2. 3. 4. 5. 6. 7. 8. 9.

+12VDISP +12VDISP GND GND LAMP-ON BACKLIGHT-PWM BACKLIGHT-BOOST INV_STATUS POWER-OK

1. 2. 3. 4. 5. 6. 7. 8. 1. +3V3STDBY 2. STANDBY 3. GND 4. GND 5. GND 6. +12VS 7. +12VS 8. +12VS 9. +24VAUDIO 10. GND-AUDIO 11. ...

LIGHT-SENSOR GND RC LED-2 +3V3STBY LED-1 KEYBOARD +5V_SW

J2

J1

8191

3P

8P

IR/LED BOARD (1112)

1735 (B03) 1G51 (B04D)

1. +VDISP-INT 2. +VDISP-INT 3. +VDISP-INT 4. +VDISP-INT | 51. GND 1. 2. 3. 4. LEFT_SPEAKER GND-AUDIO GND-AUDIO RIGHT_SPEAKER

1KA1 (T01F) 1. GND | 11. VLS_15V6 12. VLS_15V6 | 33. VCC_3V3 34. VCC_3V3 | 78. VGH_35V 79. VGL_-6V 80. GND
MAINS CORD

1. GND | 11. VLS_15V6 12. VLS_15V6 | 33. VCC_3V3 34. VCC_3V3 | 78. VGH_35V 79. VGL_-6V 80. GND

1N01 (T01A)
1. GND | 47. +VDISP-INT 48. +VDISP-INT 49. +VDISP-INT 50. +VDISP-INT | 51. GND

19130_043_110428.eps 110429

2011-Apr-29

TO BACKLIGHT

8319

Block Diagrams L11M1.1L LA 9. EN 37

Block Diagram Video VIDEO

B04 MT5363: T01A LVDS
DISLAY
B08A INTERFACE VGL_-6V VGH_35V CS(1-12) VH 50 LLV(0-7) AE PX2 47 4 48 49 50 60 +VDISP-INT VLS_15V6 3 2 +VDISP-INT B06B AUDIO-VIDEO 1 PX2 RXE VCC_3V3 TO DISPLAY 13 34 33 12 11 10 VL 1KA1 81 7H01 VPP1501BFG

B02A TUNER T01B TCON CONTROL T01E MPD T01F MINI LVDS
7700 MT5363BIMG B04C MAC-CI G34 CI_MIVAL CI_MISTRT CI_MCLKI AO CI_MDIO B04C CONTROL IF_AGC M31 AGC_IF AGC_RF M33 RF_AGC PX1 PX1 RXO ASIC_CS 7L00 ISL24016IRTZ B05 HDMI-LVDS H33 F35 H35 1KA1 60 79 78 72 61 1N01 1

+5VTUN_DIGITAL

B02A DIGITAL DEMOD

B04D LVDS DISPLAY

+B

5208

1201 VA1E1BF2403

7302 TC90517FG

B04C

RESET_DEMOD

42

TUNER
TSO_CLK

58 TSO_VALID DIGITAL DEMODULATOR 59 TSO_SYNC

IF_OUT+

10

61

IF_OUT-

11

DIF_P

30

SCL

7 SDA 9 IF_AGC

(I2C)

60 TSO_DATA0 AGCCNTI 9

LEVEL SHIFTER

RF_AGC

7218

B04C

RF_AGC_SW

7217 RF_AGC_SW

T01D P GAMMA &

VCOM & NVM
7K00 ISL24837IRZ VL/VH

2 1 1KA2 81

B06C ANALOG I/O - VIDEO

Y0N SOY0 Y0P PB0P PR0P PBR0N SOY1 Y0P AR28 AP29 AU30 AK22 AP25 AU26 Y1P AT27 PB1P PR1P Y1N AP27 AR26 PB0P PR0P AT29

B06B ANALOG I/O

AUDIO

SOY0-AV1

3B08

1C01

12

SC1_G

5C05

3C24

SY0P

3B07

MT5363

REF VOLTAGE GEN

VGL_-6V VGH_35V

79 78 72 VH RLV(0-7) 61 50 TO DISPLAY 13 34 VCC_3V3 VLS_15V6 VL 33 12 11 10 2 1

CVI-1

PB

SC1_B

5C04

3C23 SPB0P

3B09

SC1_CVBS_OUT

5C03

3C21 SPR0P

3B11

PR

1C02

SOY1-AV2

3B00

12

SY1P_SC2

5C02

3C25

SY1P

3B01

CVI-2

PB

PB1P_SC2

5C01

3C22

SPB1P

3B03

PR1P_SC2

5C00

3C20

SPR1P

3B05

2C06

PR

SY1N

3B02

1C03 B04C CONTROL AP35 CVBS_2P CVBS_0N USB_DM USB_DP AR36 AR10 AU10 USB_DM USB_DP

AVIN

CVBS

CVBS_AV3

B05B USB
1D01 1 2 3 4
3 2 4 1

2C07

GND_CVBS

B06D VGA
RP GP BP HSYNC VSYNC SOG SOG COM PDD GN AR24 AP23

1E01

USB 2.0 CONNECTOR SIDE SW UPLOAD JPEG MP3

VGA_R

VGA_Rp

10

15

VGA_G

VGA_Gp

VGA_B

VGA_Bp

B04C CONTROLLER
7708 H27U1G8F2BTR

H-SYNC

11

3 13 14

V-SYNC

AT25 RP AU24 GP AT23 BP AR22 HSYNC AU22 VSYNC NAND_PDD(0-7)

2E08

VGA CONNECTOR

2E03

FLASH 1Gb

B05A HDMI & MUX

B05 HDMI-LVDS M_RX2_2 M_RX2_2B M_RX2_1 AU18 AP17 RX1 AT17 AR16 AU16 M_RX2_1B M_RX2_0 M_RX2_0B M_RX2_C M_RX2_CB B04B DRAM

1902

1 AP19 AT19 AR18

B04B DDR
RDQ RDQ(0-31)
7600 H5PS5162FFR 7601 H5PS5162FFR

1 2

4 6 7

19 18

RDQ(0-15)

HDMI 2 CONNECTOR M_RX1_2 M_RX1_2B M_RX1_1 AU14 AP13 RX2 AT13 AR12 AU12 M_RX1_1B M_RX1_0 M_RX1_0B M_RX1_C M_RX1_CB

12

SDRAM 512Mb

RDQ(16-31)

9 10

SDRAM 512Mb

1901

1 AP15 AT15 AR14

VDD

1 2

A1 RA RA(0-13)

4 6 7

VDD
A1 +1V8_SW

19 18

9 10

HDMI 1 (SIDE) CONNECTOR

12

19130_020_110427.eps 110427

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Block Diagrams L11M1.1L LA 9. EN 38

Block Diagram Audio AUDIO

B04
MT5363: ANALOG I/O - AUDIO CLASS-D & MUTING
7700 MT5363BHMG B04C MAC-CI B06B ALI_ADAC G34 CI_MIVAL CI_MISTRT CI_MCLKI CI_MDIO AL_L AR_R u36 6 7 6 GND-AUDIO 15 RIGHT_SPEAKER PREAMPR AOUTR B04C CONTROL M31 AGC_IF AGC_RF B04C B04C B04C B06B ALI_DAC B04C SW_MUTE STANDBY 2 7408 DC_PROT DC-DETECTION RESET_AUDIO A_STBY MUTE 4 M33 V37 2 1 5 PREAMPL 22 LEFT_SPEAKER AOUTL 7B01 7400 TPA3123D2PWP H33 F35 H35

B02A

TUNER

+5VTUN_DIG

B02B

DIGITAL DEMOD

B06B

B03

5207

1201 VA1E1BF2403

+B

7302 TC90517FG

TUNER
1735 1 2 3 4

B04C

RESET_DEMOD

42

58 TSO_VALID DIGITAL DEMODULATOR 59 TSO_SYNC

IF_OUT+

10

DIF_N

29

61

TSO_CLK

IF_OUT-

11

DIF_P

30

(I2C)

60 TSO_DATA0 AGCCNTI 9

SPEAKER LEFT

SCL 7 SDA 9 IF_AGC

IF_AGC

RF_AGC

7218

RF_AGC

CLASS D POWER AMPLIFIER

SPEAKER RIGHT

B04C

RF_AGC_SW

7217 RF_AGC_SW

B06C
AD33 AIN_AADC_0_L AIN_AADC_0_R AC34

ANALOG I/O - VIDEO

1C01

AIN0_L-AV1

CVI-1

MT5363
B04C CONTROL

AV IN AUDIO L/R

AIN0_R-AV1

1C02 AB31 AIN_AADC_1_L AIN_AADC_1_R 1D01 1 USB_DM USB_DP 4 AR10 AU10 2 3 USB_DM USB_DP
3 2 4 1

5 AC32

AIN1_L-AV2

CVI-2

AV IN AUDIO L/R

AIN1_R-AV2

B05B
USB

1C03 AA36 AIN_AADC_6_L AIN_AADC_6_R Y37

SAV_L_IN

AVIN

USB 2.0 CONNECTOR SIDE SW UPLOAD JPEG MP3

AV IN AUDIO L/R

SAV_R_IN

B04C

CONTROLLER
7708 H27U1G8F2BTR

B06B
AC36 AIN_AADC_3_L AIN_AADC_3_R PDD NAND_PDD(0-7) AB37

ANALOG I/O - AUDIO

1B01

DVI_AUL_IN

AV IN AUDIO L/R

DVI_AUR_IN

FLASH 1Gb

+3V3

1B02 K33 ASPDIF B04B DRAM B05 GPIO E28 GPIO_12 ASPDIF RDQ B05 HDMI

SPDIF OUT

SPDIF_OUT

7S09 74LVC00 2 3 & 1

ASPDIF_OUT

B04B

DDR
RDQ(0-31)
7600 H5PS5162FFR 7601 H5PS5162FFR

eHDMI+

ARC_SW

B05A
AP15 AT15 AR14 AU14 AP13 RX1 AT13 AR12 AU12

HDMI & MUX

1901

M_RX1_2

RDQ(0-15)

1 2

4 6 7

M_RX1_2B M_RX1_1

M_RX1_1B M_RX1_0

SDRAM 512Mb

RDQ(16-31)

SDRAM 512Mb

19 18

VDD

HDMI 1 (SIDE) CONNECTOR

12

M_RX1_CB

A1 RA RA(0-13)

14

VDD
A1 +1V8_SW

9 10

M_RX1_0B

M_RX1_C

1902

1 AP19 AT19 AR18 AU18 AP17 RX0 AT17 AR16 AU16

M_RX2_2

1 2

4 6 7

M_RX2_2B M_RX2_1

M_RX2_1B M_RX2_0

19 18

9 10

M_RX2_0B

M_RX2_C

HDMI 2 CONNECTOR

12

M_RX2_CB

19130_038_110427.eps 110427

2011-Apr-29

Block Diagrams L11M1.1L LA 9. EN 39

Block Diagram Control & Clock Signals CONTROL + CLOCK SIGNALS

B04B
DDR
7H01 VPP1501BFG

B04
TCON CONTROL
B04B DRAM RDQ LLV(0-7) T01F
7600 H5PS5162FFR 7601 H5PS5162FFR 7H00 H5PS5162FFR

MT5363

7700 MT5363BIMG

T01B

RDQ(0-31)

TCON CONTROL
TDQ(0-15) TA(0-12) TCK L2 L1 A1 OSC_IN SLOPE T16 GSLOP RLV(0-7) T01F TCK#

RDQ(0-15)

MT5363
J8 K8 B1 OSC_OUT RA RA(0-13) AD1 AD3 T01D T01D 50Hz_60Hz U9 RTC50_60 CS T9 RST B3 A2 RCLK0# RCLK0 RCLK1# RESET ASIC_CS RCLK1 CLK CLK CLK CLK J8 K8 1H00 27M

SDRAM 512Mb
T01C

RDQ(16-31)

SDRAM 512Mb

SDRAM 512Mb

T01E

MPD

7L00 SL24016IRTZ

LEVEL SHIFTER

CS(1-12)

T01F

B04C B04C
FLASH & EJTAG & DISPLAY INTERFACE
EDID_WC B06 B07E B04C B01A B01A ARC_SW B06B LCD-PWR-ONn LAMP-ON POWER-OK
7K00 ISL24837IRZ

CONTROLLER P GAMMA & VCOM & NVM

GPIO_7 GPIO_35 GPIO_43 GPIO_41 GPIO_12 E28 AG4 AH3 A22 H29

B04C GPIO

T01D

B08C

BYPASS_MODE

B23

GPIO_32

B02A

RF_AGC_SW

B29

GPIO_9

B03

DC_PROT

AG6

GPIO_42

B06D

USB_PWR_EN

G30

GPIO_5

VH VL

T01F T01F

B06D

USB_OCP

E30

GPIO_6

B02B

RESET_DEMOD

A30

GPIO_3

2701

B25

P GAMMA
25 OUTCOM OUT12 26 OUTCOM INCOM

GPIO_26

SDM 2700 7708 H27U1G8F2BTR

A26

GPIO_21

VCOM

PANEL

VCOM BUFER

T01F

B04C CONTROL PDD NAND_PDD(0-7)

FLASH 1Gb
OUT12

24

CS_L

T01E

AJ36
1701

XTAL1 U0_RX U0_TX 1 7710 OPWRSB AL20 STANDBY B01

AT21
3 2

1700 54M

AJ34

AP21

XTALO

UART SERVICE CONNECTOR

1M20 3 HDMI_CEC OPCTRL_0 OPCTRL_4 OPCTRL_3 AR20 AU20 AM21 AN14 HDMI_CEC POWER_DOWN MUTE SW_MUTE

RC

AN22

OIRI B05A B04C B03 B03

TO IR/LED PANEL AND KEYBOARD CONTROL

+3V3STBY

LED-2

AM37

ADIN_SRV_4

KEYBOARD

AM35

ADIN_SRV_2

B06D

USB
7D00 TPS2041BD OUT EN OC USB_PWR_EN USB_OCP B04C B04C 1D01 1

LIGHT-SENSOR

AL36

ADIN_SRV_5

USB_DM0 USB_DP0

AK5

USB_DP0

3 2

+3V3STBY 7701 BD45292G 5 VDD 4 VOUT

ORESET

AL22

ORESET

AJ5

USB_DM0

2 3 4

3 19130_045_110428.eps 110429

2011-Apr-29

USB 2.0 CONNECTOR SIDE

Block Diagrams L11M1.1L LA 9. EN 40

Block Diagram I2C

B06D
VGA CONTROLLER DC_5V

IC
B04C

B04C

CONTROLLER

7700 MT5363BIMG 1E01

10 15 5

+3V3_SW
3E21

3718

3719

B04C
1

CONTROL 15
6

12 SDA_VGA SCL_VGA 4817 4E02

4E03

3E22

4818

AP1
11

SDA-MAIN

OSDA_0

OSCL_0

AP3

SCL-MAIN

3717

7703 7E00 M24C02 EEPROM 7E01 B04C EDID SW +3V3STBY EDID_WC 7 4814 I2C SWITCH 4816 7801 PCA9540BDP

3716

VGA CONNECTOR
5 6 7 8

6 1G51 SDA_VCOM SCL_VCOM 50 49

GPIO_44

AH1

SYS_EEPROM_WE

7708 H27U1G8F2BTR

7702 M24C64

MT5363

EEPROM (NVM)

TO TCON

PDD

NAND

FLASH 1Gb

ERR 15

MAIN NVM SW
3746 3747

U0_RX 3748 2 1 UART SERVICE CONNECTOR

AT21 3

3727

3749

1701

U0_TX

AP21

3728

B2B B02A
TUNER

DIGITAL DEMOD

+3V3STBY LVDS DISPLAY

T01A

T01D

P GAMMA & VCOM & NVM

3746

N34 1N01
3352 3351

3747

VCC_3V3

TUNER_DATA 2 SDA-TCON SCL-TCON 45 14 12

3228 3230

TUNER_SDA
3K40 3K41

TUNER_CLK

N36

TUNER_SCL

1KQB 1 2 B04C 12 13 RES 7K00 ISL24837IRZ BYPASS_MODE 4

B04B DRAM 46 7302 TC90517FG FE_SDA FE_SCL DIGITAL DEMODULATOR 7 1201 VA1E1BF2403 MAIN TUNER
ERR 16

B4B

DDR

TO SSB
3

RDQ

RDQ(0-31) 7600 H5PS5162FFR

7601 H5PS5162FFR

SDRAM 512Mb
6

SDRAM 512Mb

VOLTAGE GENERATOR

RA

RA(0-13)

B05A
1901 16 15

HDMI & MUX

HDMI_PLUGPWR2

T01B

TCON CONTROL

VCC

3907

3908

3K54

HDMI_SDA2

3K53

AL14

SIDE_HDMI_SDA1

1KQA ROM_SDA ROM_SCL

3K56 3K55

2 1

HDMI_SCL2

AL12

SIDE_HDMI_SCL1

HDMI 1 (SIDE) CONNECTOR

HDMI_PLUGPWR2

3915

3916

1902 16 15 6

U8

T8

6 7 7H01 VPP1501BFG TCON CONTROL 7K04 M24C64 EEPROM RES B08A WP_TCON RESET 3 4 SW SW

HDMI_SDA1

AN18

HDMI_SDA2

HDMI_SCL1

AM17

HDMI_SCL2

HDMI 2 CONNECTOR

Programmable via USB Programmable via ComPair

7900 M24C02

7901 M24C02

EEPROM

EEPROM

EDID SW

EDID SW DEBUG ONLY

19130_011_110426.eps 110426

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Block Diagrams L11M1.1L LA 9. EN 41

Supply Lines Overview

B05A
HDMI & MUX
1N01 B01 47 +2V5_SW B01 +1V25_SW B01 +3V3_SW B01 HDMI 2 CONNECTOR VCC_3V3 T01c PWR5V_1 5H03 VCC_1V8 T01c 5H02 VDD3V3LVRS VDD3V3IO VCC_1V8 5H00 5H01 +24VAUDIO B01 5H05 5H06 B03,B04a,c,d, B05a +24VAUDIO +5V_SW +5V_SW VDD1V8 VDD1V8PLL DDR2VDD 1901 18 1902 18 PWR5V_2 +3V3_SW 6901 HDMI_PLUGPWR2 +1V25_SW 6900 HDMI_PLUGPWR1 +5V_SW TO 1G51 B04D SSB 48 49 50 +5V_SW +3V3STBY +VDISP-INT T01c +3V3STBY

SUPPLY LINES OVERVIEW

T01A
LVDS DISPLAY

B01 B02B
DIGITAL Demod
B04d B01 +2V5_SW

DC - DC

1M99 1

1M99 1

+12VDISP

T01B
TCON CONTROL

LAMP-ON

B04C CONTROL

VCC_3V3

BACKLIGHT-PWM

7 B01 B01 B01 B01 +12VS +12VS +5V_SW +5V_SW +3V3STBY +3V3STBY

B04C CONTROL

B03
CLASS-D & MUTING
HDMI 1 SIDE CONNECTOR

BACKLIGHT-BOOST

INV_STATUS

POWER-OK

B04C CONTROL B06D CONTROL

B05B
USB

MAIN POWER SUPPLY

B04A
MTK POWER
+1V25_SW B01 T01c B01 +1V1_SW SENCE+1V1_MT5363 +3V3STBY B01 +1V8_SW B02b,B04a,c,d, B06a,B06b B01 +3V3-ARC SENCE_1V8 B01 B01 +12VS +12VS +3V3_SW B01 +3V3_SW T01a 4J04 B02b,B04a +1V8_SW B01 +3V3_SW +3V3_SW +VDISP-INT +3V3STBY +3V3_SW +3V3_SW +1V25_SW B01 +1V1_SW B01

1M99 1

1M95 1

+3V3STBY

STANDBY

B06A
ANOLOG I/O - HEADPHONE
VGH_35V

5H04 VGH_35V

B04A CONTROL

6 B03,B04c,B06b

+12VS

B06B
ANALOG I/O - AUDIO

T01C

TCON DC/DC

+3V3_SW

7120

+VDISP-INT +VDISP 7J01 5J06 T01d,e VLS_15V6_B 4J01 VLS_15V6 T01f,d

7122 RT8283AHGSP 5117 2 5121 Synchronous 3 Step-down Converter

IN OUT COM

+1V25_SW

+5V5_TUN B02a

7123 RT8283AHGSP 5120 2 Synchronous 3 5104 Step-down Converter

6122

+5V_SW B02a,B03.B04c, B06d,B05a,b B01 +1V8_SW B01 B02b VGA CONNECTOR 1E01 3E13 9 6E05 5E03 +1V8_SW +5V_SW

B04B
DDR

B06D
VGA

+5V_SW DC_5V

7J00 ISL97653 10

3J10 3J26

VGL_-6V VGH_35V VCC_3V3 VCC_1V8 T01b,d,f T01b T01f T01b,f 6J02 4J02 LCD 21 SUPPLY 3,4 5J00 3J12 39

7120

IN OUT COM

+2V5_SW

B04C
CONTROLLER
+3V3_SW B04a,b B01 +3V3STBY B01 B04a B01 1M20 5 5706 8 +12VS B03 B01 +12VS TO IR/LED PANEL +5V_SW +5V_SW +3V3STBY +3V3_SW

+1V8_SW

7124 RT8283AHGSP 5115 2 5123 Synchronous 3 Step-down Converter 7125 RT8283AHGSP 5105 2 5106 Synchronous 3 Step-down Converter 6102 3130

+1V1_SW

T01D
T01c T01c

P GAMMA & VCOM & NVM

EN_1

VCC_3V3 VLS_15V6

VCC_3V3 VLS_15V6

+24VAUDIO

10

10

VREF_15V2 T01e +VDISP +VDISP T01c

11

11

GND-AUDIO

N.C. +12VDISP B01 7800 5801 5800 +VDISP-INT 1 TO 1N01 T01A TCON 1G51 +12VDISP

B04D
LVDS DISPLAY

7K00 ISL24837IRZ 32 VOLTAGE GENERATOR

SENSE+1V0_MT5363

SENSE+1V1_MT5363

T01E
T01d T01c

MPD
VREF_15V2 VREF_15V2 +VDISP +VDISP

B04a

SENSE_1V8 +3V3STBY B01 +3V3_SW B01

SENSE_1V8

7802 LCD-PWR-ONn
5802 +3V3STBY +3V3_SW

2 3 4

B04a

B02A

TUNER

B01

+5V5_TUN

+5V5_TUN T01c B08c

T01F
VGL_-6V

MINI LVDS
VCC_3V3 VCC_3V3 VGL_-6V VGH_35V T01c T01c VLS_15V6 VGH_35V VLS_15V6

7216

IN OUT COM

5225

+5VTUN_DIGITAL

B01

+5V_SW

+5V_SW

5222

+5VS

19130_005_110426.eps 110426

2011-Apr-29

Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 42

10. Circuit Diagrams and PWB Layouts

10-1 B01 393912365052

DC-DC

DC-DC
7122 RT8283AHGSP 2 VIN EN SS 3140 22u 2101 VIA
I136

B01A
BOOT SW FB 22u 2152 6 5 4K7 1% 2162
3126 3127 3128 68R 68R 68R I117

12V/3V3 CONVERSION
1
+12VDISP

5117 3149 1R0 100n

+3V3_SW F133

I105

2170 5121 10u 100u 6.3V RES

F102 F103 F104

1M99

B01A
1 2 3 4 5 6 7 8 9 F105 F106 F107 F108 F109 LAMP-ON BACKLIGHT-PWM BACKLIGHT-BOOST INV_STATUS POWER-OK

33R 7 3 I137 8 10 2179 100n COMP GND GND HS 9 3n3 2160 RES
3138 10R
2041145-9

3100

EN_1

10u

2154

2163 RES

10u 16V

2100

10u

2158

100K

22n

1M99 PIN ON 1 12V 5 3V 6 >1.5V 7 1.5V 9 3V STBY 0V 0V 0V 0V 0V

SS1_GND

3146

I106

I118

100K 5% 3107

1K5 1%

100p

100p

100p

RES

2150

470p

2126

100n 2125

3135

2127

2128

2132

2133

2134

SS1_GND F135
+5V5_TUN +3V3STBY

12V/5V CONVERSION
BOOT
3129 68R

7123 RT8283AHGSP 1 3
10u +5V_SW SS36 1M95

+12VS

2 1R0 100n I138

6122 5104 F132

VIN SW
1n0

2136

+12VS

1n0

5120 3150 2123

I123

2131

2135

SS1_GND SS1_GND

RES 4100

100n

SS1_GND

12K

100p

100p

100p

10n

2198

SS1_GND

10n

33R 5 10u 22u

2164 10u 2159

EN_1 RES 2169 10u 2199

2137

3101

STANDBY

7 FB 470R 3154 470R 22u 2155 RES 3155 470R 6 2161 3153
I122

EN

10u

2102

2168

RES 2171

10u 2153

10u

10u 16V

1n0

100n

COMP GND GND HS 9 3n3 2185

3136

100u 6.3V 3115

VIA RES
10R

27K 1%

10

RES 2180

2146

2u2

2157

100K 22n

I120

SS

+12VS

2177

SS2_GND

1M95 PIN 1 2 6 7 8 9 ON 3V3 0V 12V 12V 12V 25V STBY 3V3 3V 0V 0V 0V 0V

+24VAUDIO GND-AUDIO

I107

I119

SS2_GND 10K
2186

I140

1 2 3 4 5 6 7 8 9 10 11 1-2041145-1

F113 F114 F115 F116 F117 F118 F119 F120 F121 F122 F123

RES

3122

470p

SS2_GND
3125

1n0

1n0

RES

2141

2142

100n

2143

100n 2144

3105

2149

100n

2148

SS2_GND SS2_GND SS2_GND

GND-AUDIO GND-AUDIO GND-AUDIO

12V/1V8 CONVERSION
BOOT SW 3u6 5 22u 2138 15K 1% 2191 22u 2183 6 RES 4n7 2112 RES
3108 10R

7124 RT8283AHGSP 1 3
+1V8_SW

5115 3151 1R0 100n

I131

I104

2 5123
F125

2187

VIN

33R

3102

EN_1 FB 3112 22u 22u

I127

2188

2172

10u 2189

10u

EN

10u 16V

2190 RES 2104 RES 2105

100K 22n 100u 6.3V

SS

I132

100K 1%

5K1 1%

6102

100n

10

3V3/1V2 CONVERSION
7119 LD1117DT 5124
+3V3_SW I144

BZX384-C6V8

VIA 9

COMP GND GND HS

2178

SS3_GND 3116
SENSE_1V8

3 33R
22u 2165

IN

OUT COM 2139 100n

I143

5125 33R 10n 22u 2193 22u 2140 RES 2166 2122 10n

100n 2147

100n

2145

1n0

F131 +1V25_SW

1K0

3130

I135

I134

SS3_GND 15K

I141

I139

12K

RES

3114

2192

470p

3113

RES SS3_GND SS3_GND SS3_GND

3131

4K7

68K 1% 3118

12K 1%

EN_1

SS3_GND

5V/2V5 CONVERSION
7120 LD1117DT25 5127
+5V_SW I125

12V/1V0 CONVERSION
BOOT SW FB 22u 2129 6 3106
I111

22u 6.3V 2197

7125 RT8283AHGSP 1 3 5 3u6 12K 1% 2151 1R0 100n

I110

3 33R

IN

OUT COM
2107

I126

5128 33R 100n 100n 2111 2109 100n

F136 +2V5_SW

5105 3152 5106 2124

I108

VIN

3103

EN

+1V1_SW

2176

2175

10u 2181

10u

2195

100K I109

10u 16V

SS

COMP GND GND HS 9 4n7 2167 RES

3111 10R

SS4_GND

I112

I113

I142

3117
SENSE+1V1_MT5363

47K
470p

3K6

3145

2113

RES

3109

3148

SS4_GND

100u 6.3V

VIA

22u 2130

10

22u 2106

22n

DGND DGND

47u 16V 2110

F101

33R

22u 6.3V 2108

DGND

DGND DGND

DGND

27K 1%

470K 5%

ROUND 4.02mm SCREW HOLE

1X02 REF EMC HOLE 1X03 REF EMC HOLE 1X05 REF EMC HOLE

ROUND 4.50mm SCREW HOLE

1X04 EMC HOLE

SLOT SCREW HOLE

1X01 REF EMC HOLE

SS4_GND

SS4_GND SS4_GND

2 1

2011-01-31 2011-01-13

PCB SB SSB THRILLER BRZ DIG

3139 123 6505

19130_016_110426.eps 110426

2011-Apr-29

Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 43

10-2 B02 393912365052

Tuner

B02A

Tuner

B02A

7216 LD29150DT50R +5V5_TUN 1

IN COM RES
2280

OUT 4209 RES 4210 RES

I255

5225

F236
+5VTUN_DIGITAL

0R
10u 22u 10n 2279 2281

RES

1u0

2277

22u 2278

RES

2282

F242 RF_AGC_SW AGND AGND AGND

AGND

RES

AGND

+5VS

3264

10K

3265

I220 1K0

1K0
I254 +5V_SW 5222 10u RF_AGC

7217 BC847BW

RES 3272-1 10R 1 8 RES 3272-2 10R 2 7 RES 3272-3 10R 3 6 RES 3272-4 10R 4 5 3271-1 10R 1 8 3271-2 10R 2 7 3271-3 10R 3 6 3271-4 10R 4 5

I221 I222

3269

AGND
F235 +5VS

F213 RF_AGC_EX 10K 47n 2293 RES 2213 22u 3270 F247

AGND

22u

2283

1201 VA1E1BF2403

15

MT

16

AGND

2295

AGND

100p AGND AGND 3230

FE_SCL

7218 KTK5132E

AGND

AGND 10R

TUNER

RES 5207 5208 2258 15p AGND

FE_SDA

30R 4u7 100n 3228 10R

+5VTUN_DIGITAL +5VTUN_DIGITAL

2226

2284

AGND

10n

2286

ANT_PWR NC1 RF_AGC NC2 AS SCL SDA +B IF_AGC IF_OUT+ IF_OUTIF_OUT_ANALOG

1 2 3 4 5 6 7 8 9 10 11 12

F201 F202 F203 F204 F205 F206 F207 F208 F209 A212 A213 A214

AGND

180p

2285

MT

22u

RES 2296

2294

47u

14

13

DIF_N

3262 75R

5226 220n

27p 5227 220n

2287 10n

100n

VIP_ATV

RES 2297

1n0

5228

330n

AGND 10K RES 2262 100p 2263 47n

2288
IF_AGC

33p

A225 AGND 3261 F246

AGND

2225 15p

AGND

DIF_P

3263 75R 2291 180p

5229 220n DIF_N DIF_P

5230 220n 2290 27p

2289 10n

VIN_ATV

AGND AGND

Near Tuner

Near MTK5363

2 1

2011-01-31 2011-01-13

PCB SB SSB THRILLER BRZ DIG

3139 123 6505

19130_017_110426.eps 110426

2011-Apr-29

Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 44

Digital demodulator

B02B
+1V25_SW I300 5302 30R 100n 2308 100n 2309 100n 2306 100n 2307 2310 1u0 I301

Digital demodulator

B02B

+2V5_SW

5307

30R

1u0 2321

100n

2320

2322

10n

+3V3_SW I302 I303 DGND DGND DGND DGND DGND 30R 2301 100n 2302 100n 100n 2303 100n 2304 2305 1u0 5301

5306

AGND AGND

AGND

30R

2318

1u0 2323

100n

+1V25_SW I304 I305 DGND DGND DGND DGND DGND 30R 2311 100n 2312 100n 2313 1u0 5303

5304

AGND AGND

30R

2314

1u0 2324

100n

+2V5_SW I306 DGND DGND 30R FOR DEVELOPMENT USE 1u0 DEB 6301 SML-310 DEB 3355 +3V3_SW 1K0 2317 100n 2316 DGND 5305

DGND DGND

1 DEB 7301 BC847BW

1301

18p

4 2

2333

2334

18p

25.4M

DEB 3356 32 22 34 48 20 16 36 56 63 13 35 49 64 43 DGND DGND 1K0 FIL AGND 58 3354 33R 53 54 55 59 3357 33R 52 61 60 3359 33R 38 9 10 51 2332 42 100n I325 3339 IF_AGC 20K TSO_DATA0 3358 33R TSO_CLK TSO_SYNC 3353 33R I320 TSO_VALID DGND 21 2335 1n5

7302 TC90517FG VDDC

AGND I X O 0 XSEL 1 RLOCK P ADI_AI N RSEORF SBYTE SLOCK P AD_VREF N SRCK SRDT STSFLG1 AGCCNTI AGCCNTR STSFLG0 SYRSTN AGCI CKI AGND +3V3_SW SCL SDA SCL TN SDA VSS 4 15 33 37 44 47 50 57 62 23 31 17 PLLVSS AD_AVSS AD_DVSS 12 14 SLADRS 0 1 6 5 AD_VREF DTCLK DTMB S_INFO 0 TSMD 1 P ADQ_AI N RERR PBVAL

DIF_P

3 2

DGND

RES 5308

1n2 RES 2341

100n

2339 2340

1u0 1u0

30 29

DIF_N

2377 2378

100n 100n

28 27

3331

2K7 3332

2K7

AGND

2336 2337

100n 100n

24 25

AGND

2338

100n

26

AGND AGND

AGND

39

DGND

+3V3_SW

40

DGND

3349

10K

1 41

3337

10K

I316

11

TUNER_SCL TUNER_SDA

F300 F301

3351 3352

100R 100R

I317 I318

45 46

AD_DVDD

AD_AVDD

18

DR1VDD

DR2VDD

I308

PLLVDD

AGND

I307

19

)
VDDS

39p

RES 2379

39p RES 2380

AGND AGND DGND DGND

F306

3350

4K7

RES
RESET_DEMOD

5309 3360 4K7 33R 4306 4312

DGND

DGND

DGND

3335

10K 3336

10K

DGND 4308

4307 4313 4309 4314

+3V3_SW

4310 5310 2K7 3344 3343 2K7 33R I338

4311 AGND 5311 33R

F302 F303

FE_SCL FE_SDA

AGND

DGND

2 1

2011-01-31 2011-01-13

PCB SB SSB THRILLER BRZ DIG

3139 123 6505

19130_018_110426.eps 110426

2011-Apr-29

Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 45

10-3 B03 393912365052

Class-D & muting

Class-D & muting

+24VAUDIO

B03
5400 5401 F400 I411 GND-AUDIO 22K 22K 2402 220n 22K 22K LEFT_SPEAKER I412 220R 220R

B03

+24VAUDIO

3400

4R7 2401 2400 220n 2403

1K0

2405

220n

3452

3451

1K0

1402

220u 35V

220u 35V

10u 35V 2404

V_NOM

2419 10n

2413

220n 2414

220n

1735 F404 F405

LEFT + GND SND

GND-AUDIO GND-AUDIO 3405-3 3405-4 3405-2 3405-1 GND-AUDIO 10n 1K0 3453 1K0 3454 2420

F406 10n

1 2 3 4

GND SND RIGHT -

19 20

1 3

AOUTR 47n PVCC BSR R OUT L 0 GAIN 1 BSL 220n 21 22u 35V 220u I414 2412 I418 LEFT_SPEAKER 22 I416 5403 2416 15 22u 35V 220u 220n I417 RIGHT_SPEAKER 16 I415 5402 2415 RIGHT_SPEAKER 6 R IN L 2407 I403 5 18 17 11 7 4 2 VCLAMP BYPASS MUTE SD 22K 22K 22K AGND GND_HS 7 25 5 6 8 100K 2417 220n 2418 220n 8 9 23 24 13 14 L R 22K PGND 2433 1u0 3422-4
F410

AVCC

R I413 2411

1403

47n

GND-AUDIO

2408 1u0 I405 2409 1u0 I406

MUTE

F411

3422-3 100K 3422-2

I434

A_STBY

F412

DC_PROT

40 39 38

GND-AUDIO 4 3 2 1 3422-1 100K

100K
2426 10u 7408 BC847BW

7400-2 TPA3123D2PWP 3406-4 3406-3 3406-2 3406-1 GND-AUDIO

VIA

GND-AUDIO
+12VS

26 27 28 29 GND-AUDIO

VIA

VIA

37 36 35 34

2427

1u0

VIA

GND-AUDIO

GND-AUDIO
GND-AUDIO

GND-AUDIO

VIA

30 31 32 33

DC-DETECTION

+12VS

F408

I424

3412

F416 I440

3418

1K0

GND-AUDIO F415

+5V_SW

4n7

RES

I435

7402-1 BC857BS(COL) 7403 BC847BW 3 F409 4401 1

47K 1 3433

RES RES
10K 7411 RES BC857BW 3432 3 1K0 I436

RES 6400

BAS316

3411 2 4n7

I425

3413

I433

2430

3430

RES

47K

1K0

RES
3431

RESERVED

RES
7412 2SD2653K
HP_LOUT

3410

4K7

RES

I422

4 7402-2 BC857BS(COL) 47K 3426 6402 BAT54C 47K 2 I431 7406 2SD2653K 1 3419 10K 3428 1K0 7404 3 BC857BW I429

I430

I442

56K

470u 16V

2424

3420

RES 3409

I423

2422

4K7

1K8

HP_ROUT

4n7

47K

RES 3408

RES

F413
+3V3STBY 7405 BSS84

6401

BAS316

AOUTL

RES

2431

3434

47K

RES 3435
AOUTR

RES 3416

100K

I437 1K0

RES
7413 2SD2653K

RES 3414

100K

1R0 4n7

2 RES
2425

I441

RES 3415 3421

SW_MUTE 3417 10K

F414 2423 100n

1
3427 1K0 I432

+3V3STBY

47K

7407 2SD2653K

F417

3K0

3439

10K

RESET_AUDIO

I445

3437

I443

3438

22K 2432

1u0

A_STBY

7414 BC847BW

BAT54C 6403

V_NOM

AOUTL

F402

CLASS-D AUDIO AMP

2421

7400-1 TPA3123D2PWP 10 12

F401 2406 I401

2041145-4

2 1

2011-01-31 2011-01-13

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19130_019_110427.eps 110427

2011-Apr-29

Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 46

10-4 B04 393912365052

MT5363 Power

B04A
+3V3_SW

MT5363 Power

B04A

5506 30R

7700-8 MT5363BIMG
F503

F502 +1V25_SW 30R 100n 100n 100n 100n 100n 100n 100n 100n

5500

POWER-MAIN
VCCIO33 DVSS

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

2567

4u7

2514 4u7

+3V3_SW 2516 2518 2520 2517 2521 2515 2561 2562 2563 2560 2564 2565 2566 2519 2522

2553

2552

2558

2559

H23 H31 J30 V31 W32 W34 W36 AF13 AF15 VCCIO33-1 DVSS

5501

30R

F500

3500
+1V8_SW 2598

4u7

VCC2IO DVSS

100n

100n

100n

100n

100n

I504

1R0 7700-7 MT5363BIMG

2588

4u7

2571 1u0

2573 100n

2568

2577

2576

2575

2574

POWER-MISC
VCC2IO
4u7 100n 100n 100n 100n

SENSE_1V8

2501

2502

2503

2504

2500

2505

2506

AVDD12 AVSS12 VCC2IO

2507

22u

100n

100n

AM23

AVDD10_LDO

DVSS

100n

100n

100n

2581

2584

2582

2580

100n

LVDS MEMPLL PLL_1 PLL_2 RGB USB VPLL VCC2IO

P17 T13 AH29 AH31 AN26 AM9 P19

DVSS

100n

100n

100n

100n

AVDD33 AVSS33
2508 2510 2509 2512 2513

100n

AH33 AG30 AP11 N16 P13 AM25 AG32 AF29 AL10 N18 VCC2IO

ADCPLL APLL HDMI LVDS MEMPLL RGB SYSPLL TVDPLL USB VPLL

DVSS

I505

B1 B13 C2 C12 D3 D13 E4 E12 E14 F5 F13 G6 G14 H7 J14 R2 R4 R6 AC6 AD5 AD7 AE2 AE4 AF1 AF3 DVSS

5502 5503

30R 30R

I506

5504 30R

DVSS VCCK

1u0

2597

5505 30R

2569 100n

2570 100n

2593

100n

I502

2599

2592

1u0

1u0

+3V3STBY

+3V3STBY

2595 2596

10u 100n

DVSS VCCK

I507

Y31 AF33 T31 AN32 AG34 AK31 AM13 F15 H15 W30 AL30 AM11 AN30 AN24 AK35 AADC ADAC0 ADAC1 CVBS DEMOD1 DIG HDMI LVDS REF_AADC SIF USB_1 USB_2 USB_3 VDAC VGA_STB XTAL Y33 AE34 U30 AR32 AG36 AJ30 AN12 J18 Y29 AK29 AP9 AT9 AT11 AR30 AL24 AK37

AADC ADAC0 ADAC1 CVBS DEMOD1 DIG HDMI LVDS_1 LVDS_2 REF_AADC SIF USB VDAC VGA_STB XTAL_STB

DVSS VCCK

2579

4u7

DVSS VCCK

SENSE+1V1_MT5363 F501

+1V1_SW

DVSS
100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n

4u7

100n 100n

2551

100u 6.3V

100n

100n 100n 100n

2540

100n

VCCK
2538 2537 2536 2535 2534 2533 2532 2531 2530 2529 2528 2527 2526 2525 2524 2523

2550

2549

2545 2544

2543 2542 2541

DVSS VCCK

DVSS VCCK

R16 U14 V13 Y13 Y15 AA14 AD15 AD17 AD19 AE14 AE16 AE18 AG12 AH7 AJ6 AJ8 AK5 AK7 AL2 AL4 AL6 AL8 AM1 AM3 AM5 AM7 AN2 AN4 N22 N24 T25 V25 W24 Y25 AA24 AB25 AE20 AE22

C8 D9 E8 F9 G8 G10 J4 J6 L4 L6 N14 P15 R14 R18 T15 T17 T19 U16 U18 V15 V17 V19 W4 W6 W14 W16 W18 Y3 Y17 Y19 AA16 AA18 AB13 AB15 AB17 AB19 AC14 AC16 AC18 AD13 AE8 AF9 B21 D21 E22 G22 N20 P21 P23 P25 R20 R22 R24 T21 T23 U20 U22 U24 V21 V23 W20 W22 Y21 Y23 AA20 AA22 AB21 AB23 AC20 AC22 AC24 AD21 AD23 AD25 AE24

2 1

2011-01-31 2011-01-13

PCB SB SSB THRILLER BRZ DIG

3139 123 6505

19130_021_110427.eps 110427

2011-Apr-29

Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 47

DDR

B04B
+1V8_SW
100n 100n 100n 100n 100n 100n 100n 100n

DDR

B04B

+1V8_SW

3622

F602

1K0 1% 2608 47u 16V

7700-3 MT5363BIMG

2630

100n 3623

1K0 1%

DRAM
2600 2603 2605 2606 2601 2602 2604 2607

N8 P7 A1 E1 J9 M9 R1 7600 H5PS5162FFR-G7C VDDL VDD VDDQ J1 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9

1 RVREF 2

)
3604-1 56R 3600-3 56R RBA(2) NC A2 E2 L1 R3 R7 R8 RA(13)

RODT RCKE RWE# RCS# RRAS# RCAS# ODT CKE WE CS RAS CAS

3605-2 3603-2 3603-1 3605-4 3605-3 3600-1

56R 56R 56R 56R 56R 56R

K9 K2 K3 L8 K7 L7

SDRAM

RA(0) RA(1) RA(2) RA(3) RA(4) RA(5) RA(6) RA(7) RA(8) RA(9) RA(10) RA(11) RA(12) RA(13) RBA(0) RBA(1) 0 BA 1 3603-4 3603-3 56R 56R L2 L3

N4 H5 M3 G4 M5 F1 M7 F3 P1 D1 G2 N2 E2 M1

0 1 2 3 4 5 6 RA 7 8 9 10 11 12 13

RBA(0) RBA(1) RBA(2) DQ

H3 J2 H1

0 1 RBA 2

RCLK0

RCLK0 RCLK0# RCLK1 RCLK1# RCKE 3612 22R 1% UDM LDM VREF J2 F600 3615 1K0 1% 100n 3614 100R F7 E8 LDQS J8 K8 CK B3 F3

B3 A2 AD1 AD3 K1

RCLK1

RCKE RCLK0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RDQ 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RA(0) RA(1) RA(2) RA(3) RA(4) RA(5) RA(6) RA(7) RA(8) RA(9) RA(10) RA(11) RA(12) 56R 56R 56R 56R 56R 56R 56R 56R 56R 56R 56R 56R 56R 56R 0 1 2 3 4 5 6 A 7 8 9 10 11 12 3600-2 3604-2 3602-4 3604-4 3602-2 3601-4 3602-3 3601-3 3600-4 3601-1 3604-3 3602-1 3601-2 3605-1 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 RDQ(0) RDQ(1) RDQ(2) RDQ(3) RDQ(4) RDQ(5) RDQ(6) RDQ(7) RDQ(8) RDQ(9) RDQ(10) RDQ(11) RDQ(12) RDQ(13) RDQ(14) RDQ(15) RDQM(1) RDQM(0)

D7 H11 E6 G12 H13 D5 F11 F7 B5 D11 A4 B11 A12 C4 A10 A6 AB1 U4 AC4 T1 T3 AC2 U2 AB3 Y5 T7 AA6 V7 V5 AA4 T5 Y7

RDQ(0) RDQ(1) RDQ(2) RDQ(3) RDQ(4) RDQ(5) RDQ(6) RDQ(7) RDQ(8) RDQ(9) RDQ(10) RDQ(11) RDQ(12) RDQ(13) RDQ(14) RDQ(15) RDQ(16) RDQ(17) RDQ(18) RDQ(19) RDQ(20) RDQ(21) RDQ(22) RDQ(23) RDQ(24) RDQ(25) RDQ(26) RDQ(27) RDQ(28) RDQ(29) RDQ(30) RDQ(31)

RODT RCS# RWE# RCAS# RRAS# RCLK0# 3616 22R 1% VSS A3 E3 J3 N1 P9 J7 RDQS(0) RDQS(0)# RDQS(1) RDQS(1)# A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 VSSQ VSSDL UDQS 3613 1K0 1% 2609 B7 A8

AB5 N6 P3 K3 L2 P5

RDQM

0 1 2 3

E10 C10 V1 U6

RDQM(0) RDQM(1) RDQM(2) RDQM(3)

REXTDN RODT RCS RWE RCAS RRAS

RDQS0

+1V8_SW

3624

100R

RDQS1

RDQS2

RDQS3

B9 A8 B7 C6 V3 W2 Y1 AA2

RDQS(0) RDQS(0)# RDQS(1) RDQS(1)# RDQS(2) RDQS(2)# RDQS(3) RDQS(3)#

+1V8_SW

100n

100n

100n

100n

100n

100n 100n

100n

2628 2622 2623 2620 2621 2624 2626 VDDQ 3609-4 2625 2627

A1 E1 J9 M9 R1

J1

7601 H5PS5162FFR-G7C VDD

VDDL

SDRAM
NC

A9 C1 C3 C7 C9 E9 G1 G3 G7 G9

47u 16V

RODT RCKE RWE# RCS# RRAS# RCAS# ODT CKE WE CS RAS CAS L2 L3 56R 56R 0 BA 1 RBA(0) RBA(1) 3610-1 3610-2

3611-3 3610-3 3610-4 3611-1 3611-2 3606-1

56R 56R 56R 56R 56R 56R

K9 K2 K3 L8 K7 L7

RBA(2) 56R 3606-3 56R

A2 E2 L1 R3 R7 R8

RA(13)

RA(0) RA(1) RA(2) RA(3) RA(4) RA(5) RA(6) RA(7) RA(8) RA(9) RA(10) RA(11) RA(12) RCLK1 3617 22R 1% 3619 100R

3606-2 3609-3 3608-1 3609-1 3608-3 3607-1 3608-2 3607-2 3606-4 3607-4 3609-2 3608-4 3607-3 3611-4

56R 56R 56R 56R 56R 56R 56R 56R 56R 56R 56R 56R 56R 56R

M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 J8 K8

0 1 2 3 4 5 6 A 7 8 9 10 11 12 CK

DQ

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 UDM LDM F7 E8 3618 22R 1% B7 A8 LDQS VREF UDQS VSS A3 E3 J3 N1 P9

G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 B3 F3 J2 F601

RDQ(16) RDQ(17) RDQ(18) RDQ(19) RDQ(20) RDQ(21) RDQ(22) RDQ(23) RDQ(24) RDQ(25) RDQ(26) RDQ(27) RDQ(28) RDQ(29) RDQ(30) RDQ(31) RDQM(3) RDQM(2) 3620 1K0 1% 3621 1K0 1% 2629 100n

+1V8_SW

RCLK1#

J7

VSSDL

VSSQ A7 B2 B8 D2 D8 E7 F2 F8 H2 H8

2 1

2011-01-31 2011-01-13

RDQS(2) RDQS(2)# RDQS(3) RDQS(3)#

PCB SB SSB THRILLER BRZ DIG

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Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 48

Controller

B04C
+3V3_SW

Controller

B04C
7700-6 MT5363BIMG F37 MOSTRT MOVAL MIVAL CI MDO0 MDI0 MCLKI C36 RES 2729 G32 F31 B33 D35 B37 10p F35
TSO_CLK

+3V3_SW

MISTRT G34
TSO_VALID TSO_DATA0

H33
TSO_SYNC

10K

10K

3700

3701

RES 37A9

10K

G36 H37 F33 MCLKO

+3V3_SW

RES H35
3726 4K7

7700-4 MT5363BIMG

CI

3704 3705

100R 100R

I700 I701

USB_PWR_EN USB_OCP EDID_WC

D37
+3V3_SW 10K 10K BYPASS_MODE LCD-PWR-ONn 5700 30R 4700 RES

RESET_DEMOD

ETMDIO ETCRS ETCOL ETPHYCLK ETMDC

F737 E36

RF_AGC_SW
10K F704 3711 F705 4K7 8 3712 2702 100n

ARC_SW 3713 3709 LAMP-ON 3715 3714

INV_STATUS

5701 F760 I741 D31 EN ER DV ETTX ETRX ER E34 CLK CLK

7702 M24C64-WDW6 ) F707 7

3732

100R +3V3_SW +3V3_SW 3710 4K7 F706 7703 BC847BW (8K 8) EEPROM 6 33R 100R

I758

D33

30R

2730

100n

+3V3_SW

10K

3703

10K

4K7

3786

+3V3_SW

WC SCL ADR SDA

4

37AA

3707

4K7

F759 100R
F736 3717 22R 5

SCL-MAIN
3716 22R

F708 I708

3796 F761
2703 10p 2704 10p

SDA-MAIN

3706

4K7

F702

+3V3_SW

F738 F739 F740

VCOM_SW POWER-OK DC_PROT

0 1 2

1 2 3

B31 E32 C32 A32 D3 D2 D1 D0

MAC-CI

D3 D2 D1 D0

C34 A34 B35 A36

F701

K35 K37 J32 A30 C30 G30 E30 H29 F29 B29 D29 C28 E28 J28 G28 H27 F27 B27 D27 G26 E26 A26 C26

GPIO 0 1 2 3 4 5 6 7 8 9 10 11 GPIO GPIO 12 13 14 15 16 17 18 19 20 21 22

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

J26 F25 H25 B25 D25 C24 G24 E24 J24 B23 F23 D23 A22 C22 AF5 AG2 AE6 AF7 AG4 AG6 AH3 AH1

SYS_EEPROM_WE

100n RES

100n

RES 2705

10n

PANEL

RES 2701

+3V3_SW +3V3_SW +3V3_SW 4K7 +3V3_SW 10K 10K 10K 10K 10K +3V3_SW

RES

2700

SDM

FOR DEBUGGING ONLY

+3V3_SW 4K7 10K I731

12

37

DEB

10K

3740 RES

7708 H27U1G8F2B
5705 220R 2713 100n 2712 100n +3V3_SW

3762

1K0

3776

3777

3778

VCC

1702

I711

1K0

1u0

2706

1700

JTRST JTDI JTMS JTCK JTDO

54M
3739 I713 BOOST_CONTROL 1R0

10p

2716

2717

10p

NAND_PDD(0) NAND_PDD(1) NAND_PDD(2) NAND_PDD(3) NAND_PDD(4) NAND_PDD(5) NAND_PDD(6) NAND_PDD(7)

29 30 31 32 41 42 43 44 0 1 2 3 IO 4 5 6 7

F751

DEB 3765
33R

DEB 3780 DEB 3763-1 DEB 3763-2 DEB 3763-3 DEB 3763-4

BACKLIGHT-BOOST

3741

F745 F746 F747 F748 F749 F750

10K

3782 RES

I742 I743
I727

F763 DEB
10K

1 2 3 4 5 6 7 8 9 10 11 13

12

DEB

NAND_PCLE NAND_PALE NAND_POCE NAND_POOE NAND_POWE

3760

3759

10K

502382-1170

DEB

NC

NAND_PARB 4K7 4K7 I732

I726

16 17 9 8 18 19 6 7 CLE ALE CE_ RE WE WP SE R B

+3V3STBY

7700-1 MT5363BIMG
RES 3779 4K7

AJ36

XTALI

CONTROL

4u7

4u7

2710

2709

6706

VDD

VCXO

RES 3774 RES 3775

7701 BD45292G

BAS316 3768

1K0

AJ34

XTALO

T37

I725 1

ER VSS 13 36
NAND_POCE NAND_PARB +3V3STBY

VOUT

F721

1 2 3 4 5 10 11 14 15 20 21 22 23 24 25 26 27 28 33 34 35 38 39 40 45 46 47 48

ORESET

0 1 2 3 PDD 4 5 6 7

AR2 AP5 AR6 AU6 AP7 AT7 AR8 AU8

NAND_PDD(0) NAND_PDD(1) NAND_PDD(2) NAND_PDD(3) NAND_PDD(4) NAND_PDD(5) NAND_PDD(6) NAND_PDD(7)

RES

6707

3769

2711

100K

100n

BAS316

SUB GND

I759 I756 I757

POCE

37A5

4K7

+3V3_SW

AL22 L30 K5 K7 M19

ORESET FSRC_WR MEMTN MEMTP TP_VPLL

0 1

AT1 AN6

PARB
NAND_PALE NAND_PCLE NAND_POWE NAND_POOE 3746 4K7 3747 4K7

AT5

4K7 4K7

4K7

RES 4K7

RES

JTCK JTDO JTRST JTDI JTMS 100R 100R 3748 3749 33R 33R F717 F718

AK3 AH5 AK1 AJ2 AJ4

JTCK JTDO JTRST JTDI JTMS

PAALE PACLE POWE POOE

AR4 AU4 AT3 AU2

3718 3719

3720 3721

3761 10K

U0

SCL-MAIN SCL-DISP

F741

AP3 R34 P31 4K7

0 1 OSCL 2

U1

RX TX RX TX

AT21 AP21 R36 T35

I744 I745

3727 3728

2 3 1 F719

1701

SDA-MAIN SDA-DISP I749

100R 4707 4708 +3V3_SW 3702 4K7 +3V3_SW 3729 10K 100R 100R 100R 4K7 4K7 3753 3754 3730 10K 10K 10K 7710 BC847BW STANDBY 3724 1R0 +3V3STBY +3V3STBY RES FOR ITV +3V3STBY 6700

F742

AP1 R32 P33

BZX384-C6V8

BZX384-C6V8

I746 RES RES

3734

LED-1

RES 3788

RES 3790
BACKLIGHT_CONTROL

LIGHT-SENSOR

3735 3737

100R 100R

I747 I755 I761

AL32 AK33 AM35 AL34 AM37 AL36

I714

LED-2

I733

0 1 2 ADIN_SRV 3 4 5

0 1 OPCTRL 2 3 4

AM21 AM19 AN20 AR20 AU20

I734 I739

3738

3744

100K LIGHT-SENSOR
+3V3_SW

KEYBOARD RESET_AUDIO

3787

100R 100R

I754 I753

3736

4K7

3758

10K

3722 3723

10K 10K

OIRI

AN22

6701

1705

1706

0 1 OSDA 2

0 OPWM 1 2

J34 J36 T33

I760

3783

MSJ-035-29D PPO UART (SERVICE)

+3V3_SW

+3V3_SW

3791 2722 1n0 100R

OPWRSB

AL20

I750

3751

RES 3731

DP DM USB VRT
3733 10K

USB_DP USB_DM

AU10 AR10 AN10 RES 37A6 RES 37A7

PWM DIMMING
RC

3742

10K

2723

1n0

CEC SDA1 HDMI SCL1 SDA2 SCL2

AN14 AN18 AM17 AL14 AL12

680R

+3V3STBY

I735

RC
7705 BC847BW I716 3745 4K7 MUTE HDMI_CEC F716 3781 I715 RES 3743 1K0

3792 100R

10K

RES 37AB

PWR5V

AL16 AM15

1M20 F753 3793 LED-2 BACKLIGHT-PWM 100R

100R

10K

RES 3757

3789

5K1 1%

POWER_DOWN SDA-LCD SCL-LCD SW_MUTE F766

TUNER

CLK DATA BYPASS

N36 N34 AP37

+3V3STBY 1n0 2724

+3V3STBY

F754 F755 F756 F757 F758 +5V_SW

+3V3STBY POWER_DOWN F725 6 3764 +3V3STBY 1K0 I737 2 3767 15K

DEMOD

TRAP0

AOLRCK

AOBCK

ASPDIF

BYPASS0 ADCINP ADCINN

AM31 AH37 AH35

LED-1 3798 6K8

7709-2 3 BC847BS(COL)

3794 2727 RES 2725 1n0 RES100R

5706 30R 100n

F765

1 2 3 4 5 6 7 8 2041145-8 2728 KEYBOARD RES

6708 I738 1 7709-1 BC847BS(COL) 4 5 3770 1K0 2721 220n 1K0 3771 F724 6709 +12VS BZX384-C8V2 3756 4K7

ICE mode + Serial Boot ICE mode +ROM mode

0 0

0 0

0 1

AGC

IF RF

M31 M33

HDMI_SDA2 HDMI_SCL2 SIDE_HDMI_SDA1 SIDE_HDMI_SCL1 F743 PWR5V_2 F744 PWR5V_1 TUNER_SCL TUNER_SDA

3795 2726
VIP_ATV VIN_ATV IF_AGC RF_AGC

47n

37A8

TRAP2 XTAL 54MHZ

2719 2720

AOSDATA0 1

OPWM1 0

2K2

47n

BZX384-C3V3

3784 3785 10K 10K

100n

TRAP1 PDWNC Normal

OPCTRL3(0) 0

10R

100n
2 1

+5V_SW

2011-01-31 2011-01-13

PCB SB SSB THRILLER BRZ DIG

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2011-Apr-29

Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 49

LVDS Display

B04D
+3V3_SW

LVDS Display

B04D

SDA-DISP

RES 4812 2802 100n 7801 PCA9540B 3 VDD SC0 SC1 SCL-VCOM
SCL_VGA

PCA5940 LVDS#1 1G51

PCA9515 - (RES)

Y Y
RES 4823 8 4 SDA-VCOM SD1 F832 4822 RES 7 4816 F833 RES 4824 4814 RES 4815 5 RES 4813

4810

4811

RES

SCL-DISP

4810 4814 4816

4817 4818
4817 1 2 VSS 6 4819 RES 4821 SDA
INP FIL I2 C -BUS CTRL

Y Y
SCL SD0

SDA_VGA

61 59 57 55 53

F801

4819 4820
4818 4820 RES

Y Y -

Y Y

4812 4815 4813

VCOM_SW

Y Y

BYPASS_MODE

4821 4822
PX1APX1A+ PX1BPX1B+

4811

Y Y Y

F805 F806 F807 F808 F809 F810 F811 F812

+5V_SW

+12VDISP

PX1CPX1C+ PX1CLKPX1CLK+ PX1DPX1D+ RES PX1EPX1E+

2803 10n

RES 4800 RES 4801 RES 4802

4803 4804 4805

F813 F814 F815 F816

5800

I801 +VDISP-INT

33R 5801

PX2APX2A+ PX2BPX2B+ PX2CPX2C+ PX2CLKPX2CLK+ PX2DPX2D+

I800

4806 RES 4807 RES 4808 RES 8 3 7 6 2 1 5

F831 F817 F818 F819 F820 F821 F822

33R 5802

33R

F823 F824 F825 F826 F827 F828 F834

7800 SI4835DDY

3802

47K 6800

BZX384-C6V8

3803

I802

2806

3805

47K

47R

1u0

PX2EPX2E+

+VDISP-INT

F829

+3V3STBY

60 58 56 54 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
2804 100n 100u 16V 2805

FI-RNE51SZ-HF-R1500

7803 BC857BW
I809

I808

3808 3809 LCD-PWR-ONn 1K0 1K0

F800

3806

15K

I806

3807

I807

10K

10K 7802-1 BC847BS(COL) 1

2807

220n 3810

7802-2 BC847BS(COL) 4

2 1

2011-01-31 2011-01-13

PCB SB SSB THRILLER BRZ DIG

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2011-Apr-29

Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 50

10-5 B05 393912365052

HDMI & Multiplexer

B05A
HDMI_PLUGPWR1

HDMI & Multiplexer

B05A
HDMI PORT 1
+3V3STBY 6902 +3V3STBY 8 RB521S-30 27K 2900 3906 100n
M_RX1_2B M_RX1_1 M_RX1_2

RES 6913 IP4281CZ10

M_RX1_1B

1 3

M_RX1_1

M_RX1_2

8 5

M_RX1_2B

6 7 I906 7900 M24C02-WMN6 1901

M_RX1_2 M_RX1_2B

9 10

M_RX1_1B M_RX1_1

)
WC SCL 7 6 SDA 5

RES 6914 IP4281CZ10 HDMI_PLUGPWR1

M_RX1_1B M_RX1_0

M_RX1_CB M_RX1_0B M_RX1_C

1 3 1 2 3 0 1 2 ADR

M_RX1_C

7908 BSH111 RES

(256 8) EEPROM

F901 F902 F903

SIDE_HDMI_SCL1

SIDE_HDMI_SDA1

3908

3K3 3907

3K3

M_RX1_0

8 5 5900 30R F915 HDMI_CEC ARC_eHDMI+ 4904 HDMI_CEC_A F914

M_RX1_CB

M_RX1_0B

F904

M_RX1_0 M_RX1_0B

6 7

9 10

M_RX1_CB M_RX1_C

eHDMI+ SIDE_HDMI_SCL1 SIDE_HDMI_SDA1

PWR5V_1 1K0 3912 21 23

EDID_WC

F905
L : WP

3901 10K DEB 3924 68K 3902 4K7

I915 7902 MMBT3904

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22
H : WRITE

10p

2902

6903

RES 6915 IP4281CZ10 4900 F900 3913 100K I902 47266-9002

CDS2C05HDMI2 5.6V

M_RX2_1B SIDE_HDMI_HPD1

1 3 RES 4901 RES 7905 MMBT3904

M_RX2_1

HDMI_PLUGPWR1 +5V_SW 1

M_RX2_2

8 5 RES 3914 4K7

M_RX2_2B

6 7

9 10

HDMI_PLUGPWR1 F913 3

RES 6916 IP4281CZ10

6900

M_RX2_2 M_RX2_2B

M_RX2_1B M_RX2_1

BAT54C

M_RX2_CB

1 3

M_RX2_C

PWR5V_1

M_RX2_0

8 5

M_RX2_0B

HDMI PORT 2 (SIDE)

1902
M_RX2_2

HDMI_PLUGPWR2

M_RX2_0 M_RX2_0B

6 7

9 10

M_RX2_CB M_RX2_C

2901

100n

)
(256 8) EEPROM
1 2 3 0 1 2 ADR SDA WC SCL 7 6 F906 F907 HDMI_SCL2

HDMI_PLUGPWR2 RES 6917

M_RX2_1B M_RX2_0

3916

3K3 3915

3K3

HDMI-LVDS
HDMI_SCL2 HDMI_SDA2

M_RX2_CB HDMI_CEC_A

7700-5 MT5363BIMG

CDS2C05HDMI2 5.6V

M_RX2_0B M_RX2_C

F908 HDMI_SDA2

F909

PWR5V_2 3919 1K0

EDID_WC 21 23 47266-9002 HDMI_PLUGPWR2

3904 10K DEB 3923 68K 3905 4K7

M_RX2_0 M_RX2_0B M_RX2_1 M_RX2_1B M_RX2_2 M_RX2_2B M_RX2_C M_RX2_CB

AP17 AT17 AR18 AU18 AP19 AT19 AR16 AU16 4902 F912 I905

0 0B 1 1B RX1 2 2B C CB

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 HDMI_CEC_A
M_RX2_2B M_RX2_1

I916

7903 MMBT3904

HDMI_HPD2

AL18

HDMI_HPD1
HDMI_HPD2

0P 0N 1P 1N 2P 2N AE 3P 3N 4P 4N CKP CKN RES 4903 RES 7907 MMBT3904 3920 100K

G16 E16 H17 F17 G18 E18 G20 E20 H21 F21 H19 F19

PX2A+ PX2APX2B+ PX2BPX2C+ PX2CPX2D+ PX2DPX2E+ PX2EPX2CLK+ PX2CLK-

RES 3921

4K7

+5V_SW 1

M_RX1_0 M_RX1_0B M_RX1_1 M_RX1_1B M_RX1_2 M_RX1_2B M_RX1_C M_RX1_CB

AP13 AT13 AR14 AU14 AP15 AT15 AR12 AU12

0 0B 1 1B RX2 2 2B C CB

HDMI_PLUGPWR2 F911 3

0P 0N 1P 1N 2P 2N AO 3P 3N 4P 4N CKP CKN

D15 B15 C16 A16 D17 B17 D19 B19 C20 A20 C18 A18

PX1A+ PX1APX1B+ PX1BPX1C+ PX1CPX1D+ PX1DPX1E+ PX1EPX1CLK+ PX1CLK-

6901

HDMI_HPD2

BAT54C

SIDE_HDMI_HPD1

AN16

PWR5V_2

3903

10K

7901 M24C02-WMN6

3900

10K
2 1 2011-01-31 2011-01-13

PCB SB SSB THRILLER BRZ DIG

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2011-Apr-29

Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 51

USB

B05B

USB

B05B

7D00 TPS2041BD 6

1
EN_

4 2 +5V_SW 3

FD04 USB_PWR_EN

USB
7

1D01 FD01 8 FD02 33R FD03 5 GND OC_ 2D12 100n 2D14 100u 16V 5D00 FD07

2 OUT 1 IN 3 2

6 1D04 1D05 6D00 1D03 2D11 10u 1 FD06 FD05 BZX384-C6V8

1 5V 2 USB_DM 3 USB_DP FD00 4 5

USB-01-PBT-B-30-CU2

USB_OCP

USB_DM

USB_DP

2 1

2011-01-31 2011-01-13

PCB SB SSB THRILLER BRZ DIG

3139 123 6505

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2011-Apr-29

Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 52

10-6 B06 393912365052

Analog I/O - Headphone

B06A

Analog I/O - Headphone

B06A

RESERVED

RES
3A04

HP_LOUT

LEFT

FA03

1R0 RES 2A02 1n0 6A01

RES

PESD5V0S1BA RES 1A03

HEADPHONE
1A01 2 RES 3 1
FA04

MSJ-035-12D-B-AG-PBT-BRF

RES
3A03

HP_ROUT

RIGHT

FA02

1R0 RES 2A01 1n0

RES

6A00

RES 3A10 22K +3V3_SW

PESD5V0S1BA RES 1A02

RES 2A05

47n

4A02 RES

HPOUTL 10K 2 1 IN2 SHUTDOWN BYPASS VO 6 5 RES 2A11 3 1u0 RES 2A04 47n IA10 10K 10K IA04 IA03 RES 3A16

FA06 IA02 1

RES 2A07 RES 3A15

VDD 1 IA09

RES 2A10

PBS_HPL

1u0

RES 7A00 TPA6111A2DGN

RES 3A11 RES 2A06 33R IA00 RES 3A12 33R IA08 100u 4V RES 2A09
FA08

RES 3A18

10K

AMPLIFIER

HP_LOUT

HPOUTR

FA07

1u0 RES 2A08

3A19

RES

RESET_AUDIO

1u0

RES 3A17

7 10 11

IA01 100u 4V

RES 3A13 33R RES 3A14

FA09

HP_ROUT

PBS_HPR

4A03 RES RES 2A12 1n0 RES 2A13 1n0

10K

VIA GND GND_HS 4 9

33R

RES 3A09 22K

2 1

2011-01-31 2011-01-13

PCB SB SSB THRILLER BRZ DIG

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Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 53

Analog I/O - Audio

B06B
7700-2 MT5363BIMG

Analog I/O - Audio

B06B
AF P N AN34 AN36 AM33 MPX

AUDIO-VIDEO

HSYNC VSYNC HSYNC VSYNC SOG RP

3B31 30K 10u RES 6B00 1R0 3B32 IB02 2B34 DVI_AUL_IN DVI_AUR_IN IB01 IB00 FB00

IB66 IB67 AR22 AU22 AP23 AT25 AU24 AT23 RES

1n0 1n0

IB10 FB02 IB12 IB13

AIN0_L-AV1 AIN0_R-AV1 AIN1_L-AV2 AIN1_R-AV2

SOG RP GP BP COM
SAV_L_IN SAV_R_IN IB03 3B34 2B37 2B35 RES 2B36

IB23 IB24

AUDIO IN
2 3 1 1B01

GP BP AR24 IB39
PR0PAU30

IB25 IB26
1B03

PESD5V0S1BA

GN

IB27

MSJ-035-29D PPO FB06

3B11

3B05

68R

2B05

10n

IB29 IB41 IB43 IB08

1R0 30K 10u 1u0

68R

2B11

10n

3B03

68R

2B03

10n

IB31 VMID_AADC IB09

3B33

3B09

68R

2B09 10n

0_L 0_R 1_L 1_R 2_L 2_R 3_L AIN_AADC 3_R 4_L 4_R 5_L 5_R 6_L 6_R AA30

AD33 AC34 AB31 AC32 AD35 AB35 AC36 AB37 AA32 AB33 AA34 Y35 AA36 Y37

SPR0P SPR1P SPB0P SPB1P SY0P SY1P AP27 PB0PAP29 AT27 Y0PAR28 AU26
100n Y0NAT29 1n0 RES 2B38 2B41 2B40

3B01

68R

2B01

10n

IB33 IB45 AR26 IB47

SOY0AU28

3B07

68R

2B07 10n

0P PR 1P 0P PB 1P 0P Y 1P

FB01

RES 2B39

SOY1-AV2 IB16
+3V3_SW

3B00

1R0

2B00

1n5

IB37 3B37 4K7 3B38

+3V3_SW FB03

3B06

1R0

2B06

1n5

AOBCK AOLRCK AOMCLK

L34 M37 M35

SOY0-AV1

AP25 AP33 AR34 AT33 AU34 IB61 ASPDIF ALIN 4K7 RES 2B16
10u

0 SOY 1 0 SY 1 0 SC 1 0 1 AOSDATA 2 3 4 K33 L32 100n RES 3B39 4K7 IB17 2B42 ASPDIF_OUT
SPDIF_OUT

PESD5V0S1BA 1n0 RES 6B01

1B04

SY0N SY1N 0 COM 1 IB14 IB15 3B35 3B36 4K7 4K7

3B02

100R

2B02

10n

IB35

3B08

100R

2B08 10n

NEAR CONNECTOR

GND_CVBS

FB08

2B15

L36 P35 P37 K31 N32

SPDIF
3B15 3B16 2B20 240R 100R 1B05 2B19 33p 33p FB04

1B02 2 FB07 1 MTJ-032-21B-43-NI

CVBS_AV3

1u0 3B14

2B14

IB63

100R

47n

AR36 AT37 AU36 AP35 AT35 0N 0P 1P CVBS 2P 3P OUT1 VDAC OUT2 IB18
2B17 10u

AP31 AT31

DEB
IB19 AM29 FS_VDAC AR
10u

0 1 AL 2 3

AF37 U32 V35 V37

HPOUTL PREAMPL

75R

RES 2B24 IB20

2B25 10u

DEB 3B58

3B47

560R

0 1 2 3 IB21 AF35 47K 47K RES 3B18 47K RES 3B17 3B48 3B49 IB22 47K

AE36 V33 U34 U36

HPOUTR PREAMPR

AVICM
1u0 2B43 2B44 100n

+3V3_SW +3V3-ARC

3B40 3B54 1R0 IB70

22K

2B50

220p

PREAMPL 2B58
AOUTL

10u 10u 47K 3B51 ASPDIF_OUT IB71

10K

IB49 5K1

2B52

820p

+12VS

LM833 7B01-1

7B05-1 74LVC00APW 1 2

14

+12VS

2B60 100n

2B51

IB48

3B41

3B50

&
3 +3V3_SW +3V3_SW

2B61 100n 7

IB72

SPDIF_OUT

3B43

47K

IB50

1u0

IB51

3B42

30R

2B53

+3V3-ARC 10K +3V3-ARC 14 7B05-2 74LVC00APW 4 ARC_SW 2B59

AOUTR

10u

2B54

3B44

47K

3B55

&
FB09 6 5 7 +3V3_SW

7B05-3 74LVC00APW 9 10

14

&
8

7B01-2 LM833

2B62 100n 7

3B56 180R

IB74

2B63 100n

eHDMI+

5 10u 3B53 47K

2B56

820p

10u

10K

5K1

2B57

220p

+3V3-ARC

3B46 +3V3_SW

7B05-4 74LVC00APW 12 13

14

&
11

22K

3B57

68R

PREAMPR

2B55

IB53

3B45

IB52

3B52

2 1

2011-01-31 2011-01-13

PCB SB SSB THRILLER BRZ DIG

3139 123 6505

19130_028_110427.eps 110427

2011-Apr-29

Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 54

Analog I/O - Video

B06C
NEAR CONNECTOR
AIN0_R-AV1
IC01 3C00 1n0 RES 2C20 RES 2C21 1n0

Analog I/O - Video

B06C
3C28
IC09 3C12 1R0

NEAR CONNECTOR
2C24 10u 6C19 RES 30K

AIN1_R-AV2
1R0 1n0 1n0 RES 2C00 RES 2C01 RES 6C00 0001 PESD5V0S1BA 1202

3C26 PESD5V0S1BA 1C14

2C22

30K

10u

AIN0_L-AV1
IC10 1R0 RES 2C18 1n0 RES 2C19 1n0 IC02 3C01 1R0 1n0 1n0 RES 2C02 RES 6C01 RES 2C03 1C16

3C29
3C13

2C25 10u

FC15

AIN1_L-AV2 RES 6C20

PESD5V0S1BA

3C27

2C23

30K

30K

10u

PESD5V0S1BA 1C15

CVI 2
FC09

CVI 1
FC10

1C02 MSP-636V1-01

IC03

SPR1P 18R
60R FC07 15p 56R

3C20 SPR0P 4 18R

2C17 3C14

5C00

1 FC08 2 3
IC11

1C01 1 MSP-636H1-01-NI 2 3
FC11

3C21

5C03 60R

4 5 6
FC12 PR_CVI1

2C04

15p 3C02

56R

5 6
PR_CVI2 FC04 PB_CVI2 FC05

RES 6C02

RES 6C08

PESD5V0S1BA 1C17

7 8 9
15p 56R

PESD5V0S1BA 1C10

7 8
FC13 PB_CVI1

56R

RES

RES 6C03

2C16

2C05

3C16

15p 3C04

PESD5V0S1BA 1C18

SPB1P SPB0P SOY0-AV1 SY0P IC21 18R

60R

18R
IC14

60R

IC16 3C25
5C02 60R RES 6C04

SOY1-AV2

SY1P 18R
2C06 15p 3C05 56R

IC17

3C24 18R
15p 2C15 56R 3C17

5C05 60R RES 6C10

SY1N

PESD5V0S1BA 1C19

IC18

3C06

SY0N

1R0

1R0

SIDE AV
3C07 CVBS_AV3 1R0 SAV_L_IN SAV_R_IN IC04

CVBS
IC19 IC20

RIGHT

1C03-1 YELLOW2

FC03

(YELLOW)

15p

1C05

RES 6C05

75R

3C08

PESD5V0S1BA

RES 2C08

2C07

47p

MTJ-032-37BAA-432 NI

GND_CVBS

LEFT 1C03-2
IC05 3C10 30K 10u 1n0 2C09

WHITE

FC02

3C09

(WHITE)

5 4 6

1R0

RES 6C06

1n0

1C06

PESD5V0S1BA

RES 2C11

RES 2C10

MTJ-032-37BAA-432 NI

NEAR CONNECTOR

1C03-3 RED IC07 10u 2C14

FC01

3C11

3C19 30K

(RED)
1n0

8 7 9

1R0

RES 6C07

1C07

RES 2C12

1n0

FC00

RES 2C13

MTJ-032-37BAA-432 NI

PESD5V0S1BA 1C08

IC22

3C18

PESD5V0S1BA 1C09

IC15 3C22
5C01 IC13

10 11 12

3C23

5C04

6C09

SY_CVI2

FC06

FC14

SY_CVI1

10 11 12

PESD5V0S1BA

2 1

2011-01-31 2011-01-13

PCB SB SSB THRILLER BRZ DIG

3139 123 6505

19130_029_110427.eps 110427

2011-Apr-29

Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 55

VGA

B06D

VGA

B06D

6E06

+5V_SW

IE00 3E26 10K 3E25 10K 7E01 BC847BW BAS316

EDID_WC

FE16

DC_5V

2E00 5E00 VGA_R FE01 60R

RP

3E00

VGA_Rp

10n

68R

5p6

75R

RES

2E07

3E16

6E00

2E03

SOG 5E01 VGA_G FE02 60R 5p6 75R

3E03

1n5

1R0

GP

2E02

3E02

VGA_Gp

10n

68R

RES

PESD5V0S1BA

1E00

2E08

3E15

6E01

1E05

0001

RES 3E27 68K

GN 1R0 DC_5V 5E02 VGA_B 60R 5p6 75R

VGA_Gn

10n

100R

PESD5V0S1BA

2E04 3E10

3E04

FE11
RES 3E24 6K2 1% 2E16 4E04 1E02 0001

DC_5V

BP

2E05

3E05

VGA_Bp

10n 3E14

68R

FE15

RES

2E09

6E02

100n 7E00 M24C02-WMN6 8 10K 10K 3E21 3E22 3E23 33R ) FE10 7

PESD5V0S1BA

1E01
5E03 6E05 3E13 150R 100n 1n0 2E10 2E11 FE03 BAS316 60R

WC FE13 4E02 4E03 1%

SCL_VGA SDA_VGA FE08 FE09 6 5

(256 8) EEPROM

DC_5V

SCL ADR SDA 1%

4 330p 2E14 2E15 330p

0 1 2

1 2 3

FE12
6K2 6K2

RES 3E19

HSYNC 30R 5p6 2K2 2E12 FE05 FE06

5E04 H_SYNC

RES

6E03

1E03

FE14
FE07

RES 3E17

VSYNC 30R 5p6 2K2 2E13

5E05 VSYNC

PESD5V0S1BA

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

1216-02D-15L-2EC

RES

6E04

RES 3E18

PESD5V0S1BA

1E04

RES 3E20

FE04

2 1

2011-01-31 2011-01-13

PCB SB SSB THRILLER BRZ DIG

3139 123 6505

19130_030_110427.eps 110427

2011-Apr-29

Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 56

10-7 B07 393912365052

Hospitality

B07

Hospitality

B07

DMMC1 DMMC3
RES
1F01

RES FF12
FF11

1F00

+3V3STBY
SDA-LCD SCL-LCD

PBS_HPL PBS_HPR

SDA_CLOCK SCL_CLOCK

FF00 FF01 FF02 33R 100R 100R 4 FF03 33R 1 2 3 5

RES 5F00 RES 3F00 RES 3F01 FF13 RES 5F01 +5V_SW
502382-0370 1n0

1 2 3 4 5 7

FF04

RES

2F00

502382-0570

RES

2F01

1n0

2 1

2011-01-31 2011-01-13

PCB SB SSB THRILLER BRZ DIG

3139 123 6505

19130_031_110427.eps 110427

2011-Apr-29

Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 57

10-8 313912365052 SSB Layout

Overview top side

4817 4820 4815

U4

1X05
U2

U5

1702
4818 4812 4819 4823

7801
4824 4813

4814 4822 4816 4821

1G51
2155 2161 2171 2153
2803 2805

7122

3760

3765 3780

3759

7124

2183 2152 2162 2100

3762

2140

5115 2188

2189

2172

2105

2163

2191
3615 2609

5117 2154

5120 2168

2138

3763

2802

4810 4811

7123

2104

1X04

5506

7600
3707 3706
37A9

2700 1D05 1D04 6C07

2C13 2C12 3C11 3C19 3C10 2C10

U23

1M99

2128 3127 3605 3614 3612 3613 2729 3600 3602

7125

2131 3128 3607

3B37

2132

2133

4700 3726

2514

2127 3126
37AA

2134

7120 2159
2109
2D14
1F01

2164

2126 2125 2701

5123

2608 2101

2135

5121

6122

2804 5104

2130
3609 3611 3608
37A8 3B18

1D01

4100 3606 3754 3753 2B24

3B17

2129
3610 3784 2720 3785 2719

5105 2176

2198

2175

2181

2146 2136 2B16 2B25 2B41

2B40

2106

2151

2169 2199
2B17

2551 2628

2137 3129
2B44

2180

5106

7601
2B43 2288

5228

5700

1M95

1700

3737 3757 3735 3731 3758 3788 3787

7216
7A00

2143

2149

2716

2141 2144

3712

3713 3709 3719 3718

2B02 2B03 2B05 2B06 2B07 2B08 2B11 2E05 2E02 2E04 2E00 2B00 2B01 2B09

7702

1402

2419

2402
3E05 3E02 3E04 3E00 3B07 3B08 3B00 3B01 3B02 3B03 3B05 3B06 3B11

1C06 6C06

2C09

2142

2403
7703
3715 3796

2C14

2145

3711 2702

2717

2147
2285

3617 3618

2286

3619

2287 5227

5229 5226

3C09 2C11

1C07

2148

2289 5230

2291

7700
2290

1403

2421 2420

2411

5401

2704 2703 3717 3716

3B09

1C03
2297
3C07 2C08 1C20 3A13 3A14 3A12 3A11 3C08 2C07

3B49 3B46 3B52 2B57

2B55
3B45

2B56

2412

2405 5402

7400

4306

5400 2400

7B01

2724 3793 2727

5311

2416 2415 2422

2A02

1M20 1735

5403

2294 5208

2B34

2B37

3B40

3B50

3B48

2B35

2B38

3B32 2B36

3B33 2B39 2A01 3A03

2B52

3749

2B20

3B16

2B19

2726 3795 3798 2728 5706 3748

3B15

2296

1B05 1706 1C08 1C09

6701

6700

6B00

6B01

6A00 1A02 1B03 1705 1B04

1A03

2B50

2258

3A04

2725 3794

2401
1C10

1X03

5207

3B31

3B34

6A01

1C05 6C05

2723 3792

2A09

2A06

3791 3790 2722

1A01 1B01 1201

5309
2295
2E09

1C14

2C21

3C12

3C13

2C19

1B02

1C15

1C01
3C21

1701
2B61

5C03

3C14

2C17

3C17

2C15

3C28

3C29

2C16

6C20

6C19

2C18

6C10

2C24
3C23

6C08

2C20

2C25 5C04

3C16

5C05

3C24

3C18

5E02

3E14

3E15 2E08

6916 6915

2C06

3C05

3C25

3C06

2C05

3B55

2C01

3C00

6C00

3C26

2C02

6C01

5C01

6C03

3E16

3F01

5F01

3F00

5F00

1202 1C19
3B56 2B62

6914 6913
2B60 2E11 3E13 2E10

6E00 6E05
3E18

5E00
2E13

2E07

5C02

6C04

1X02
3C20 3C02 2C04 3C04 3B54 3C22

6E02

5E01

2C00

2C22 5C00

6C09

1902
6E01
5E03
3E10

3C01

2C03

6C02

3C27

2C23

7B05
3B57

6917

3E17

1C16 1C18

1C17

6E04
2B63

1E04

1E03

1F00

1E02 1E05 1E00

6E03

5E05

5E04

2E12

1C02

1901

1X01 1E01

2011-01-31

SSB Layout Top

3139 123 6505

19130_040_110428.eps 110428

2011-Apr-29

Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 58

Overview bottom side

I107

2185 3135
I106 F750 F746 I136 I127 I137 I132 I141 F763 F801 F749 F747 F811 F805 F809 F807 F832 F815 F813 F748 I144

2157

I122

3101 2177 2160 3114

I135

2179 3100 2112 2190 2158 3113 2178 3102

I140

I120

F132 F831

3122 3125 3105 3115 2139

F812 F810 F808 F806 F834 F816 F814 F833

7119
2165
3118 3116 3112

3107 3146 3140

F135 F751 I117 I143 F829 I131 F133 I105

3136

2197

5125

2166

2122

I119 F131 I118 I134 I104

I801

5801 5802 5800

2192

F125 F818 F817 F824 F823

FD00

3153 3154 3155

2602 3616
F600 F102

2607 3779 3778 3775 3774 2712 3776 3777

F103

4803 4804 4805

3741 3782

F819 F822 F828 F820 F104 I112 F827 F826 F825 F821

2600

I800 F702

5500

FD05

FD04

3740 3700 3701

F701 U1

2567
2566
I732 I742 I731 I726

I743 I727

7800

2604 2603 2605 3103

I111 I109

3705
F800

5705

2706
F502

2601

4800 4806 5127 4801 4807 4802 4808

3809

3704
I711 I806 3B38 FB03 IB17 2B42 3B39

2606 3601
I142

2167
F105

3108 2187 3151 2195

F106

2150

2D12

FD03 I125

7D00
3808 3802 3739
I713

3604 3603

7803
3805
I807

3138 2170 3149

2186

2193

2123 3150
I123

5124

I138

2108

FD07

2107

FD02

6800
3803
F716 IB16 F503 F737 I809 I715 I758 I802 I808

2806

3721 3720

FD06

3145 3109 3148 3117 3106

F107

2807 3807 3810

3781

7802
I701

3732 5701 2730

F108

1D03

5D00

F109

3742

FD01 I126 I110 F742 I700 F101 I113

7705

2D11

6D00

2521

2505

2113

3111

3806 2581

2502 2501 2506

I108

2110

5128

F741 IB14

5503

3745 2522 2515 2503

I756 I757 F601 3B36 IB15 37A5

3736

I716

2504

7708
2623 2624 3621 2622
F501 F409

2124 3152

3743

2525 2516 2518 2526 2626 4401 2537 2533 2527 2538 2532 3624 2508 2545 2509 2713 2510 2531 2423 3417 2535 2534 2529
F414

2629 3620

I714

2599 2570 3622 2552 2553 2512 2621 2620 2625

2627

4311
IB18 IB20

4314 2536
F602

3783

2524 2565

I506 I760

2523 2564

2111
F136 3B35

I759

F113

2584 3623

F114

4309

FF11

4307

2513 2630

F117

2F00

I254

2569

2277
5502 2577 2597 2558 2562 2563
F500 I505 IB22

2517

6402
I429

F416

3416
I139

3131 3412

F116

FC01

2278
2560 2528
3B47

6401
I424

3130

2F01

FF13

FF12

F115

3415
F413

F236

7405

5222

2282 2559 2541 2561 3723 3722 2574

F704 CXXX I436 I747 I507 I255

2530

2519 2520 2582

2580

2500 2507
F759

6102
3414

2579
I735

2102
3432
I423 I442

F119

7402
F415 I422 I435

I425 F118

6400

2596

5505

2540 2542

IC20

4209 4210
2543 2544
U3 F745

2573 2549
3B58

7411

7412 7413

F408

3411 3413

IC07

5225

2284

2595

2575

2576

2550

I754 I753

7403
I437

3418

3761
I741

2430 3430

3435

I733

3789 2568 2705

F738 F706 F705 I708 F760 F761

3431 3433 3426

3409 3410 3408

F121

IC19

2280

2281

2283

2279

4313
37AB

3786 3714 3710

F740 F707 F708

7404
2431 3434 3419

IB63 I502 I504 3B14 2B14 2B15 IB61

2571 2588

I440

I433

F122

IC05

I430

F123

3A18

4A02

3272 4312
IB37 IB27 I744 I750 I739 F736 IB26 F721

3271

3A15

2A07

2A12

3A10

2A05

FA06

IA02

2593 5504 2592 3703 5501 F739

3405
I412 F404

FC00

FC02 IB41 37A7 I734 37A6 IB47 IB24 IB25 IB31 IB33

4707

2598 3500

IA09

IA10

4708

2A11

IB43 2E03 IB23

IB29

IB35

F417 3E03

2711 3738 3756 3734 3751 3729 3702

I745 F766 I761 I746

3744

IB39

IB45

2414
I405 IB21 I415

3452 3451

2413
I413

I417

2A10

4A03

6706
F411 I749

2408

2426

F410

3422

3A17

IA04

F405

IB53 I906 I406

C400 F400 I414 I434

F406

3A16

3724

FA07

2A04 A214

3768 3727 3728 3730 3769

I725 I755

6707
6902 3746 3747 3764 4904 3906

3A09

IA03

2A08

7710

IC04

IB52

I403

3400
I401

2427 3453 3454

2409

2378

2337

2333

2710

2B59

3B53

FB08

7701

A213

3262 2334 2338 3263

F725 I738 I737 I300 I308 F246 I307

5306 2318 2323 2335

7908
IB50

F402 F753 F401

2425 3421

2377

2336

3733 2709

FC03

3332 3331 5308 2341

2340 2339

5307 2320 2321 2322

1301
6708
7709
3771

IA00 A212

IA01

3B42

4308

2721

3770

2B53

7407
I411 3B43 I432 3B44

2406 2407

2424 3420

2404

2A13

7408

IA08 I302

3A19

5304 2262 2324 2263 2314 3261

FA04 F303

I304

3767
F724

6709
IB51 IB19 IB48

F754

IB02 I338 F209 I301 F302

IB03

3427

2B54

7406

2311 2303 2309

F306 I325

2306 3344 2301 3343

F412 I431

I416

2418
3428
3B41

F756

IB01 I306 F208 F213

3350

2B51

IB09

IB08

FB00

3B51

I317

FA09 F301 I318 F207

7302
3337 3335 3336 3349
F717 I303 I316 F718 I320 FB04

I445

7414

F300

2B58

6403

3406

FA08

IB00

5305

3339 2332

IB49

I441

2433 3439

2417

I418 F757

F758

F765

5303 3360 2313 3352 3351 2316 2312 2379 2380 2317

FA02

I305

F206

I220

3355

6301
F719

7217

F235 F242

3265

F204

7301

4310

3354 3357 3359 3358 2307 2302

F205

2226 2225 3230 3228

FA03

FB01

2304 2305 5301

3353 2308 3356 2310 5302

I221

3915

3916

7901
FE16 FE12 FE11 FE09 3E25 F904

6901

F911 F202

3270
F247

IB72

F907 I222

F203

3264 3269

F908

5310

FB07

I916

IC22 FB09

IC14

FC14

IC11

3438

3437

I443

2432

F755 FC12 FC11 IC10 FC13 IC13 IB10 FC15 IC09 FC10 FC06 IC18 FB02 IC17 IC01 FC08 IC15 IC03 IB13 IC02 IB12 IC16 FC05 FC04 FC07 FC09

3E21

3E19

2213 7218

3904 3905

7E01

I905 A225 3E22 3E20 2E15 FE08

F743

7903
F201 FE10 IE00 3E23

2293

2E14

F909

FB06

3E27

IC21

F905

3919

3923

F906

7907

3903

4903 3921

7E00
FE15 F903 2E16 3E24 F902

IB71

2901
FE04 3E26 4E04

7902

IB70

I915

FE05

FE01

FE03

4902 3920

IB66

FE07

IB67

FE02

7900

F912

F901

3901 3924 3902 2900 3900 3908 3907

FE06

4E03

3913

3914

6900

F914

3912 5900
F915

4900 6903 2902

4901

FE14

F744

7905

F913

I902

6E06

F900

FF00

FF01

FF02

FF03

IB74 FF04

FE13 4E02

F120

2011-01-31

SSB Layout Bottom

3139 123 6505

19130_041_110428.eps 110428

2011-Apr-29

Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 59

10-9 T01 393912365071

LVDS Display

T01A
LVDS#1 1N01
FI-RE51S-HF FN32 SDA-TCON SCL-TCON BYPASS_MODE
NC

LVDS Display

T01A

PX1APX1A+

PX1BPX1B+

FN05 FN06 FN07 FN08 FN09 FN10 FN11 FN12

PX1CPX1C+

PX1CLKPX1CLK+ FN13 FN14 FN15 FN16

RES 2N03 10n

PX1DPX1D+

PX1EPX1E+

PX2APX2A+

FN31 FN17 FN18 FN19 FN20 FN21 FN22 FN23 FN24 FN25 FN26 FN27 FN28

PX2BPX2B+

PX2CPX2C+

PX2CLKPX2CLK+

PX2DPX2D+

PX2EPX2E+

+VDISP-INT

FN29

2N01

100n

FN01 53 55 57 59 61 FN33

100u 16V 2N02

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 54 56 58 60

1X01 REF EMC HOLE

1X02 REF EMC HOLE

2010-06-29

PCB SB THRILLER BRZ TCON

3139 123 6507

19130_032_110427.eps 110427

2011-Apr-29

Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 60

TCON Control

T01B
VDD1V8 VDD3V3LVRS DDR2VDD VDD3V3IO VDD1V8PLL FH36 100n 100n 100n 100n 2H07 100n 2H08 100n 2H09 100n 2H10 100n 100n 2H27 2H28 100n 2H29 2H30 100n 2H31 100n 2H04 100n 2H05 100n 2H06 100n 2H35 100n 2H36 100n 2H38 100n 2H13 2H25 100n 2H26 100n 2H33 2H32 100n 2H34 100n 2H37 100n 2H39 100n FH37 FH38 FH39 FH40

TCON Control

T01B

2H01

100n 2H02

POWER

VDD18

VSS

100n 2H03

7H01-5 VPP1501BFG VDD1V8

VDD18 3H01
OSCOUT

VSS 27M 3H02 1M0 560R

1H00 DSX321G 2 NC 1 4 3 7H01-4 VPP1501BFG

DRAM

VDD18
GSP1

VSS 3H21 33R VCC_3V3 VCC_3V3

GSP2

OSCIN

2H40

10p

2H41 10p

RES 3H22 2K2 5 7H02-1 74LVC2G04 1 1 5 6 8 4

REV

VDD18 7H05 74LVC1G86GW 2 4H05 Q 3 Q

TCK TCK#

VSS

TA0 TA1 TA2 TA3 TA4 TA5 TA6 TA7 TA8 TA9 TA10 TA11 TA12

P4 R2 P3 T1 R4 T2 R3 U1 T4 U2 R1 T3 U3 0 1 2 3 4 5 6 A 7 8 9 10 11 12 0 1 2 3 4 5 6 DQ 7 8 9 10 11 12 13 14 15 N2 M3 N1 M2 CS RAS CAS WE L2 L1 M1 M4 P1 P2 3H00 1K0 E1 CK UDQS CKE ODT 0 BA 1 RESIMP LDQS

VGH_35V 5 3 1
TCS# TRAS# TCAS# TWE#

VDD18
RESET

VSS

7H03 74LVC1G74DC 7 S 1 C1 2 1D 6 R 4

H3 H2 K3 K2 K1 K4 H1 H4 D3 D2 F3 F2 F1 F4 D1 D4 G2 G1

TDQ0 TDQ1 TDQ2 TDQ3 TDQ4 TDQ5 TDQ6 TDQ7 TDQ8 TDQ9 TDQ10 TDQ11 TDQ12 TDQ13 TDQ14 TDQ15 TLDQS TLDQS#

3H03

150K

VCC_3V3
RESET

4H04 5
U_D

VDD18 1 4
TCKE TODT U_D_INV

VSS 2H54 1u0 2H42 100n 2

60R
GCK

3H23 Q Q 3 5 100R 4

5H00
TBA0 TBA1

2H43

10u

VDD18

VSS

3H04

16K

VCC1V8 7H04 74LVC1G74DC 7 S 1 C1 2 1D 6 R

7H02-2 74LVC2G04 3

C2 C1

TUDQS TUDQS#

2H44

5H01

10u

C5 C9 D15 E3 E6 E7 E10 E11 F5 F8 F9 F12 F13 G5 G8 G9 G12 G13 H6 H7 H10 H11 J3 J6 J7 J10 J11 K5 K8 K9 K12 K13 L3 L5 L8 L9 L12 L13 M6 M7 M10 M11 N3 N6 N7 N10 N11 P15 R5 R8 R11 VCC1V8 5H04 60R

VDD18

VSS

VDD1V8PLL

60R

VDD3V3LVRS 7H01-3 VPP1501BFG

60R

VSS

2H45

10u

VDD33LVML
ASIC_CS1 ASIC_CS3 ASIC_CS5 ASIC_CS7 ASIC_CS9 ASIC_CS11

LCD

C8 C11 C13 E15 J15 N15 R13

VCC1V8

DDR2VDD

100n RES 2H53

5H02

2H52

100n

VCC_3V3

C7 C10 C12 G3

VDD18PLL

VSS

VCC1V8 DDR2VDD 5H05 60R 10u 2H50 5H06 60R 2H51 A1 E1 J9 M9 R1 J1 7H00 H5PS5162FFR-S6C VDDL VDD VDDQ 10u

VDD3V3IO

10u

VSS

5H03

2H46

C6 R6 R9 R12

VDD33IO

60R

VSS 3H05 J17 RESPI F1 STH F2 B1 STH B2 POL TP CPV OE STVU STVD SLOPE GP01 GP02 L|R_ U|D_ SELLVOS RLV CKP CKN M14 M15 U15 U14 H15 H14 FH35 3H06 RES T13 U13 T11 U11 T12 U12 T16 1K0
LCK+ LCKLDIO1 LDIO2 RDIO1 RDIO2 REV LS GCK

C3 C4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E2 E4 E5 E8 E9 E12 E13 E14 F6 F7 F10 F11 G4 G6 G7 G10 G11 H5 H8 H9 H12 H13 J1 J2 J4 J5 J8 J9 J12 J13 J14 J16 K6 K7 K10 K11 L4 L6 L7 L10 L11 M5 M8 M9 M12 M13 N4 N5 N8 N9 N12 N13 N14 P5 P6 P8 P9 P10 P11 P12 P13 P14 U4 M16 M17 N16 N17 P16 P17 R14 R15 R16 R17 T14 T15 1 2 3 4 5 6 CS 7 8 9 10 11 12 2K4 0P 0N 1P 1N 2P 2N 3P 3N RLV 4P 4N 5P 5N 6P 6N 7P 7N F16 F17 G14 G15 G16 G17 H16 H17 K14 K15 K16 K17 L14 L15 L16 L17
LLV6+ LLV6LLV5+ LLV5LLV4+ LLV4LLV3+ LLV3LLV2+ LLV2LLV1+ LLV1LLV0+ LLV0LLV7+ LLV7-

FH00

SDRAM
NC

7H01-1 VPP1501BFG FH06

GOE GSP2 GSP1 GSLOP

TODT TCKE TWE# TCS# TRAS# TCAS#

K9 K2 K3 L8 K7 L7

ODT CKE WE CS RAS CAS

TBA0 TBA1

A9 C1 C3 C7 C9 E9 G1 G3 G7 G9

A2 E2 L1 R3 R7 R8 L2 L3 0 BA 1

MISC
T8 U8 FH05 RES 3H27 RES 3H28 1R0 1R0 R10
ROM_SCL ROM_SDA SCL-TCON SDA-TCON

OSCIN

A1

IN

OSCOUT

B1

OSC

EE

SCL SDA

OUT

RESET

FH01

T9

TESTAGN

RST

3H25 U16 U17

R_L U_D SELLVDS

FH02

SCL-TCON SDA-TCON

RES 1R0 RES 1R0

3H26

FH03

P7 R7

SCL DB SDA U7 T10 U10 T17

TESTMOD

FH04

T7

0 1 2 3

U5 T5 U6 T6

ATTN

0P 0N 1P 1N 2P 2N 3P 3N LLV 4P 4N 5P 5N 6P 6N 7P 7N LLV CKP CKN F14 F15

A14 A15 A16 A17 B14 B15 B16 B17 C14 C15 C16 C17 D16 D17 E16 E17

RLV6+ RLV6RLV5+ RLV5RLV4+ RLV4RLV3+ RLV3RLV2+ RLV2RLV1+ RLV1RLV0+ RLV0RLV7+ RLV7RCK+ RCK-

DQ

50Hz_60Hz

U9

TESTSE

RTC50_60

TA0 TA1 TA2 TA3 TA4 TA5 TA6 TA7 TA8 TA9 TA10 TA11 TA12 TCK TCK#

M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 J8 K8
TLDQS TLDQS# TUDQS TUDQS#

0 1 2 3 4 5 6 A 7 8 9 10 11 12 CK F7 E8 B7 A8

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 UDM LDM LDQS VREF UDQS VSS

G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 B3 F3 J2 100n 2H48 FH34 100n 3H19

TDQ0 TDQ1 TDQ2 TDQ3 TDQ4 TDQ5 TDQ6 TDQ7 TDQ8 TDQ9 TDQ10 TDQ11 TDQ12 TDQ13 TDQ14 TDQ15

DDR2VDD 3H20 100R VSSDL 100R 100R

100R

100R

100R

100R

100R

100R

100R

100R

100R

100R

100R

A3 E3 J3 N1 P9

J7

7H01-2 VPP1501BFG

3H07

3H12

3H13

3H14

3H15

3H08

3H09

3H10

3H11

3H16

PX2A+ PX2APX2B+ PX2BPX2C+ PX2CPX2D+ PX2DPX2E+ PX2E-

B7 A7 B6 A6 B5 A5 B3 A3 B2 A2 0P 0N 1P 1N 2P RXE 2N 3P 3N 4P 4N CLKP RXE CLKN RXO CLKP CLKN B10 A10 0P 0N 1P 1N 2P RXO 2N 3P 3N 4P 4N B13 A13 B12 A12 B11 A11 B9 A9 B8 A8 B4 A4

LVDS

3H17

3H18

PX1A+ PX1APX1B+ PX1BPX1C+ PX1CPX1D+ PX1DPX1E+ PX1EPX1CLK+ PX1CLK1 2010-06-29

PX2CLK+ PX2CLK-

A7 B2 B8 D2 D8 E7 F2 F8 H2 H8

RES 2H47 VSSQ

PCB SB THRILLER BRZ TCON

3139 123 6507

19130_033_110427.eps 110427

2011-Apr-29

Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 61

TCON DC/DC

T01C
RES RES RES RES VLS_15V6_B 1 2 3 4 4J01-1 4J01-2 4J01-3 4J01-4 8 7 6 5 +VDISP 5J06 FJ00 VLS_15V6 RES 2J08 47u 25V 2J07 10u 2J09 2u2 FJ01 6u8 2u2 10u 39K 10n 10u 2J05 2J03 2J04 RES 3J02 RES 2J06 10u RES 2J10 SS34 6J06 1 2 3 4 4J00-1 4J00-2 4J00-3 4J00-4 8 7 6 5 7J01 FDS9435A 8 7 3 6 2 5 1 2J00 2u2 2J01 10u 2J02 100n 3J00 2K2 RES 7J02 FDS9435A 8 3 7 2 6 5 1

TCON DC/DC

T01C

+VDISP

2J44

2u2

10u

2J49

RES 2J47

47u 25V

RES

FJ59 3J01 RES 3J05 RES 3J09 VLS_15V6 2K2 RES 2J16 100n SGND1 2J32 SGND1 2J40 3J26 1u0 240K 3J10 RES 2J33 820p 220n 2J35 3J11 3J12 VCC_3V3 1u0 FJ11 20K 2u2 1n0 2J38 22u RES 2J39 6J05 3J24 RES 2J36 2J41 3J27 SS24 100n 4u5 0.5% 16V 22u 10K 13K 5J00 FJ13 VCC_3V3 FJ14 VGL_-6V 2J34 39K 220n VGL_-6V 100K 10K FJ58 39K 3J03 RES 2J11 RES 2J12 SGND1 FJ03 1n0 1n0

FJ57

VCC_3V3 FJ02

VLS_15V6

2u2

4u7

2J14

2J13

SGND1 38 1

7J00-1 ISL97653AIRZ PVIN LX RES 3J06 SGND1 2K2 34 35 29 28 21 20 23 22 10 11 13

SUPP

)
1 2 FBB

2J15

3J07

30 RSET POUT FBP DRN COM

COMP

FJ56

4n7

10K 1%

27

HVS

SGND1

26 36

EN PROT

FJ60

2J17

100n

15 16

P C1 N

2J18 VREF FBN NOUT

100n

17 18

P C2 N

GSLOP

FJ04

3J08 2K2 RES

2J19 CB 1 LXL 2 FBL 40 39 31 7J03 KTB1124-C 3 1 24K 0.5% SGND1 VCC1V8 3J25 12K 2u2 RES 2J24 2J25 RES 2J37 1n0 2 FJ05 FJ10

220n

24 25 2 3 4 8

3J04 3K3

CTL CDEL

5 4

2J20

4u7

VL

6J01 RB550EA 1 2 3

2J21 LDO-CTL LDO-FB TEMP 10n

4n7

CM2

SGND1

SUPN

AGND

RES 2J51

47u RES 2J52

47u

12

37

2J23

2K2 RES 3J29

4J03

2K2 2J22

2u2

RES 3J13

cK00

+VDISP

3J14

22u 16V

SGND1

VLS_15V6_B

SGND1 SGND1

SGND1

DISPLAY INTERFACING - VDISP

RES 1J00 T 3.0A 32V

7J00-2 ISL97653AIRZ 2K2 3J15 2J26 120p RES RES

42 43 44 45 VIA

VIA

57 56 55 54

VIA 53 52 51 50

VIA

RES 5J07 +VDISP-INT 2K2 3J16 2J27 120p RES RES 30R RES 5J08 22u 30R

2K2 RES 2J50

SGND1

SGND1

32 33 5 6 14 41

GND_HS

PGND

RES 1J01 T 3.0A 32V 2J43 10u

FJ55 +VDISP FOR DEBUG ONLY 3J28 2K2 6J07 LTST-C190KGKT RES 2J42

VIA

46 47 48 49

SGND1

1 2 3 4

4J04-1 4J04-2 4J04-3 4J04-4

8 7 6 5

27K

2K2

RES 3J19

3J17

RES 2J28

FJ06

3J18

2J29

750K

100p

100n SGND1

RES 3J20

2K2

1 2 3 4 FJ07 2J30 4u7 RES 2J31 100n RES 3J21

4J02-1 4J02-2 4J02-3 4J02-4

8 7 6 5

6J02 RB550EA 1 2 3

RES 7J04 2SB1767 2 3 2K2 RES 6J00 3J22 10K

VGH_35V

RES 4J05

FJ09 RES 3J23

SGND1

RES 7J05 2N7002 2 3

1
1 2010-06-29

GSLOP

3K6

PMEG1030EJ 1

PCB SB THRILLER BRZ TCON

3139 123 6507

19130_034_110427.eps 110427

2011-Apr-29

Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 62

P Gamma & Vcom & NVM

T01D
VCC_3V3

P Gamma & Vcom & NVM

T01D
ASIC OPTIONS
10u

VREF_15V2

VLS_15V6

VCC_3V3

VLS_15V6

VLS_15V6

VLS_15V6

FK00

1u0

1u0

22K 5%

100n

2K00

2K01

3K00

100K 0.5%

3K03

100n

100n

3K05

2K03

2K02

2K04

6K2 0.5%

FK02

FK03 6K8 10K 10K 3K40 6K8 3K41 RES 3K44 RES 3K60 RES 3K45 RES 3K46 10K

3K01

3K04

18K 5%

FK01 FK10
VH255 VH191

29 FK40 4K00 RES 4K22 RES 4K07 FK11 FK42

VH127 VH31 VH159

AVDD

VSD

OUT1

5K1 0.5%

7K00 ISL24837IRZ-T13

21

2K2 5%

2K05

3K02

10K 0.5%

27

OUT2

SDA-TCON SCL-TCON

INPCOM|DVR_OUT

OUT3

50Hz_60Hz

REFIN_INN 5 6 7 8

OUT4

32 1n0 3K61 3K49 1n0 3K51 10R 3K11-4 10R 3K11-3 10R 3K11-2 10R 3K11-1 1n0 3K50 FK44

OUT5

8
VH127 VH63 VH247 VH95

FK38 FK27 FK28 FK29 1n0

SELLVDS R_L U_D

REFIN

INN5 4 3 2 1

3K06

RES 4K08 RES 4K09 4K01 RES 4K10 10K RES 2K30 1 0K RES 2K24 10K RES 2K25

3K3 5% 2K2 2K06 100n 2K07 100n 2K08 100n 2K09 100n

SCL-TCON SDA-TCON

FK04 FK05

13 12

SCL SDA

OUT7

16

VCC_3V3

NC

30

INN7

15

SET_COMP

OUT8

18

10K

RES 3K08

NC

31

V_THERM

INN8

17

RES 3K07

INN6

11

RES 4K11 RES 4K12 RES 4K13 4K02 FK14 FK15 FK16 FK46 VCC_3V3 FK47
VL0 VH127 VH95 VH31 VH63 VH0

SSB-TCON EEPROM
VCC

FK06

14

OUT9

19

BANKSEL

OUT10

22

3K10

10K

OUT11 FK18 2K28 100n

23 6K00 MSS1P4

OUT12 5 6 7 8 OUTCOM 3K12-4 10R 3K12-3 10R 3K12-2 10R 3K12-1 INNCOM 4 3 2 1 10R

24

VIA

OUTCOM

25

FK56

RES 4K14 RES 4K15 RES 4K16 4K03

VL127 VL95 VL31 VL63

FK35

34 35 36 37 38 39 40 41 7K04 M24C64-WDW6

INNCOM

26

FK57

2K2

6 20

33

3K52

2K10

100n 2K11

100n 2K12

100n 2K13

100n

FK07

FK36

) (8K 8) EEPROM
1 2 3 0 1 2 ADR

WC SCL SDA 4

7 6 5

FK37 FK54 FK55 3K55 3K56 2K0 2K0

3K53

6K8 3K54 8

6K8

GND

GND_HS

10K RES 2K26

28

SET

OUT6

10

WP_TCON
ROM_SCL ROM_SDA

RES 4K17 RES 4K18 4K04 RES 4K19 FK19 FK20

VL127 VL63 VL247 VL95

VCOM BUFFER
RES 4K20 RES 4K21 4K05 FK22 FK23 FK24
VL31 VL159 VL127 VL191 CS_L

+VDISP

8 7 6 5

3K62

1 2 3 4

4K06-1 4K06-2 4K06-3 4K06-4

cK01

FK51 INNCOM 5 6 7 8 FK52

2K18

68p

3K13-4

10R 3K13-3

10R 3K13-2

OUTCOM 3 2 1

2K19

10u

5R6 0.5%

5K1 0.5%

10R 3K13-1

100n 2K15

3K14

3K17

2K14

100n 2K16

100n 2K17

100n

3K34

7K01 PBSS4540X

10R

2K2

DEBUG ONLY
RES 1KQA WP_TCON RESET VCC NC NC NC 10 11 502382-0970 RES 1KQB SDA-TCON SCL-TCON 1 2 3 4 FK33 5 6 502382-0470 RES 3K36 10K BYPASS_MODE VCC_3V3

VCOM

FK08

3K16

2K21

100n

2K20

22u 16V

7K02 PBSS5330X

3K15

5R6 0.5%

560R 5%

1 2 3 4 5 6 7 8 9

100R

FK53

ITEM NO. 3K45 3K51 4K01 4K02 4K03 4K04 4K09 4K13 4K16 4K18

32" 5K1 JUMPER JUMPER JUMPER JUMPER

40" 10K JUMPER JUMPER JUMPER JUMPER -

RES 3K35

10K

2010-06-29

PCB SB THRILLER BRZ TCON

3139 123 6507

19130_035_110427.eps 110427

2011-Apr-29

Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 63

MPD

T01E
+VDISP FL14 2 7L02 2SC5886A 3 1 FL16 VREF_15V2

MPD

T01E

3L17

1R0

FL15 33R 0.5% 2L14 100n 2L15 22u 16V 33R 0.5%

3L16

3L15

7L01 NJM2125F 4 2

1 3

FL13

3L13

4 FL00
CS1

5 28 7L00 ISL24016IRTZ

4L00-4 RES AVDD

FL12

62K

2L13
ASIC_CS1 ASIC_CS3 ASIC_CS5 ASIC_CS7 ASIC_CS9 ASIC_CS11 CS_L

4L00-3 RES FL01

CS2

OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 INA OUT7 OUTA OUTB NC VIA REFH REFL 10 11

2 FL02
CS3

4L00-2 RES

1 2 3 IN 4 5 6 7

32 31 30 29 27 26 25

1 FL03
CS4

4L00-1

RES FL04
CS5 NC NC

1 2 3 4 5 6 7 8 19 20 21 22 23 24 18 + + INB 13 14 15 16 2L12 1n0

4L01-4

CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10 CS11 CS12

RES FL05
CS6

VCOM

3 17
NC

4L01-3

RES 9 FL06
CS7

4L01-2

RES FL07
CS8

4L01-1

34 35 36 37 38 39 40 41 42 GND_HS 33 GND 12

RES FL08
CS9

4L02-4

RES FL09
CS10

4L02-3

RES FL10
CS11

4L02-2

FOR 32" / 40"

RES FL11
CS12

4L02-1

RES 8 6 5 10R 6 10R 10R 10R 3L01-3 10R 3L01-4 3L02-1 2 3L02-2 7 10R 3L02-3 10R

3L00-1

10R 3L00-2

10R

10R

3L01-1

10R 3L00-4

10R 3L01-2

3 3L00-3 6

100n 2L02

2L08

100n 2L09

100n 2L10

100n 2L11

4 3L02-4 5

2L00

100n 2L01

100n 2L03

100n

2L04

100n 2L05

100n 2L06

100n 2L07

100n

100n

ITEM NO. 3L12 3L13 3L14

32" 47K 2K2 56K

40" 68K 2K 82K

3L12

100n

10K 0.5%

82K 0.5% 2L16 3L14

+VDISP

100n

2010-06-29

PCB SB THRILLER BRZ TCON

3139 123 6507

19130_036_110427.eps 110427

2011-Apr-29

Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 64

Mini LVDS

T01F
FM98 81 82 1KA2 FM00 VGL_-6V VGH_35V 3M00 3M01 3M03 3M08 FM69 FM70 FM71 FM72 68R 68R 68R 68R VGL_-6V VGH_35V 1KA1

Mini LVDS

T01F

GSP2 GSP1 GCK GOE U_D_INV CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10 CS11 CS12 VCOM VH255 VH247 VH191 VH159 VH127 VH95 VH63 VH31 VH0

3M02 3M07 3M09 3M10

68R 68R 68R 68R

FM01 FM02 FM03 FM04 FM05 FM06 FM97

GSP2 GSP1 GCK GOE U_D CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10 CS11 CS12 VCOM VH255 VH247 VH191 VH159 VH127 VH95 VH63 VH31 VH0 LLV5+ LLV5LLV4+ LLV4LLV3+ LLV3-

FM73 FM74 FM75 FM76 FM77 FM78 FM79 FM80 FM81 FM82 FM83 FM84 FM85 FM86 RES 3M13 3M14 68R 1 4M08-1 2 4M08-2 3 4M08-3 4 4M08-4 RES 1 4M13-1 RES 2 4M13-2 RES 3 4M13-3 RES 4 4M13-4 8 7 6 5 8 7 6 5 68R VCC_3V3 FM87 FM89 FM90 FM91 FM92 FM93 FM94 FM95 FM96

LCK+ LCKLLV2+ LLV2LLV1+ LLV1LLV0+ LLV0-

RLV7+ RLV7RLV6+ RLV6-

RES RES RES RES FM30 FM31 FM32 FM33 FM34 FM35 FM36

RDIO2 R_L RDIO1

1 2 3 4 4 1 2 3 VCC_3V3 FM38

4M00-1 4M00-2 4M00-3 4M00-4 4M04-4 4M04-1 4M04-2 4M04-3

8 7 6 5 5 8 7 6

RES 2M01 100n

RES 3M15

68R

3M16 4M11 FM40

LDIO2 R_L LDIO1 LLV6+ LLV6LLV7+ LLV7-

GSP2 GSP1 REV LS

68R

GSP2 GSP1 REV LS

RLV5+ RLV5RLV4+ RLV4RLV3+ RLV3-

FM41 FM42 FM43 FM44 FM45 FM46 FM47 FM48

RCK+ RCK-

RLV2+ RLV2RLV1+ RLV1RLV0+ RLV0-

FM49 FM50 FM51 FM52 FM53 FM54 VLS_15V6

VL0 VL31 VL63 VL95 VL127 VL159 VL191 VL247

VLS_15V6

VL0 VL31 VL63 VL95 VL127 VL159 VL191 VL247

FM65

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 3M17 20R 501559-8093 10u

3M18

20R

81 82 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 RES 36 2M02 35 34 100n 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 501559-8093 FM67

10u

RES 2M04

FM68

RES 2M03

2010-06-29

PCB SB THRILLER BRZ TCON

3139 123 6507

19130_037_110427.eps 110427

2011-Apr-29

Circuit Diagrams and PWB Layouts L11M1.1L LA 10. EN 65

10-10 313912365071 TCON Layout

Overview top/bottom side

FM83 FM95 FM73 FM93 FM85

FM81

FM79

FM77

FM75 FM53

FM51

FM49

FM47

FM45

FM43 FM41 FM32 FM30 FM34 FM35

FM36

FM68

FM05 FM04
3M18

FM96 FM74 FM76 FM84

FK16

FM94 FM82 FK15

FK14 FK11

FM86 FM80 FM78

FM54 FM00 FM65 FM52 FM50 FM48 FM46 FM44

FM42

FM33

FM31
3M02 3M07

FK44 FK40 FK42

1KA2
3M17

1KA1
FM98 FM67 FM92 FM90 FK46 FM91 FM89
3M14 3M13

FM06

4M00 4M04 4M08 4M13

2M03
FK10 FM87 FL09 FL10

FL06 FL02 FL00 FL01 FL03

FL07

2M01

2M04
FL05 FL04 FL08

2M02

2K26

3K50

3K46

FM97

FL11
FH05 3H26 3H28 3H25 3H27 FJ14

3K61

2K30

3K60

FK38 FH35 FH03 FH02 FH06

3M16 3M15

3K15 3K14
4H05

2K15

FM38 FM01

FM02

7H02

7K02
7H04
FK29
3H23 3H22 3H21

2K16

2K14

2K17

7H05

FM69

3M00 FM70 3M01 FK52

3M08

4M11 FM40 FK28

3K51 2K25

FK07 FK08 FM71 3M03 FM72

3K45

2K19

2K21

3K16

7K01

3K13
FH04

2K04

4K18

4K06
3K55 FK37 FK54
3K52

1KQA

2K20
FH00
3K53

FK24

3K34

4K15 FH01 3H06 4H04 3H04 FK47 FK23 FK27 2K24 3K44 3K49 FL12 FK20 FK18 FK57

2K18

cK01 2H34 FH40

2H29 2H28

4K17

3K03

4K05 FK55

4K04

2L12

2L13 3L12

3K17
3K54 3K56

4K19

4K16

2H42

3H03

4K03

4K14

4K20

7H03

2H54

FK51

FK19

FK56 FJ13 FK22

FK02

3K04

3K08

4K21

2H52

2H53

2H04

3K06

3K10

2H27

2H05

2H06

3K07

2K00 2K28
FK53
3H19 3H20 2H36

3K12

2H02

4L02

2K12
FK36
2H37

2K11
FH34

4L01

2H48

3K01

3K02

2H10

7K04

3K62

2H08

2K13
2H32

4L00

2H13 2H39

2H01

3L02

3L00

2H07

2H25

2L09

2K10
2H09

3L01

7K00
2H47
FK35

2H50

6K00

2K02

2L08

FK01

2H03

7L00
2L10 2L11
2H30
2H31

2L07 2L06 2L05 2L04 2L03 2L02 2L01 2L00

FL16 FL15

FK06

3K00

2K01

4K10

4K09

4K01

4K08

4K02

4K11

4K13

3K05

1X01
FK04 3K40 3H00 FK05 2H33 2H35 3K35
2H38

4K12

3K11

2K03

3H05

7H01
6J07
3K41 FH38

1X02
5H03
3K36

FL14

4K00

4K22

7L01
FH36
2H26

3L15 3L13
5H01 2H44 2H45
FK00 FH37 FL13

FK03

4K07

7H00

2K05
3J28
FK33

2K07

2K09

2K08

2K06

6J05
2H51 5H05 5H04 5H06 4J04
FJ05 3H14 3H18 3H17 3H11 3H07 3H08

3L16
2H43 2H46 5H00

3L17

5H02

2J39

2L16 3L14

3J22
5J08
FN29
3H01 2H41

2J38

2L14

FH39

2L15

7L02
FJ55 FJ01

FJ56

3J25 2J36

4J02

3J27
3H13 3H15 3H16 3H12 3H10 3H09

5J00
3H02

2J25

2J24

2J50

FJ10

2J52

2J41

2J20 2J37 3J24

2J21

2J44

2J01

7J04
2H40

3J26 3J10

2J33

2J32

2J35 2J00

7J03
2J07 2J09
2N03 2N02

2J08
2J10

1J01 1J00 2J43

6J01

3J11

3J12

2J22

3J23 6J00

3J13 4J03

2J42

5J06
2N01 2J49
2J47

6J06

7J05

3J14

1KQB

2J40

2J51

3J29

1H00

5J07

FJ11

CK00

2J13

FN31 FJ59 FJ58 FN24 FN33 FN25 FN27 FN23 FN19 FN13 FN09 FJ06 FJ00 FN21 FN17 FN15 FN11 FN07 FN05 FJ03 FN01 FN28 FN26 FN22 FN20 FN18 FN16 FN14 FN12 FN10 FN08 FN06 FN32 FJ04 FJ07 FJ02 FJ57 FJ09

4J00

2J31 2J14

3J05 3J02

3J08

2J19

3J19 3J09

3J06

3J18

2J12 2J11 3J07

3J20

3J16 3J15

2J27 2J26

3J17 2J29

2J16

2J28

2J23

3J04 3J03 2J15

4J01

2J30

2J34 2J17 2J18

4J05 2J02 3J01 3J00

2J03

2J05 2J04

3J21

6J02

7J01

7J00

7J02

FJ60

2J06

1N01

3M10

3M09

FM03

2011-04-28

TCON THRILLER

3139 123 6506

19130_042_110428.eps 110428

2011-Apr-29

Styling Sheets L11M1.1L LA 11. EN 66

11. Styling Sheets

Styling Sheet Thriller 32"

THRILLER 32"

1150 0021 5213

0024

0154 0012

1005

0260

Pos No.

Description

Remarks

1114

1112 1004 0004

0004 0012 0021 0024 0154 0260 1004 1005 1112 1114 1150 5213 8191 8G51 1085

Front Cabinet Back Cover Side IO Bracket Bottom IO Bracket Speaker Bracket Stand Display panel Power Supply Unit IR/LED Keyboard + Board SSB Loudspeaker box Mainscord 1.8m Cable LVDS FFC Remote Control

Not Displayed Not Displayed Not Displayed

19130_039_110428.eps 110428

2011-Apr-29

Styling Sheets L11M1.1L LA 11. EN 67

Styling Sheet Thriller 40"

THRILLER 40"

1157

5213

1150 0021

0024 0012 0154

1005 0260

Pos No.

Description

Remarks

1114

1112 1004

0004

0004 0012 0021 0024 0154 0260 1004 1005 1112 1114 1150 1157 5213 8191 8G50 8KA1 8KA2 1085

Front Cabinet Back Cover Side IO Bracket Bottom IO Bracket Speaker Bracket Stand Display panel Power Supply Unit IR/LED Keyboard + Board SSB TCON module Loudspeaker box Mainscord 1.8m Cable LVDS FFC Cable LVDS FFC Cable LVDS FFC Remote Control

Not Displayed Not Displayed Not Displayed Not Displayed Not Displayed
19130_046_110429.eps 110429

2011-Apr-29