12.

Multiply-Accumulate Circuits

Multiplication followed by accumulation is a common operation in many digital systems, particularly those highly interconnected, like digital lters, neural networks, data quantizers, etc.

Figure 12.6 MAC circuit.

One typical MAC (multiply-accumulate) architecture is illustrated in gure 12.6. It consists of multiplying two values, then adding the result to the previously accumulated value, which must then be re-stored in the registers for future accumulations. Another feature of a MAC circuit is that it must check for overow, which might happen when the number of MAC operations is large. This design can be done using COMPONENTS, because we have already designed each of the units shown in gure 12.6. However, since it is a relatively simple circuit, it can also be designed directly. The latter approach is illustrated below, while the former is treated in problem 12.2. In any case, the MAC circuit, as a whole, can be used as a COMPONENT in applications like digital lters and neural networks (next sections). Overow: In the implementation (code) shown below, a FUNCTION was written to detect overow and truncate the result in case overow happens. Overow in a signed adder occurs when two operands with the same signal (leftmost bit) produce a result with a dierent signal from them. If it occurs, the largest value (positive or negative) should be assigned to the result. For example, if eight bits are used to encode the values, the addition of two positive numbers must fall in the interval from 0 to 127, while the addition of two negative numbers must fall between 128 (that is, 128 in unsigned representation) and 1 (255 in unsigned representation). For example, 65 65 130, which is indeed 126 (overow), so the result should be truncated to the largest positive value (127). Likewise, (70) (70) 140, which is, indeed, 116 (overow), so the result should be truncated to the most negative value (128). On the other hand, when the operands have dierent signals, overow cannot happen. The add_truncate( ) function was placed in a PACKAGE (chapter 10) called my_functions. The function receives two signals, adds them, then checks for overow

and truncates the result if necessary, returning the processed result to the main code. Notice that the function is generic, for the number of bits of the operands is passed to it by means of a parameter called size. Notice also in the main code that the parameters passed to the function were declared as signals (line 14), because variables are not allowed (chapter 11).
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 ------- PACKAGE my_functions: ----------------------------LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ---------------------------------------------------------PACKAGE my_functions IS FUNCTION add_truncate (SIGNAL a, b: SIGNED; size: INTEGER) RETURN SIGNED; END my_functions; ---------------------------------------------------------PACKAGE BODY my_functions IS FUNCTION add_truncate (SIGNAL a, b: SIGNED; size: INTEGER) RETURN SIGNED IS VARIABLE result: SIGNED (7 DOWNTO 0); BEGIN result := a + b; IF (a(a'left)=b(b'left)) AND (result(result'LEFT)/=a(a'left)) THEN result := (result'LEFT => a(a'LEFT), OTHERS => NOT a(a'left)); END IF; RETURN result; END add_truncate; END my_functions; ---------------------------------------------------------------- Main code: ----------------------LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE work.my_functions.all; ------------------------------------------

7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

ENTITY mac IS PORT ( a, b: IN SIGNED(3 DOWNTO 0); clk, rst: IN STD_LOGIC; acc: OUT SIGNED(7 DOWNTO 0)); END mac; -----------------------------------------ARCHITECTURE rtl OF mac IS SIGNAL prod, reg: SIGNED(7 DOWNTO 0); BEGIN PROCESS (rst, clk) VARIABLE sum: SIGNED(7 DOWNTO 0); BEGIN prod <= a * b; IF (rst='1') THEN reg <= (OTHERS=>'0'); ELSIF (clk'EVENT AND clk='1') THEN sum := add_truncate (prod, reg, 8); reg <= sum; END IF; acc <= reg; END PROCESS; END rtl; ------------------------------------------

Simulation results are presented in gure 12.7. Notice that the following sequence of signals was presented to the MAC circuit: a (0, 2, 4, 6, 8, 6, 4, 2), b (0, 3, 6, 7, 8, 8, 8). Therefore, the expected output sequence is acc (0, 6, 30, 12, 52, 100, 148) (recall that 12 is represented in the graph as 256 12 244).

Figure 12.7 Simulation results of MAC circuit.

All the values are OK, except the last one, for it is above the maximum positive value allowed for 8-bit signed numbers (127). Therefore, this result was kept at 127.