TL7702B, TL7705B, TL7733B SUPPLY-VOLTAGE SUPERVISORS

SLVS037K SEPTEMBER 1989 REVISED APRIL 2002

D D D D D D D

Power-On Reset Generator Automatic Reset Generation After Voltage Drop RESET Output Defined From VCC 1 V Precision Voltage Sensor Temperature-Compensated Voltage Reference True and Complement Reset Outputs Externally Adjustable Pulse Duration

TL77xxBC . . . D OR P PACKAGE TL7705BM . . . JG PACKAGE TL7705BQ . . . D PACKAGE (TOP VIEW)

REF RESIN CT GND

1 2 3 4

8 7 6 5

VCC SENSE RESET RESET

TL7705BM . . . U PACKAGE (TOP VIEW)

description
The TL7702B, TL7733B, and TL7705B are integrated-circuit supply-voltage supervisors designed for use as reset controllers in microcomputer and microprocessor systems. The supply-voltage supervisor monitors the supply for undervoltage conditions at the SENSE input. During power up, the RESET output becomes active (low) when VCC attains a value approaching 1 V. As VCC approaches 3 V (assuming that SENSE is above VT+), the delay timer function activates a time delay, after which outputs RESET and RESET go inactive (high and low, respectively). When an undervoltage condition occurs during normal operation, outputs RESET and RESET go active. To ensure that a complete reset occurs, the reset outputs remain active for a time delay after the voltage at the SENSE input exceeds the positive-going threshold value. The time delay is determined by the value of the external capacitor CT: td 2.6 104 CT, where CT is in farads (F) and td is in seconds (s). An external capacitor (typically 0.1 F) must be connected to REF to reduce the influence of fast transients in the supply voltage.
NC REF RESIN CT GND

1
2 3 4 5

10 9 8 7 6

NC VCC SENSE RESET RESET

NC No internal connection TL7705BM . . . FK PACKAGE (TOP VIEW)

NC REF NC VCC NC NC RESIN NC CT NC

3 4 5 6 7 8 2 1 20 19 18 17 16 15 14 9 10 11 12 13

NC SENSE NC RESET NC

NC No internal connection

The TL7702BC, TL7733BC, and TL7705BC are characterized for operation from 0C to 70C. The TL7702BI, TL7733BI, and TL7705BI are characterized for operation from 40C to 85C. The TL7705BQ is characterized for operation from 40C to 125C. The TL7705BM is characterized for operation from 55C to 125C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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NC GND NC RESET NC

TL7702B, TL7705B, TL7733B SUPPLY-VOLTAGE SUPERVISORS

SLVS037K SEPTEMBER 1989 REVISED APRIL 2002

AVAILABLE OPTIONS PACKAGED DEVICES TA SMALL OUTLINE (D) TL7702BCD 0C to 70C TL7733BCD TL7705BCD TL7702BID 40C to 85C 40C to 125C 55C to 125C TL7733BID TL7705BID TL7705BQD CHIP CARRIER (FK) TL7705BMFK CERAMIC DIP (JG) TL7705BMJG PLASTIC DIP (P) TL7702BCP TL7733BCP TL7705BCP TL7702BIP TL7733BIP TL7705BIP CERAMIC FLATPACK (U) TL7705BMU

The D package is available taped and reeled. Add the suffix R to device type (e.g., TL7702BCDR).

functional block diagram

The functional block diagram is shown for illustrative purposes only; the actual circuit includes a trimming network to adjust the reference voltage and sense-comparator trip point.
VCC 8

Reference Voltage 1 CT SENSE R1 (see Note A) 3 7 Reference Voltage 2

70 A 6 RESET

RESET

R2 (see Note A) 2 RESIN 1 4 GND Pin numbers shown are for the D, JG, and P packages. NOTE A: TL7702B: R1 = 0 , R2 = open TL7705B: R1 = 23 k, R2 = 10 k, nominal TL7733B: R1 = 11.3 k, R2 = 10 k, nominal REF

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TL7702B, TL7705B, TL7733B SUPPLY-VOLTAGE SUPERVISORS

SLVS037K SEPTEMBER 1989 REVISED APRIL 2002

typical timing diagram

VCC and SENSE VIT+ Vres 0 RESET td td VIT Vres

VIT

VIT+

Output Undefined

Output Undefined

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V Input voltage range, VI: RESIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 20 V SENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 20 V High-level output current, IOH (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Low-level output current, IOL (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Package thermal impedance, JA (see Notes 2 and 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97C/W P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85C/W Case temperature for 60 seconds, TC: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG or U packages . . . . . . . . . . . . . . 300C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P packages . . . . . . . . . . . . . . . . 260C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to the network ground terminal. 2. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) TA)/JA. Operating at the absolute maximum TJ of 150C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions

MIN VCC VIH VIL VI IOH IOL Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current RESIN RESIN SENSE RESET RESET TL770xBC TA Operating O erating free-air tem temperature erature range TL770xBI TL7705BQ TL7705BM 0 40 40 55 3.6 2 0 0 MAX 18 18 0.8 18 20 20 70 85 125 125 C UNIT V V V V mA mA

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TL7702B, TL7705B, TL7733B SUPPLY-VOLTAGE SUPERVISORS

SLVS037K SEPTEMBER 1989 REVISED APRIL 2002

electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS TL77xxBC TL77xxBI TL7705BQ MIN VOH VOL Vref High-level output voltage, RESET Low-level output voltage, RESET Reference voltage TL7702B TL7733B VIT Negative-going input threshold voltage input at SENSE in ut TL7705B TL7702B TL7733B TL7705B TL7702B Vhys y Vres II IOH IOL ICC Hysteresis, H t i SENSE (VIT+ VIT) Power-up reset voltage Input current RESIN SENSE TL7702B TL7733B TL7705B IOL at RESET = 2 mA, VI = 0.4 V to VCC VI = Vref to 18 V VO = 18 V, VO = 0 V, VSENSE = 15 V, See Figure 1 See Figure 1 RESIN 2 V 1.8 TA = 25C 0.1 VCC = 3.6 V to 18 V, TA = 25C TA = full range g TA = 25C IOH = 16 mA IOL = 16 mA Iref = 500 A, TA = 25C VCC1.5 0.4 2.48 2.505 3.03 4.5 2.48 3 4.45 2.53 2.53 3.08 4.55 2.53 3.08 4.55 10 10 30 1 10 2 50 50 3 V A A A mA mV 2.58 2.555 3.13 4.6 2.58 3.16 4.65 V TYP MAX V V V UNIT

High-level output current, RESET Low-level output current, RESET Supply current

3.5 VCC = 18 V, TA = full range All electrical characteristics are measured with 0.1-F capacitors connected at REF, CT, and VCC to GND. Full range is 0C to 70C for the C-suffix devices, 40C to 85C for the I-suffix devices, and 40C to 125C for the Q-suffix device. This is the lowest voltage at which RESET becomes active.

switching characteristics, VCC = 5 V, CT open, TA = 25C

PARAMETER FROM (INPUT) ( ) TO (OUTPUT) ( ) TEST CONDITIONS TL77xxBC TL77xxBI TL7705BQ MIN tPLH tPHL tw tr tf tr tf Propagation delay time from low- to high-level output Propagation delay time from high- to low-level output Effective pulse duration Rise time Fall time Rise time Fall time RESET See Figures 1 and 3 RESET 150 75 RESIN RESIN RESIN SENSE RESET 1 2, 2 and 3 See Figures 1, RESET See Figure 2 270 150 100 75 200 150 50 500 ns ns ns ns TYP 270 MAX 500 ns UNIT

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TL7702B, TL7705B, TL7733B SUPPLY-VOLTAGE SUPERVISORS

SLVS037K SEPTEMBER 1989 REVISED APRIL 2002

electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER VOH VOL Vref High-level output voltage, RESET Low-level output voltage, RESET Reference voltage TL7702B VIT Negative-going input threshold voltage input at SENSE in ut Hysteresis, y , SENSE (VIT+ VIT) Power-up reset voltage Input current RESIN SENSE TL7702B TL7705B TL7702B TL7705B Vh hys Vres II IOH IOL ICC TL7702B TL7705B TEST CONDITIONS IOH = 16 mA IOL = 16 mA Iref = 500 A, TA = 25C TA = 55C to 125C VCC = 3 3.6 6 V to 18 V, V IOL at RESET = 2 mA, VI = 0.4 V to VCC VI = Vref to VCC 1.5 V VO = 18 V VO = 0 VSENSE = 15 V, Supply current VCC = 18 V, RESIN 2 V TA = 55C to 125C 1.8 TA = 25C TA = 25C 0.1 TA = 25C TL7705BM MIN VCC1.5 0.4 2.48 2.505 4.5 2.48 4.45 2.53 2.53 4.55 2.53 4.55 10 30 1 10 2 50 50 3 mA 4 2.58 2.555 4.6 2.58 4.65 mV V A A A V TYP MAX UNIT V V V

High-level output current, RESET Low-level output current, RESET

All electrical characteristics are measured with 0.1-F capacitors connected at REF, CT, and VCC to GND. This is the lowest value at which RESET becomes active.

switching characteristics, VCC = 5 V, CT open, TA = 25C

PARAMETER tPLH tPHL tw tr tf tr tf Propagation delay time from low- to high-level output Propagation delay time from high- to low-level output Effective pulse duration Rise time Fall time Rise time Fall time RESET See Figures 1 and 3 RESET 150 75 FROM (INPUT) RESIN RESIN RESIN SENSE TO (OUTPUT) RESET See Figures 1, 1 2, 2 and 3 RESET See Figure 2 270 150 100 75* 200* 150* 50* 500* ns ns ns ns TEST CONDITIONS TL7705BM MIN TYP 270 MAX 500* UNIT ns

* On products compliant to MIL-PRF-38535, these parameters are not production tested.

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TL7702B, TL7705B, TL7733B SUPPLY-VOLTAGE SUPERVISORS

SLVS037K SEPTEMBER 1989 REVISED APRIL 2002

PARAMETER MEASUREMENT INFORMATION

5V RL (see Note A) RESET DUT 15 pF (see Note B) GND RESET RL (see Note A) 15 pF (see Note B) 5V VCC DUT

RESET OUTPUT CONFIGURATION

RESET OUTPUT CONFIGURATION

NOTES: A. For IOL and IOH, RL = 10 k. For all switching characteristics, RL = 511 . B. This figure includes jig and probe capacitance.

Figure 1. RESET and RESET Output Configurations

tw 5V 2.5 V 0V RESIN WAVEFORMS

tw

VT + 2 V VT VT 2 V

SENSE

Figure 2. Input Pulse Definition

Voltage Fault VIT+ VIT VIT+ 0V VIH RESIN Undefined 0.8 V tf 90% RESET 10% td 90% RESET 10% tr 10% 10% tPHL 50% 10% V OL tf td tr tPLH 90% 50% 90% VOH 2V VIL

SENSE

td

Figure 3. Voltage Waveforms

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TL7702B, TL7705B, TL7733B SUPPLY-VOLTAGE SUPERVISORS

SLVS037K SEPTEMBER 1989 REVISED APRIL 2002

TYPICAL CHARACTERISTICS
ASSERTION TIME vs LOAD RESISTANCE
20 18 VCC = 5 V CT = 0.1 F CL = 10 pF TA = 25C RESET tr 14 12 700 600 t Deassertion Time ns VCC = 5 V CT = 0.1 F CL = 10 pF TA = 25C RESET tr

DEASSERTION TIME vs LOAD RESISTANCE

t Assertion Time ns

16

500 RESET tf 400 300 RESET tf 200 100 RESET tr

10 8

RESET tf

10

10

RL Load Resistance k

RL Load Resistance k

Figure 4
ASSERTION TIME vs LOAD CAPACITANCE
36 VCC = 5 V CT = 0.1 F RL = 4.7 k TA = 25C 2.1 1.9 t Deassertion Time s 1.7 1.5 1.3 1.1

Figure 5
DEASSERTION TIME vs LOAD CAPACITANCE
VCC = 5 V CT = 0.1 F RL = 4.7 k TA = 25C

30 t Assertion Time ns

24 RESET tr 18 RESET tf 12

RESET tf and RESET tr 0.9 0.7 0.5

6 0 25 50 75 100 125 150 175 200 CL Load Capacitance pF

0.3 0 25 50 75 100 125 150 175 200 CL Load Capacitance pF

Figure 6

Figure 7

For proper operation, both RESET and RESET should be terminated with resistors of similar value. Failure to do so may cause unwanted plateauing in either output waveform during switching.

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TL7702B, TL7705B, TL7733B SUPPLY-VOLTAGE SUPERVISORS

SLVS037K SEPTEMBER 1989 REVISED APRIL 2002

APPLICATION INFORMATION
VS 8 7 Reset Input (from system) 2 RESIN 1 REF RT 3 CT (see text) 0.1 F CT RESET GND 4 6 10 k To System RESET VCC SENSE RESET 5 10 k To System RESET System Supply

Figure 8. System Reset Controller With Undervoltage Sensing When the TL770xB SENSE terminal is used to monitor VCC, a current-limiting resistor in series with CT is recommended. During normal operation, the timing capacitor is charged by the onboard current source to approximately VCC or an internal voltage clamp (7.1-V zener), whichever is less. When the circuit is then subjected to an undervoltage condition during which VCC is rapidly slewed down, the voltage on CT exceeds that on VCC. This forward biases a secondary path internally, which falsely activates the outputs. A fault is indicated when VCC drops below V(CT), not when VSENSE falls below VT. Texas Instruments performs a 100% electrical screen to verify that the outputs do not switch with 1 mA forced into the CT terminal. Adding the external resistor, RT, prevents false triggering. Its value is calculated as follows: V (CT)

*V *
T

RT Where: V(CT) = VCC or 7.1 V, whichever is less VT = 4.55 V (nom) RT = value of series resistor required For VCC = 5 V: 5
T

* 4.55 t 1 mA R u 450 W

Therefore, RT

Using a 20%-tolerance resistor, RT should be greater than 560 . Adding this series resistor changes the duration of the reset pulse by no more than 10%. RT extends the discharge of CT, but also skews the V(CT) threshold. These effects tend to cancel one another. The precise percentage change can be derived theoretically, but the equation is complicated by this interaction and is dependent upon the duration of the supply-voltage fault condition. Both outputs of the TL770xB should be terminated with similar value resistors, even when only one is being used. This prevents unwanted plateauing in either output waveform during switching, which may be interpreted as an undefined state or delay system reset.

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